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Development of Scalable Electrical Models for High-Voltage LDMOS

Development of Scalable Electrical Models for High-Voltage LDMOS

SoC BIST

SoC BIST for Transceiver Reference - J. Dabrowski, “BiST Model for IC RF-Transceiver Front-End,” Proc. 18 th IEEE International Symp. on Defect and Fault Tolerance in VLSI Systems, 2003. 34

SoC Transceiver BIST • Test implemented at baseband. • Loopback between A/D and D/A converters. • DSP implemented with digital BIST. • Test amplifier (TA) implemented on chip; is disabled during normal operation. • A test procedure: – Test DSP using digital BIST. – Apply RF BIST: • Pseudorandom bit sequence generated by DSP • Up converted by transmitter chain and applied to receiver through TA • Down converted signal compared to input bit sequence by DSP to • analyze bit error rate (BER) • BER correlated to relevant characteristics of SOC components • Advantage: Low tester cost. Disadvantage: Poor diagnosis. 35

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