Views
3 years ago

Power ISA™ Version 2.03 - Power.org

Power ISA™ Version 2.03 - Power.org

Power ISA™ Version 2.03 -

® Power ISA Version 2.03 September 29, 2006

  • Page 2 and 3: Version 2.03 The following paragrap
  • Page 4 and 5: Version 2.03 iv Power ISA
  • Page 6 and 7: Version 2.03 3.3 Fixed-Point Proces
  • Page 8 and 9: Version 2.03 7.2 Programming Model.
  • Page 10 and 11: Version 2.03 3.3.4 Wait Instruction
  • Page 12 and 13: Version 2.03 7.5 Processor Utilizat
  • Page 14 and 15: Version 2.03 5.6.19 Embedded Floati
  • Page 16 and 17: Version 2.03 E.2.2 Processor Contex
  • Page 18 and 19: Version 2.03 Appendix B. Platform S
  • Page 20 and 21: Version 2.03 2. [Category: Server]
  • Page 22 and 23: Version 2.03 xxii Power ISA
  • Page 24 and 25: Version 2.03 2 Power ISA -- Book I
  • Page 26 and 27: Version 2.03 applicati
  • Page 28 and 29: Version 2.03 Programming Note It is
  • Page 30 and 31: Version 2.03 1.3.5 Categories Each
  • Page 32 and 33: Version 2.03 1.4 Processor Overview
  • Page 34 and 35: Version 2.03 1.5 Computation modes
  • Page 36 and 37: Version 2.03 1.6.7 XL-FORM 0 6 11 1
  • Page 38 and 39: Version 2.03 FRA (11:15) Field used
  • Page 40 and 41: Version 2.03 in an efficient manner
  • Page 42 and 43: Version 2.03 struct { int a; /* 0x1
  • Page 44 and 45: Version 2.03 second is a signed off
  • Page 46 and 47: Version 2.03 2.3 Branch Processor R
  • Page 48 and 49: Version 2.03 provides a hint about
  • Page 50 and 51: Version 2.03 Compatibility Note The
  • Page 52 and 53:

    Version 2.03 Branch Conditional to

  • Page 54 and 55:

    Version 2.03 Condition Register NOR

  • Page 56 and 57:

    Version 2.03 34 Power ISA -- Book I

  • Page 58 and 59:

    Version 2.03 3.2 Fixed-Point Proces

  • Page 60 and 61:

    Version 2.03 3.3 Fixed-Point Proces

  • Page 62 and 63:

    Version 2.03 Load Halfword and Zero

  • Page 64 and 65:

    Version 2.03 Load Word and Zero D-f

  • Page 66 and 67:

    Version 2.03 Load Doubleword DS-for

  • Page 68 and 69:

    Version 2.03 Store Halfword D-form

  • Page 70 and 71:

    Version 2.03 3.3.3.1 64-bit Fixed-P

  • Page 72 and 73:

    Version 2.03 3.3.5 Fixed-Point Load

  • Page 74 and 75:

    Version 2.03 Load String Word Immed

  • Page 76 and 77:

    Version 2.03 3.3.7 Other Fixed-Poin

  • Page 78 and 79:

    Version 2.03 Add XO-form Subtract F

  • Page 80 and 81:

    Version 2.03 Add Extended XO-form S

  • Page 82 and 83:

    Version 2.03 Multiply Low Immediate

  • Page 84 and 85:

    Version 2.03 3.3.8.1 64-bit Fixed-P

  • Page 86 and 87:

    Version 2.03 3.3.9 Fixed-Point Comp

  • Page 88 and 89:

    Version 2.03 3.3.10 Fixed-Point Tra

  • Page 90 and 91:

    Version 2.03 3.3.12 Fixed-Point Log

  • Page 92 and 93:

    Version 2.03 AND X-form OR X-form a

  • Page 94 and 95:

    Version 2.03 Extend Sign Byte X-for

  • Page 96 and 97:

    Version 2.03 3.3.13 Fixed-Point Rot

  • Page 98 and 99:

    Version 2.03 Rotate Left Word then

  • Page 100 and 101:

    Version 2.03 Rotate Left Doubleword

  • Page 102 and 103:

    Version 2.03 3.3.13.2 Fixed-Point S

  • Page 104 and 105:

    Version 2.03 3.3.13.2.1 64-bit Fixe

  • Page 106 and 107:

    Version 2.03 Move From Special Purp

  • Page 108 and 109:

    Version 2.03 Move To One Condition

  • Page 110 and 111:

    Version 2.03 88 Power ISA -- Book I

  • Page 112 and 113:

    Version 2.03 Reciprocal Estimate in

  • Page 114 and 115:

    Version 2.03 39 Floating-Point Inva

  • Page 116 and 117:

    Version 2.03 mats can be specified

  • Page 118 and 119:

    Version 2.03 mented by one. For the

  • Page 120 and 121:

    Version 2.03 RN Rounding Mode 00 Ro

  • Page 122 and 123:

    Version 2.03 before the instruction

  • Page 124 and 125:

    Version 2.03 1. Overflow Exception

  • Page 126 and 127:

    Version 2.03 IEEE-conforming signif

  • Page 128 and 129:

    Version 2.03 4.6 Floating-Point Pro

  • Page 130 and 131:

    Version 2.03 Load Floating-Point Do

  • Page 132 and 133:

    Version 2.03 Store Floating-Point S

  • Page 134 and 135:

    Version 2.03 Store Floating-Point a

  • Page 136 and 137:

    Version 2.03 4.6.5 Floating-Point A

  • Page 138 and 139:

    Version 2.03 Floating Square Root [

  • Page 140 and 141:

    Version 2.03 4.6.5.2 Floating-Point

  • Page 142 and 143:

    Version 2.03 4.6.6 Floating-Point R

  • Page 144 and 145:

    Version 2.03 Floating Convert To In

  • Page 146 and 147:

    Version 2.03 4.6.7 Floating-Point C

  • Page 148 and 149:

    Version 2.03 Move From FPSCR X-form

  • Page 150 and 151:

    Version 2.03 128 Power ISA -- Book

  • Page 152 and 153:

    Version 2.03 5.1 Vector Processor O

  • Page 154 and 155:

    Version 2.03 tor unit, meaning that

  • Page 156 and 157:

    Version 2.03 5.4.1 Accessing Unalig

  • Page 158 and 159:

    Version 2.03 Borderline cases that

  • Page 160 and 161:

    Version 2.03 3. If the instruction

  • Page 162 and 163:

    Version 2.03 Load Vector Element Wo

  • Page 164 and 165:

    Version 2.03 Store Vector Element W

  • Page 166 and 167:

    Version 2.03 5.8 Vector Permute and

  • Page 168 and 169:

    Version 2.03 Vector Pack Unsigned H

  • Page 170 and 171:

    Version 2.03 Vector Unpack Low Pixe

  • Page 172 and 173:

    Version 2.03 Vector Merge Low Byte

  • Page 174 and 175:

    Version 2.03 5.8.4 Vector Permute I

  • Page 176 and 177:

    Version 2.03 Vector Shift Right VX-

  • Page 178 and 179:

    Version 2.03 Vector Add Unsigned By

  • Page 180 and 181:

    Version 2.03 5.9.1.2 Vector Integer

  • Page 182 and 183:

    Version 2.03 Vector Subtract Unsign

  • Page 184 and 185:

    Version 2.03 Vector Multiply Odd Si

  • Page 186 and 187:

    Version 2.03 Vector Multiply-Sum Un

  • Page 188 and 189:

    Version 2.03 Vector Multiply-Sum Un

  • Page 190 and 191:

    Version 2.03 Vector Sum across Quar

  • Page 192 and 193:

    Version 2.03 Vector Average Unsigne

  • Page 194 and 195:

    Version 2.03 Vector Maximum Unsigne

  • Page 196 and 197:

    Version 2.03 Vector Minimum Unsigne

  • Page 198 and 199:

    Version 2.03 Vector Compare Equal T

  • Page 200 and 201:

    Version 2.03 5.9.3 Vector Logical I

  • Page 202 and 203:

    Version 2.03 Vector Shift Left Byte

  • Page 204 and 205:

    Version 2.03 Vector Shift Right Byt

  • Page 206 and 207:

    Version 2.03 Vector Multiply-Add Si

  • Page 208 and 209:

    Version 2.03 5.10.3 Vector Floating

  • Page 210 and 211:

    Version 2.03 Vector Round to Single

  • Page 212 and 213:

    Version 2.03 Vector Compare Greater

  • Page 214 and 215:

    Version 2.03 Vector Reciprocal Esti

  • Page 216 and 217:

    Version 2.03 194 Power ISA -- Book

  • Page 218 and 219:

    Version 2.03 ea 0:31 = EXTS(a) eb 0

  • Page 220 and 221:

    Version 2.03 set to 1. That is, FUN

  • Page 222 and 223:

    Version 2.03 6.3.6 Computational Op

  • Page 224 and 225:

    Version 2.03 6.3.9 SPE Instruction

  • Page 226 and 227:

    Version 2.03 Vector AND EVX-form Ve

  • Page 228 and 229:

    Version 2.03 Vector Count Leading S

  • Page 230 and 231:

    Version 2.03 Vector Load Double Wor

  • Page 232 and 233:

    Version 2.03 Vector Load Halfword i

  • Page 234 and 235:

    Version 2.03 Vector Load Word into

  • Page 236 and 237:

    Version 2.03 Vector Merge High/Low

  • Page 238 and 239:

    Version 2.03 Vector Multiply Halfwo

  • Page 240 and 241:

    Version 2.03 Vector Multiply Halfwo

  • Page 242 and 243:

    Version 2.03 Vector Multiply Halfwo

  • Page 244 and 245:

    Version 2.03 Vector Multiply Halfwo

  • Page 246 and 247:

    Version 2.03 Vector Multiply Halfwo

  • Page 248 and 249:

    Version 2.03 Vector Multiply Halfwo

  • Page 250 and 251:

    Version 2.03 Vector Multiply Halfwo

  • Page 252 and 253:

    Version 2.03 Vector Multiply Halfwo

  • Page 254 and 255:

    Version 2.03 Vector Multiply Word H

  • Page 256 and 257:

    Version 2.03 Vector Multiply Word L

  • Page 258 and 259:

    Version 2.03 Vector Multiply Word S

  • Page 260 and 261:

    Version 2.03 Vector Multiply Word S

  • Page 262 and 263:

    Version 2.03 Vector NOR EVX-form Ve

  • Page 264 and 265:

    Version 2.03 Vector Shift Left Word

  • Page 266 and 267:

    Version 2.03 Vector Store Double of

  • Page 268 and 269:

    Version 2.03 Vector Store Word of W

  • Page 270 and 271:

    Version 2.03 248 Power ISA -- Book

  • Page 272 and 273:

    Version 2.03 7.2 Programming Model

  • Page 274 and 275:

    Version 2.03 interrupt is then take

  • Page 276 and 277:

    Version 2.03 Vector Floating-Point

  • Page 278 and 279:

    Version 2.03 Vector Floating-Point

  • Page 280 and 281:

    Version 2.03 Vector Convert Floatin

  • Page 282 and 283:

    Version 2.03 Vector Convert Floatin

  • Page 284 and 285:

    Version 2.03 Floating-Point Single-

  • Page 286 and 287:

    Version 2.03 Floating-Point Single-

  • Page 288 and 289:

    Version 2.03 Convert Floating-Point

  • Page 290 and 291:

    Version 2.03 7.3.4 SPE.Embedded Flo

  • Page 292 and 293:

    Version 2.03 Floating-Point Double-

  • Page 294 and 295:

    Version 2.03 Convert Floating-Point

  • Page 296 and 297:

    Version 2.03 Convert Floating-Point

  • Page 298 and 299:

    Version 2.03 Floating-Point Single-

  • Page 300 and 301:

    Version 2.03 Table 3: Embedded Floa

  • Page 302 and 303:

    Version 2.03 Table 4: Embedded Floa

  • Page 304 and 305:

    Version 2.03 282 Power ISA -- Book

  • Page 306 and 307:

    Version 2.03 284 Power ISA -- Book

  • Page 308 and 309:

    Version 2.03 Multiply Accumulate Cr

  • Page 310 and 311:

    Version 2.03 Multiply Accumulate Hi

  • Page 312 and 313:

    Version 2.03 Multiply Accumulate Lo

  • Page 314 and 315:

    Version 2.03 Negative Multiply Accu

  • Page 316 and 317:

    Version 2.03 Negative Multiply Accu

  • Page 318 and 319:

    Version 2.03 FRT 0 sign FRT 1:63

  • Page 320 and 321:

    Version 2.03 SNaN Operand: FPSCR VX

  • Page 322 and 323:

    Version 2.03 Round Integer(sign,fra

  • Page 324 and 325:

    Version 2.03 A.3 Floating-Point Con

  • Page 326 and 327:

    Version 2.03 Infinity Operand: FRT

  • Page 328 and 329:

    Version 2.03 ConvertUXWtoSP( X ) ex

  • Page 330 and 331:

    Version 2.03 C.2 Convert from Singl

  • Page 332 and 333:

    Version 2.03 C.4 Convert from Doubl

  • Page 334 and 335:

    Version 2.03 C.7 Convert to Double-

  • Page 336 and 337:

    Version 2.03 any of these four basi

  • Page 338 and 339:

    Version 2.03 4. Same as (3), but ta

  • Page 340 and 341:

    Version 2.03 D.5.2 Word Comparisons

  • Page 342 and 343:

    Version 2.03 D.7 Rotate and Shift M

  • Page 344 and 345:

    Version 2.03 D.8 Move To/From Speci

  • Page 346 and 347:

    Version 2.03 324 Power ISA -- Book

  • Page 348 and 349:

    Version 2.03 Multiple-precision shi

  • Page 350 and 351:

    Version 2.03 E.2 Floating-Point Con

  • Page 352 and 353:

    Version 2.03 E.3 Floating-Point Sel

  • Page 354 and 355:

    Version 2.03 332 Power ISA -- Book

  • Page 356 and 357:

    Version 2.03 334 Power ISA -- Book

  • Page 358 and 359:

    Version 2.03 - instruction fe

  • Page 360 and 361:

    Version 2.03 The processor is not r

  • Page 362 and 363:

    Version 2.03 Programming Note In so

  • Page 364 and 365:

    Version 2.03 Programming Note Becau

  • Page 366 and 367:

    Version 2.03 ified by another proce

  • Page 368 and 369:

    Version 2.03 Case 1: The given prog

  • Page 370 and 371:

    Version 2.03 348 Power ISA -- Book

  • Page 372 and 373:

    Version 2.03 Operand Boundary Cross

  • Page 374 and 375:

    Version 2.03 3.2.1 Instruction Cach

  • Page 376 and 377:

    Version 2.03 Programming Note New p

  • Page 378 and 379:

    Version 2.03 Programming Note To ob

  • Page 380 and 381:

    Version 2.03 Data Cache Block Touch

  • Page 382 and 383:

    Version 2.03 Data Cache Block Flush

  • Page 384 and 385:

    Version 2.03 3.3 Synchronization In

  • Page 386 and 387:

    Version 2.03 3.3.2.1 64-bit Load an

  • Page 388 and 389:

    Version 2.03 Extended Mnemonics: Ex

  • Page 390 and 391:

    Version 2.03 Programming Note The f

  • Page 392 and 393:

    Version 2.03 4.2.1 Time Base Instru

  • Page 394 and 395:

    Version 2.03 4.3 Alternate Time Bas

  • Page 396 and 397:

    Version 2.03 5.1 External Access In

  • Page 398 and 399:

    Version 2.03 376 Power ISA -- Book

  • Page 400 and 401:

    Version 2.03 Fetch and Add The “F

  • Page 402 and 403:

    Version 2.03 B.2.2 Lock Release and

  • Page 404 and 405:

    Version 2.03 382 Power ISA -- Book

  • Page 406 and 407:

    Version 2.03 384 Power ISA -- Book

  • Page 408 and 409:

    Version 2.03 Check interrupt. (Th

  • Page 410 and 411:

    Version 2.03 388 Power ISA -- Book

  • Page 412 and 413:

    Version 2.03 60:61 Logical Partitio

  • Page 414 and 415:

    Version 2.03 are identical among al

  • Page 416 and 417:

    Version 2.03 49 Problem State (PR)

  • Page 418 and 419:

    Version 2.03 Return From Interrupt

  • Page 420 and 421:

    Version 2.03 4.3.2 Processor Identi

  • Page 422 and 423:

    Version 2.03 4.4 Fixed-Point Proces

  • Page 424 and 425:

    Version 2.03 decimal SPR 1 Register

  • Page 426 and 427:

    Version 2.03 Move To Machine State

  • Page 428 and 429:

    Version 2.03 Move From Machine Stat

  • Page 430 and 431:

    Version 2.03 5.2 Storage Exceptions

  • Page 432 and 433:

    Version 2.03 Programming Note Treat

  • Page 434 and 435:

    Version 2.03 Programming Note The p

  • Page 436 and 437:

    Version 2.03 For each SLB entry, so

  • Page 438 and 439:

    Version 2.03 5.7.6.1 Page Table The

  • Page 440 and 441:

    Version 2.03 5.7.6.2 Storage Descri

  • Page 442 and 443:

    Version 2.03 5.7.7 Reference and Ch

  • Page 444 and 445:

    Version 2.03 5.7.8 Storage Protecti

  • Page 446 and 447:

    Version 2.03 Bit Storage Control At

  • Page 448 and 449:

    Version 2.03 Table Entries (PTEs);

  • Page 450 and 451:

    Version 2.03 SLB Move To Entry slbm

  • Page 452 and 453:

    Version 2.03 5.9.3.2 Bridge to SLB

  • Page 454 and 455:

    Version 2.03 Move From Segment Regi

  • Page 456 and 457:

    Version 2.03 TLB Invalidate Entry L

  • Page 458 and 459:

    Version 2.03 5.10 Page Table Update

  • Page 460 and 461:

    Version 2.03 5.10.1.2 Modifying a P

  • Page 462 and 463:

    Version 2.03 restore machine state

  • Page 464 and 465:

    Version 2.03 6.4.3 Interrupt Proces

  • Page 466 and 467:

    Version 2.03 In order to handle Mac

  • Page 468 and 469:

    Version 2.03 6.5.1 System Reset Int

  • Page 470 and 471:

    Version 2.03 If a Move Assist instr

  • Page 472 and 473:

    Version 2.03 For an X-form Load or

  • Page 474 and 475:

    Version 2.03 SRR0 Set to the effect

  • Page 476 and 477:

    Version 2.03 6.7 Exception Ordering

  • Page 478 and 479:

    Version 2.03 These exceptions are t

  • Page 480 and 481:

    Version 2.03 Programming Note If so

  • Page 482 and 483:

    Version 2.03 The PURR is implemente

  • Page 484 and 485:

    Version 2.03 8.1.2 Data Address Bre

  • Page 486 and 487:

    Version 2.03 464 Power ISA -- Book

  • Page 488 and 489:

    Version 2.03 466 Power ISA -- Book

  • Page 490 and 491:

    Version 2.03 Instruction or Event R

  • Page 492 and 493:

    Version 2.03 ing the ptesync instru

  • Page 494 and 495:

    Version 2.03 Table 3: Extended mnem

  • Page 496 and 497:

    Version 2.03 an MMCR. A single Pe

  • Page 498 and 499:

    Version 2.03 MMCRA, controls the op

  • Page 500 and 501:

    Version 2.03 Programming Note Softw

  • Page 502 and 503:

    Version 2.03 B.3 Performance Monito

  • Page 504 and 505:

    Version 2.03 482 Power ISA -- Book

  • Page 506 and 507:

    Version 2.03 then it is either X- f

  • Page 508 and 509:

    Version 2.03 486 Power ISA -- Book

  • Page 510 and 511:

    Version 2.03 interrupt The act of

  • Page 512 and 513:

    Version 2.03 490 Power ISA -- Book

  • Page 514 and 515:

    Version 2.03 46 Critical Enable (CE

  • Page 516 and 517:

    Version 2.03 Return From Critical I

  • Page 518 and 519:

    Version 2.03 496 Power ISA -- Book

  • Page 520 and 521:

    Version 2.03 privileged; write acce

  • Page 522 and 523:

    Version 2.03 3.3.4.2 External Proce

  • Page 524 and 525:

    Version 2.03 decimal SPR 1 Register

  • Page 526 and 527:

    Version 2.03 Move From Special Purp

  • Page 528 and 529:

    Version 2.03 Write MSR External Ena

  • Page 530 and 531:

    Version 2.03 Load Word by External

  • Page 532 and 533:

    Version 2.03 Store Word by External

  • Page 534 and 535:

    Version 2.03 . Extended: Equivalent

  • Page 536 and 537:

    Version 2.03 Instruction Cache Bloc

  • Page 538 and 539:

    Version 2.03 Vector Load Doubleword

  • Page 540 and 541:

    Version 2.03 Store Vector by Extern

  • Page 542 and 543:

    Version 2.03 4.3 Instruction Fetch

  • Page 544 and 545:

    Version 2.03 write portions of indi

  • Page 546 and 547:

    Version 2.03 The virtual address of

  • Page 548 and 549:

    Version 2.03 4.7.3 Address Translat

  • Page 550 and 551:

    Version 2.03 dcbf, dcbfep, dcbst, a

  • Page 552 and 553:

    Version 2.03 Load or Store instru

  • Page 554 and 555:

    Version 2.03 4.9 Storage Control In

  • Page 556 and 557:

    Version 2.03 be loaded are already

  • Page 558 and 559:

    Version 2.03 Instruction Cache Bloc

  • Page 560 and 561:

    Version 2.03 4.9.4.1 TLB Management

  • Page 562 and 563:

    Version 2.03 TLB Write Entry X-form

  • Page 564 and 565:

    Version 2.03 5.9.1.2 Exception Prio

  • Page 566 and 567:

    Version 2.03 5.2.7 Data Exception A

  • Page 568 and 569:

    Version 2.03 Programming Note The i

  • Page 570 and 571:

    Version 2.03 5.3 Exceptions There a

  • Page 572 and 573:

    Version 2.03 Check interrupts) will

  • Page 574 and 575:

    Version 2.03 5.6 Interrupt Definiti

  • Page 576 and 577:

    Version 2.03 6. The precision of th

  • Page 578 and 579:

    Version 2.03 DEAR Set to the effect

  • Page 580 and 581:

    Version 2.03 5.6.7 Program Interrup

  • Page 582 and 583:

    Version 2.03 MSR CM MSR CM is set t

  • Page 584 and 585:

    Version 2.03 SRR0 SRR1 Set to the e

  • Page 586 and 587:

    Version 2.03 5.6.19 Embedded Floati

  • Page 588 and 589:

    Version 2.03 5.7 Partially Executed

  • Page 590 and 591:

    Version 2.03 5.8.1 Guidelines for S

  • Page 592 and 593:

    Version 2.03 Programming Note Some

  • Page 594 and 595:

    Version 2.03 572 Power ISA -- Book

  • Page 596 and 597:

    Version 2.03 TLB entry A TLB entry

  • Page 598 and 599:

    Version 2.03 Programming Note If so

  • Page 600 and 601:

    Version 2.03 If the auto-reload fea

  • Page 602 and 603:

    Version 2.03 33 Watchdog Timer Inte

  • Page 604 and 605:

    Version 2.03 3. Never take the Watc

  • Page 606 and 607:

    Version 2.03 Debug interrupts. The

  • Page 608 and 609:

    Version 2.03 effective addresses an

  • Page 610 and 611:

    Version 2.03 address match occurs.

  • Page 612 and 613:

    Version 2.03 [Category: Embedded.En

  • Page 614 and 615:

    Version 2.03 38 Interrupt Taken Deb

  • Page 616 and 617:

    Version 2.03 56:57 Instruction Addr

  • Page 618 and 619:

    Version 2.03 34:35 Most Recent Rese

  • Page 620 and 621:

    Version 2.03 8.6 Debugger Notify Ha

  • Page 622 and 623:

    Version 2.03 Critical Interrupt occ

  • Page 624 and 625:

    Version 2.03 602 Power ISA -- Book

  • Page 626 and 627:

    Version 2.03 Instruction or Require

  • Page 628 and 629:

    Version 2.03 606 Power ISA -- Book

  • Page 630 and 631:

    Version 2.03 A.2 Embedded Cache Deb

  • Page 632 and 633:

    Version 2.03 A.3 Embedded Cache Deb

  • Page 634 and 635:

    Version 2.03 612 Power ISA -- Book

  • Page 636 and 637:

    Version 2.03 B.1 Move To/From Speci

  • Page 638 and 639:

    Version 2.03 616 Power ISA -- Book

  • Page 640 and 641:

    Version 2.03 TLB entry contains eff

  • Page 642 and 643:

    Version 2.03 0 Instructions fetched

  • Page 644 and 645:

    Version 2.03 Table 7: MAS Register

  • Page 646 and 647:

    Version 2.03 arrays that have progr

  • Page 648 and 649:

    Version 2.03 registers on the occur

  • Page 650 and 651:

    Version 2.03 TLB Search Indexed tlb

  • Page 652 and 653:

    Version 2.03 630 Power ISA -- Book

  • Page 654 and 655:

    Version 2.03 should be taken when a

  • Page 656 and 657:

    Version 2.03 35:63 Reserved The UPM

  • Page 658 and 659:

    Version 2.03 E.4 Performance Monito

  • Page 660 and 661:

    Version 2.03 638 Power ISA -- Book

  • Page 662 and 663:

    Version 2.03 640 Power ISA -- Book

  • Page 664 and 665:

    Version 2.03 in Book I, Book II, an

  • Page 666 and 667:

    Version 2.03 ARY (8:11) Field used

  • Page 668 and 669:

    Version 2.03 646 Power ISA -- Book

  • Page 670 and 671:

    Version 2.03 2.2 Instruction Storag

  • Page 672 and 673:

    Version 2.03 650 Power ISA -- Book

  • Page 674 and 675:

    Version 2.03 652 Power ISA -- Book

  • Page 676 and 677:

    Version 2.03 35 Summary overflow (S

  • Page 678 and 679:

    Version 2.03 Branch [and Link] BD24

  • Page 680 and 681:

    Version 2.03 4.3 System Linkage Ins

  • Page 682 and 683:

    Version 2.03 Return From Interrupt

  • Page 684 and 685:

    Version 2.03 Condition Register OR

  • Page 686 and 687:

    Version 2.03 Load Byte and Zero D-f

  • Page 688 and 689:

    Version 2.03 Load Word and Zero wit

  • Page 690 and 691:

    Version 2.03 Store Byte with Update

  • Page 692 and 693:

    Version 2.03 5.3 Fixed-Point Load a

  • Page 694 and 695:

    Version 2.03 Add Short Form RR-form

  • Page 696 and 697:

    Version 2.03 Multiply Low Scaled Im

  • Page 698 and 699:

    Version 2.03 Compare Scaled Immedia

  • Page 700 and 701:

    Version 2.03 Compare Halfword Short

  • Page 702 and 703:

    Version 2.03 5.9 Fixed-Point Logica

  • Page 704 and 705:

    Version 2.03 OR Short Form RR-form

  • Page 706 and 707:

    Version 2.03 Move from Alternate Re

  • Page 708 and 709:

    Version 2.03 Shift Left Word Immedi

  • Page 710 and 711:

    Version 2.03 5.11 Move To/From Syst

  • Page 712 and 713:

    Version 2.03 6.2 Cache Management I

  • Page 714 and 715:

    Version 2.03 7.7 Embedded Performan

  • Page 716 and 717:

    Version 2.03 Form Mode Dep. 1 Priv

  • Page 718 and 719:

    Version 2.03 Form Mode Dep. 1 Priv

  • Page 720 and 721:

    Version 2.03 Form Mode Dep. 1 Priv

  • Page 722 and 723:

    Version 2.03 Form Mode Dep. 1 Priv

  • Page 724 and 725:

    Version 2.03 Form Mode Dep. 1 Priv

  • Page 726 and 727:

    Version 2.03 Form Mode Dep. 1 Priv

  • Page 728 and 729:

    Version 2.03 Form Mode Dep. 1 Priv

  • Page 730 and 731:

    Version 2.03 Form Mode Dep. 1 Priv

  • Page 732 and 733:

    Version 2.03 Form Mode Dep. 1 Priv

  • Page 734 and 735:

    Version 2.03 Form Mode Dep. 1 Priv

  • Page 736 and 737:

    Version 2.03 Form Mode Dep. 1 Priv

  • Page 738 and 739:

    Version 2.03 Form Mode Dep. 1 Priv

  • Page 740 and 741:

    Version 2.03 Form Mode Dep. 1 Priv

  • Page 742 and 743:

    Version 2.03 Form Mode Dep. 1 Priv

  • Page 744 and 745:

    Version 2.03 Form Mode Dep. 1 Priv

  • Page 746 and 747:

    Version 2.03 Form Mode Dep. 1 Priv

  • Page 748 and 749:

    Version 2.03 726 Power ISA -- Book

  • Page 750 and 751:

    Version 2.03 bits”.) POWER-compat

  • Page 752 and 753:

    Version 2.03 registers are altered

  • Page 754 and 755:

    Version 2.03 A.30 Deleted Instructi

  • Page 756 and 757:

    Version 2.03 A.32.5 Deleted Instruc

  • Page 758 and 759:

    Version 2.03 Category Server Platfo

  • Page 760 and 761:

    Version 2.03 decimal SPR 1 Register

  • Page 762 and 763:

    Version 2.03 740 Power ISA -- Book

  • Page 764 and 765:

    Version 2.03 742 Power ISA -- Book

  • Page 766 and 767:

    Version 2.03 744 Power ISA -- Book

  • Page 768 and 769:

    Version 2.03 Table 1: Primary opcod

  • Page 770 and 771:

    Version 2.03 Power ISA -- Book Appe

  • Page 772 and 773:

    Version 2.03 Power ISA -- Book Appe

  • Page 774 and 775:

    Version 2.03 Table 6: (Left) Extend

  • Page 776 and 777:

    Version 2.03 Table 6 (Right-Center)

  • Page 778 and 779:

    Version 2.03 Table 7: (Left) Extend

  • Page 780 and 781:

    Version 2.03 Table 8: (Left) Extend

  • Page 782 and 783:

    Version 2.03 Table 9: Opcode: 31, E

  • Page 784 and 785:

    Version 2.03 Table 13:(Left) Extend

  • Page 786 and 787:

    Version 2.03 Table 14:(Left) Extend

  • Page 788 and 789:

    Version 2.03 766 Power ISA -- Book

  • Page 790 and 791:

    Version 2.03 Form Opcode Pri Ext Mo

  • Page 792 and 793:

    Version 2.03 Form Opcode Pri Ext Mo

  • Page 794 and 795:

    Version 2.03 Form Opcode Pri Ext Mo

  • Page 796 and 797:

    Version 2.03 Form Opcode Pri Ext Mo

  • Page 798 and 799:

    Version 2.03 Form Opcode Pri Ext Mo

  • Page 800 and 801:

    Version 2.03 Form Opcode Pri Ext Mo

  • Page 802 and 803:

    Version 2.03 Form Opcode Pri Ext Mo

  • Page 804 and 805:

    Version 2.03 Form Opcode Pri Ext Mo

  • Page 806 and 807:

    Version 2.03 Form Opcode Pri Ext Mo

  • Page 808 and 809:

    Version 2.03 Form Opcode Pri Ext Mo

  • Page 810 and 811:

    Version 2.03 Form Opcode Pri Ext Mo

  • Page 812 and 813:

    Version 2.03 Form Opcode Pri Ext Mo

  • Page 814 and 815:

    Version 2.03 Form Opcode Pri Ext Mo

  • Page 816 and 817:

    Version 2.03 Form Opcode Pri Ext Mo

  • Page 818 and 819:

    Version 2.03 Form Opcode Pri Ext Mo

  • Page 820 and 821:

    Version 2.03 Form Opcode Pri Ext Mo

  • Page 822 and 823:

    Version 2.03 Form Opcode Pri Ext Mo

  • Page 824 and 825:

    Version 2.03 Form Opcode Pri Ext Mo

  • Page 826 and 827:

    Version 2.03 Form Opcode Pri Ext Mo

  • Page 828 and 829:

    Version 2.03 Form Opcode Pri Ext Mo

  • Page 830 and 831:

    Version 2.03 Form Opcode Pri Ext Mo

  • Page 832 and 833:

    Version 2.03 Form Opcode Pri Ext Mo

  • Page 834 and 835:

    Version 2.03 Form Opcode Pri Ext Mo

  • Page 836 and 837:

    Version 2.03 Form Opcode Pri Ext Mo

  • Page 838 and 839:

    Version 2.03 816 Power ISA -- Book

  • Page 840 and 841:

    Version 2.03 CTRL See Control Regis

  • Page 842 and 843:

    Version 2.03 See HSRR0, HSRR1 Hyper

  • Page 844 and 845:

    Version 2.03 Decrementer 560 Extern

  • Page 846 and 847:

    Version 2.03 definition 385, 487 re

  • Page 848 and 849:

    Version 2.03 System Call interrupt

  • Page 850:

    Version 2.03 828 Power ISA

Power ISA™ Version 2.05 - Power.org
Wireless Access - Power.org
PARALLEL THREAD EXECUTION ISA VERSION 3.1
Topic Notes: MIPS ISA - Courses
PDF Version - Edwardbosworth.com
319433-017
PDF version - ARM Information Center
PDF version - ARM Information Center
PDF version - ARM Information Center
PDF version - ARM Information Center
PDF version - ARM Information Center
MPC603e RISC Microprocessor User's Manual
Volume_3b-System_Pro..
AMD Vol 1
sparc-architecture-2011-1728132