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1.5 Computation modes
1.5.1 Modes [Category: Server]
Processors provide two execution modes, 64-bit mode
and 32-bit mode. In both of these modes, instructions
that set a 64-bit register affect all 64 bits. The computational
mode controls how the effective address is interpreted,
how status bits are set, how the Link Register is
set by Branch instructions in which LK=1, and how the
Count Register is tested by Branch Conditional instructions.
Nearly all instructions are available in both
modes (the only exceptions are a few instructions that
are defined in Book III-S). In both modes, effective
address computations use all 64 bits of the relevant
registers (General Purpose Registers, Link Register,
Count Register, etc.) and produce a 64-bit result. However,
in 32-bit mode the high-order 32 bits of the computed
effective address are ignored for the purpose of
addressing storage; see Section 1.10.3 for additional
details.
1.5.2 Modes [Category: Embedded]
Processors may provide 32-bit mode, or both 64-bit
mode and 32-bit mode. The modes differ in the following
ways.
In 64-bit mode, the processor behaves as
described for 64-bit mode in the Server environment;
see Section 1.5.1.
In 32-bit mode, instructions other than SP,
SP.Embedded Float Scalar Double, and
SP.Embedded Float Vector use only the lower 32
bits of a GPR and produce a 32-bit result. Results
written to the GPRs write only the lower 32-bits
and the upper 32 bits are undefined except for
SP.Embedded Float Scalar Single instructions
which leave the upper 32-bits unchanged. SP,
SP.Embedded Float Scalar Double, and
SP.Embedded Float Vector instructions use all 64
bits of a GPR and produce a 64-bit result regardless
of the mode.
Instructions that set condition bits do so based on
the 32-bit result computed. Effective addresses
and all SPRs operate on the lower 32 bits only
unless otherwise stated. The instructions in the
64-Bit category are not necessarily available; if
they are not available, attempting to execute such
an instruction causes the system illegal instruction
error handler to be invoked.
Floating-Point and Vector instructions operate on FPRs
and VPRs, respectively, independent of modes.
1.6 Instruction formats
All instructions are four bytes long and word-aligned
(except for VLE instructions; see Book VLE). Thus,
whenever instruction addresses are presented to the
processor (as in Branch instructions) the low-order two
bits are ignored. Similarly, whenever the processor
develops an instruction address the low-order two bits
are zero.
Bits 0:5 always specify the opcode (OPCD, below).
Many instructions also have an extended opcode (XO,
below). The remaining bits of the instruction contain
one or more fields as shown below for the different
instruction formats.
The format diagrams given below show horizontally all
valid combinations of instruction fields. The diagrams
include instruction fields that are used only by instructions
defined in Book II or in Book III.
Split Field Notation
In some cases an instruction field occupies more than
one contiguous sequence of bits, or occupies one contiguous
sequence of bits that are used in permuted
order. Such a field is called a split field. In the format
diagrams given below and in the individual instruction
layouts, the name of a split field is shown in small letters,
once for each of the contiguous sequences. In the
RTL description of an instruction having a split field,
and in certain other places where individual bits of a
split field are identified, the name of the field in small
letters represents the concatenation of the sequences
from left to right. In all other places, the name of the
field is capitalized and represents the concatenation of
the sequences in some order, which need not be left to
right, as described for each affected instruction.
1.6.1 I-FORM
0 6 30 31
OPCD LI AA LK
Figure 4.
I instruction format
1.6.2 B-FORM
0 6 11 16 30 31
OPCD BO BI BD AA LK
Figure 5.
B instruction format
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Power ISA -- Book I