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MITSUBISHI MICROCOMPUTERSCONTENTSDGUIDANCEpageI ndex by Function······················································································································ ·····1 - 3Developm.ent Support Systems ...........:..........................................·························.. ·······················1-4Ordering Information··········· .. ·······························......................................;.................···················1-5Package Outlines····························································································· .. ·········· .. ············· ···1 - 7Letter Symbols for The Dynamic Parameters·········· .. ···················· .. ····················· .. ···························· '1-10Symbology··························· ......................................................................................................... '1-13Quality Assurance and Reliability Testing················ .. ······································································· '1-16Precaution in Handling MOS IC/LSls ............................................................................................... '1-18BMELPS 760 MICROCOMPUTERSM50760-XXXP/M50761-XXXP Single-Chip 4-Bit CMOS Microcomputer ....................... "2-3DMELPS 740 MICROCOMPUTERSM50740-XXXSP Single-Chip 8-Bit CMOS Microcomputer ....................... "3-3DMELPS 8-48 MICROCOMPUTERSFunctions of MELPS 8-48 Microcomputers····· .................................................................................. '4-3M5L8048-XXXP/M5L8035LP Single-Chip 8-Bit MicrocomRuter····· ..····························4-21M5L8049-XXXP, P-8, P-6/M5L8039P-11, P-8, P-6 Single-Chip 8-Bit Microcomputer'" ....·····················..·····4-25M5L8049H-XXX P/M5L8039H LPSingle-Chip 8-Bit Microcomputer······ .. ··························'4-29M5M8050H-XXXP/M5M8040H PSingle-Chip 8-Bit Microcomputer······ ............................'4-34M5M8050L-XXX P/M5M8040LPSingle-Chip 8-Bit Microcomputer······ .. · ..·············· ..·······'4-39M5M80C49-XXX P/M5M80C39P-6Single-Chip 8-Bit CMOS Microcomputer························ '4-44mMELPS 8-41SLAVE MICROCOMPUTERSFunctions of MELPS 8-41 Slave Microcomputers ...................................................... ·····,···················5-3M5L8041A-XXXP Slave microcomputer ···················· ..···························5-25M5L8042-XXXPSlave microcomputer······· .........................................'5-32DLSIS FOR PERIPHERAL CIRCUITSM50780SP/M50781SP/M50782SP/M50783SP Input/Output Expander·················· ..·························"6-3M50784SP Input Expander················ ..............................................................................········6-9M50786SP InputlOutput Expander ...........................................................................................'6-11M50790SP Input/Output Expander···················· ..··································;······..···· ..····················'6-16M5L8243P Input/Output Expander ...........................................................................................'6-26M5M82C43P Input/Output Expander ...........................................................................·················6-32M5L8155P 2048-Bit Static RAM with 1/0 Ports and Timer···· .........................................................."6-39M5L8156P 2048-Bit Static RAM with 1/0 Ports and Timer··························· .................................····6-47DMICROCOMPUTER SUPPORT SYSTEMSPC4000PC9000PC9100PC9001CPMPC9004PC9005PCA4040PCA4060PCA4340PCA4360Debugging Machine .......................................................········································7-3Cross Assembler Machine···························································· .. ··························7-716-Bit CPU Softwear Development System ......................................................·············7-10CP/M Software for PC9000···,················································· .. ···· .. ··························7-14Interface Cable Between PC9000 and PC4000 ..············································..·· .. ···· ..·····7-16Printer Interface Cable····················· ..··············································..····················· 7 -17MELPS 740 Dedicated Board(M50740-XXXSP, M50741-XXXSP)········ ..···· ..··· ..·····················7-18MELPS 760 Dedicated Board ( M50760-XXXP, M50761-XXXP) ............................................ 7-20MELPS 740 Evaluation Board(M50740-XXXSP, M50741-XXXSP) ············· .. ··························7-22MELPS 760 Evaluation Board(M50760-XXXP, M50761-XXXP) ················.. ········..················7-23:;'.MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSCONTENTStoPCAS400'PCA8403MELPS 8-48 Dedicated Board ...................................................... ·····························7-24MELPS 8-48 Evaluation Board ...................................................... ·····························7-26mAPPENDICESMELPS 760 Mask ROM Ordering Method ...................................................... ···································8-3MELPS 740 Mask ROM Ordering Method ...................................................... ···································8-5MELPS 8-48 Mask ROM Ordering Method ...................................................... ···························:······8-7MELPS 8-41 Mask ROM Ordering Method ...................................................... ··································8-10Contact Address for Further Information• MITSUBISHI.... ELECTRIC


GUIDANCE D


MITSl,JBISHI MICROCOMPUTERSINDEX BY FUNCTIONElectrical characteristicsSupply Typ Max. Min Max.Type Circuit function and organization Structure voltage pwr access cycle fre- Package(V) dissipation time time quency(mW) (ns) (ns) (MHz)InterchangeableproductsPageII.MELPS 760 MicrocomputersMS0760-XXXPMS0761-XXX P1 K-Byte Mask-Prog. ROM0.5K-Byte Mask-Prog. ROM.MELPS 740 MicrocomputersI MS0740-XXXSP 13K-Byte Mask-Prog. ROM IC,Si 15±10% I 20I 2tLs I 4I 52P4B.MELPS 8-48 MicrocomputersMSLB04B-XXXP 1 K-Byte Mask-Prog. ROM N,Si,ED 5±10% 325MSLB03SLP External ROM Type,64-Byte RAM N,Si,ED S±10% 325MSLB049-XXXP 500MSLB049-XXXP-S 2K-Byte Mask-Prog. ROM N,Si,ED 5±10% 500MSLB049-XXXP-6 500MSLB039P,11 500MSLB039P-S External ROM Type,128-Byte RAM N,Si,ED 5±10% 500MSLB039P-6 500M5LS049H-XXXP : 2K-Byte Mask-Prog. ROM N,Si,ED 5±10% 250MSLB039HLP : External ROM Type,128-Byte RAM N,Si,ED 5±10% 250MSMSOC49-XXX P* 2K-Byte Mask-Prog. ROM C,Si S±10% 25MSMBOC39P-6 * External ROM Type,12S-Byte RAM C,Si S±10% 25MSMBOSOH-XXXP 4K-Byte Mask-Prog. ROM N,Si,ED 5±10% 350MSMB040HP * External ROM Type,256-Byte RAM N,Si,ED 5±10% 350MSMBOSOL-XXXP * 4K-Byte Mask-Prog. ROM N,Si,ED S±10% 250MSMB040LP * External ROM Type,2S6-Byte ~AM N,Si,ED S±10% 250- 2500 6 40P4 iS04S 4-21- 2500 6 40P4 iS03SL 4-21- 1360 11 iS049- 1875 8 40P4 - 4-25- 2500 6 -- 1360 11 iS039- 1875 8 40P4 - 4-25- 2500 6 iS039-6- 1360 ,.1 40P4 iS049H 4-29- 1360 11 40P4 iSO~9HL--.--~.-4-29- 2500 6 40P4 - 4-44- 2500 6 40P4 - 4-44- 1360 11 40P4 - 4-34- 1360 11 40P4 - 4-34- 2500 6 40P4 - 4-39- 2500 6 40P4 - 4-39.MELPS 8-41 Slave MicrocomputersMSLB041A-XXXP 1 K-Byte Mask-Prog. ROMMSLB042-XXXP * 2K-Byte Mask-Prog. ROM.LSls for Peripheral CircuitsMS07BOSP I/O Expander (CE="H" active) C,AI 3-14 -MS07B1SP I/O Expander (CE="H" active) C,AI 3-14 -MS07B2SP I/O Expander.(CE="L" active) C,AI 3-14 -MS07B3SP I/O Expander (CE="L" active) C,AI 3-14 -MS07B4SP Input Expander C,AI 4-14 -MS07B6SP I/O Expander (CE="L" active) C,AI 4-14 -MS0790SP I/O Expander C,AI 4-14 -MSLB243P I/O Expander N,Si,ED SV±10% -MSMB2C43P * I/O Expander C,Si SV±10% -MSLB1SSP2048-Bit Static RAM with I/OPorts and Timer (CE="L" active)N,Si,ED S ±S% 500MSLB1S6P2048-Bit Static RAM with I/OPorts and Timer (CE="W active)N,Si,ED S ±5% 500- - - 40P4B TMS102SC 6-3- - - 28P4B TMS1024C 6-3- - - 40P4B - 6-3- - - 28P4B - 6-3- - - 2SP4B - 6-9- - - 40P4B - 6-11- - - S2P4B - 6-16- - - 24P4 iB243 6-26- - - 24P4 - 6-32- - - 40P4 i815S 6-39- - - 40P4 iB1S6 6-47Note: AI=<strong>Al</strong>uminum gate. C=CMOS. ED=Enhancement depletion mode.* : New product : : Under developmentN=N-channel. P= P-channel. Si=Silicon gate.. • MITSUBISH. I.... ELECTRIC1-3


MITSUBISHI MICROCOMPUTERSDEVELOPMENT SUPPORT SYSTEMSDevelopment Support SystemsTypeCMOS MELPS4-bit 760CMOS8-bitMELPS740MS0760-XXXPMS0761-XXXPMS0740-XXXSPMS0741-XXXSPMSM80C49-XXXPMSM80C39P-6Cross-assembler unitDebugging unit/------r------+--------r--------1 Evaluation boardsHardware Software Main unit Special boardsIlh;:Iit~~i4~6ot1f,1FM'M¢'~¥$J1;1~~4,Mq':1r~~,07,4Q+~~y~jMSL8048-XXXPNMOS8-bitMELPS8-48MSL803SLPMSL8049-XXXPMSL8049-XXXP-8MSL8049-XXXP-6MSL8039P-11MSL8039P-8MSL8039P-6MSM80S0H-XXXPMSM80S0L-XXXPMSL8049H-XXXP1·~;PQA~40~;,\lI· P,C~840~,;1.P¢A~4.()3J1\:i?qA84ij~


MITSUBISHI MICROCOMPUTERSORDERING INFORMATIONFUNCTION CODEMitsubishi integrated circuits may be ordered using the following simplified alphanumeric typ-codes which define the functionof the IC/lSls and the package style.aFor Mitsubishi Original ProductsExample: M 5 07 60 - 001 P - 2T....;;:....~~~....;~-.:;=.-M: Mitsubishi integrated prefixL-----+----+-----I----l---I-Temperature range5 : Standard industrial/commercial (0 to 70175°e or -20 to 86°e).9 : High reliabilityL---l----l----I---I-Series designation using 1 or 2 alphanumeric characters.01-09 : CMOS1 : Linear circuit3 : TTL10 ..... 19 : Linear circuit32-33 : TTL (equivalent to Texas Instruments' SN74 series)41-47 : TTL81 : P-channel aluminum-gate MOS84 : COMS85 : P-channel silicon-gate MOS86 : P-channel aluminum-gate MOS87 : N-channel silicon-gate MOS88 : P-channel aluminum gate EO:"MOS89 : COMS9 : DTlSO-52 : Schottky TTL (equivalent to Texas Instruments' SN74Sseries)L----l----+---+-Circuit function identification code using 2 digits.L-_----+-_ ___+_ Mask ROM number.L---I-Package styleK : Glass-sealed ceramicP : Molded plastic5 : Metal-sealed ceramic, Electrical characteristic identification code using 1 or 2 digits.• MITSUBISHI.... ELECTRIC1-5


MITSUBISHI MICROCOMPUTERSORDERING INFORMATIONFor Second Source ProductsExample: ~ 4- _-=-- i 8041A - J!O;L -p.- -J,1M: Mitsubishi integrated circuit prefix~-+---+----+---+--+-Temperature range5 : Standard industrial/commercial (0 to 70175°C or -20 to 85°C)9 : High reliability~--+----+---+---+-Series designation of original source using 1 or 2 alphabeticalcharacters.C :. Motorola's MC seriesG : General Instrument's seriesK : Mostek's MK seriesL : Intel's seriesT : Texas Instruments' TMS seriesW : Western Digital's seriesL----+--+---t- Circuit function identification code of the original source type name'----+---+-Mask ROM number'--t-Package styleK : Glass-sealed ceramicP : Molded plasticS : Metal-sealed ceramic'--Electrical characteristic identification code using 1 or 2 digits.PACKAGE CODEPackage style may be specified by using the following simplified alphanumeric code.Example: 42 P 4 BL..--+---l----t--Number of pins'---+--+--Package structureK : Glass-sealed ceramicP : Molded plasticS : Metal-sealed ceramicL..-.-I----Package outline4 : OIL without fin (improved)10 : OIL without fin and with quartz lidOther package outlineB : Shrink OIL package1-6• MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSPACKAGE OUTLINESTYPE 20P420-PIN MOLDED PLASTIC OILDimension in mmaI 24':3; I§::::::: :0]]17 62± O. 314.5MAX1 I, '\i\ 1j~ I O.27~g:g~2. 54± 0 .250.5±0.17.6 -10TYPE 24P424-PIN MOLDED PLASTIC OILDimension in mm31. 1 ~~: ~LJ)oCI15.24 I- 0.3O. 27~~: ~~2.54 to.25-t------I--I.15.2- 17,1• MITSUBISHI.... ELECTRIC1-7


MITSUBISHI MICROCOMPUTERSPACKAGE OUTLINESTYPE 28P4B28-PIN MOLDED PLASTIC DIL( LEAD PITCH 1.78mm)Dimension in mm~~55MAX~~'8M'N1 . 78 ± O. 25 : 1 to. 3-----1----1---' ~C::Jr\.' , r10-14TYPE 40P4 40-PIN MOLDED PLASTIC DILDimension in mm51.5~~:~I- .~~ : ~ :::::::::::: ~: :~J15.24 ±O.3~5.5MAX~ '.5M'N,'·8M'N2.54±0.25 O.5±0.1.. --1.2 :~t~1 ' -- , \\. " J.I 025+ 0 . 1 '1 • _ O. 05 :15.2-171-8•.. MITSUBISHI ,.... ELECTRIC


MITSUBISHI MICROCOMPUTERSPACKAGE OUTLINESTYPE 40P4B40-PIN MOLDED PLASTIC OIL (LEAD PITCH 1.78mm)Dimension in mmII-~ 5.5MAXO.5MIN2.BMIN1.77B±O.25O.5±O.11 ~~:~! Ii E 15.2-11 :TYPE 52P4B52-PIN MOLDED PLASTIC OIL (LEAD PITCH 1.78mm)Dimension in mm45.B5~~:~1.77B±O.25IIE 15.2-17 .. II' ... MITSUBISHI.... ELECTRIC1-9


MITSUBISHI MICROCOMPUTERSLE,:lTER SYMBOLS FOR THE DYNAMIC PARAMETERS1. INTRODUCTIONA system of letter symbols to be used to represent thedynamic parameters of intergrated circuit memories andother sequential circuits especially for single-chip microcomputers,microprocessors and LSls for peripheralcircuits has been discussed internationally in the TC47of the International Electrotechnical Committee (I ECI.Finally the IEC has decided on the meeting of TC47 inFebruary 1980 that this system of letter symbols will bea Central Office document and circulated to all countriesto vote which means this system of letter symbols willbe a international standard.The system is applied in this LSI .data book for thenew products only. Future editions of this data bookwill be applied this system. The IEC document whichdescribes "Letter symbols for dynamic parameters ofsequential integrated circuits, including memories" isintrod4ced below. In this data book, the dynamic parametersin the I EC document are applied to timingrequirements and switching characteristics.2. LETTER SYMBOLSThe system of letter symbols outlined in this documentenables symbols to be generated for the dynamic parametersof complex sequential circuits, including memories,and also allows these symbols to be abbreviated tosimple mnemonic symbols when no ambiguity is likelyto arise.2.1. General FormThe dynamic parameters are represented by a generalsymbol of the form:-where:tA(BC-DC)F ...•........•.•..•.....•............• (1)Subscript A indicates the type of dynamic parameterbeing represented, for example; cycletime, setup time, enable time, etc.Subscript B indicates the name of the signal or terminalfor which a change of state or level (orestablishment of a state or level) constitutesa signal event assumed to occurfirst, that is, at the beginning of the timeinterval. If this event actually occurs last,that is, at the end of the time interval,the value of the time interval is negative.Subscript C indicates the direction of the transitionand/or the final state or level of the signalrepresented by B. When two letters areused, the initial state or level is also indicated.Subscript 0 indicates the name of the signal or terminalfor which a change of state or level (orestablishment of a state or level) constitutesa signal event assumed to occur last,that is, at the end of the time interval. Ifthis event actually occurs first, that is, atthe beginning of the time interval, thevalue of the time interval is negative.Subscript E indicates the direction of the transitionand/or the final state or level of the signalrepresented by D. When two letters areused, the initial state or level is also indicated.Subscript F indicates additional information such asmode of operation, test conditions, etc.Note 1: Subscripts A to F may each consists of one or more letters.2: Subscripts D and E are not used for transition times.3· The "-" in the symbol (1) above is used to indicate "to"; hence the symbolrepresents the time interval from signal event B occuring to signalevent D occuring, and it is important to note that this convention is usedfor all dynamic parameters including hold times. Where no misunderstandingcan occur the hyphen may be omitted.2.2. Abbreviated FormThe general symbol given above may· be abbreviatedwhen no misunderstanding is likely to arise. For exampleto:ortA(B-D)·tA(B)or tA(D) often used for hold timesor tAF no brackets are used in this caseortAor tBC-DE often used for unclassified timeintervals2.3. <strong>Al</strong>location of SubscriptsIn allocating letter symbols for the subscripts, the mostcommonly used subscripts are given single letters wherepracticable and those less commonly used are designatedby up to three letters. As far as possible, some form ofmnemonic representation is used. Longer letter symbolsmay be used for specialised signals or terminals if thisaids understanding.3. SUBSCRIPT A{For Type of Dynamic P,arameter}The subscript A represents the type of dynamic parameterto be designated by the symbol and, for memories,the parameters may be divided into two classes:a) those that are timing requirements for the memo~iand1-10 • MITSUBISHI"ELECTRIC


MITSUBISHI MICROCOMPUTERSLETTER SYMBOLS FOR THE DYNAMIC PARAMETERSb) those that are characteristics of the memory.The letter symbols so far proposed for memory circuitsare listed in sub-clauses 3.1 and 3.2 below.<strong>Al</strong>l subscripts A should be in lower-case.3.1. Timi ng RequirementsThe letter symbols for the timing requirements of semiconductormemories are as follows:Cycle timeTermTime interval between two signal eventsFall timeHold timePrecharging timeRise timeRecovery timeRefresh time intervalSetup timeTransition timePulse duration (wid~h)3.2. CharacteristicsSubscriptThe letter symbols for the dynamic characteristics ofsemiconductor memories are as follows:Access timeCharacteristicDisable timeEnable timePropagation timeRecovery timeTransition timeValid timecdhpcrecrfsuwSubscriptadisenprecNote: Recovery time for use as a characteristic is limited to sense recovery time.4. SUBSCRIPTS BAND D(For Signal Name or Terminal Name)The letter symbols for the signal name or the name ofthe terminal are as given below.<strong>Al</strong>l subscripts Band D should be in upper-case.AddressClockSignal or terminalColumn addressColumn address strobeData inputData input/outputChip enablevSubscriptACCACASDDOEErasureOutput enableProgramERData output 0ReadRRow addressRARow address strobeRefreshReadIWriteChip selectWrite (write enable)GPRRASRFRWSWNote l' In the letter symbols for time intervals, bars over the subscripts, for exampleCAS, should not be used.2: It should be noted, when further letter symbols are chosen, that the subscriptshould not end with H, K, V, X, or Z. (See clause 5)3' If the same terminal, or signal, can be used for two functions (for exampleData input/output, Read!vVrite) the waveform should be labelled with thedual function, if appropriate, but the symbols for the dynamic parametersshould include only that part of the subscript relevant to the parameter.5. SUBSCRIPTS C AND E(For Transition of Signal)The following symbols are used to represent the level orstate of a signal:High logic levelLow logic levelTransition of signalValid steady-state level (either low or high)Unknown, changing, or 'don't care' levelHigh-impedance state of three-state outputSubscriptThe direction of transition is expressed by two letters,the direction being from the state represented by thefirst letter to that represented by the second letter, withthe letters being as given above.When no misunderstanding can occur, the first lettermay be omitted to give an abbreviated symbol for subscriptsC and E as indicated below.<strong>Al</strong>l subscripts C and E should be in upper-case.ExamplesHLVXZSubscriptFull AbbreviatedTransition from high level tolow level HL LTransition from low level tohigh level LH HTransition from unknown orchanging state to valid state XV VTransition from valid state tounknown or changing state VX XTransition from high-impedancestate to valid state ZV VNote:Since subscripts C and E may be abbreviated, and since subscripts Band Dmay contain an indeterminate number of letters, it is necessary to put therestriction on the subscripts Band D that they should not end with H, L,V. X, or Z, so as to avoid possible confusion.a• MITSUBISHI..... ELECTRIC1-11


MITSUBISHI MICROCOMPUTERSLETTER SYMBOLS F,OR THE DYNAMIC PARAMETERS6. SUBSCRIPT F (For Additional Information)If necessary, subscript F is used to represent any additionalqualification of the parameter such as mode ofoperation, test conditi9ns, etc. The letter symbols forsubscript F are given below.Subscript P sltould be in upper-case.Modes of operationPower-downPage-mode readPage-mode writeReadRefreshRead-modify-writeRead-writeWriteSubscriptPOPGRPGWRRFRMWRWW-1-12• MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSSYMBOLOGYFOR DIGITAL INTEGRATED CIRCUITSNew symbol Former symbolCiInput capacitanceCoOutput capacitanceCi/oI nput/output terminal capacitanceCit¢»~I nput capacitance of clock inputfFrequencyParameter-definitionaf(¢»Clock frequencyCurrent-the current into an integrated circuit terminal is defined as a positive value and the current out of a terminal is defined as a negative valueISSISS(AV)ICCICC(AV)ICC(PD)100IDD(AV)IGGIGG(AV)IIIIHIlL10H10LlozSupply current from VBBAverage supply current from VBBSupply current from VccAvarage supply current from VccPower-down supply current from VccSupply current from VooAverage supply current from VOOSupply current from VGGA~erage supply current from VGGInput currentHigh-level input current-the value of the input current when VOH is applied to the input consideredLOW-level input current-the value of the input current when VOL is applied to the input consideredHigh-level output current-the value of the output current when VOH is applied to the output consideredLow-level output current-the value of the output current when VOL is applied to the output consideredOff-state (high-impedance statel output current-the current into an output having a three-st~te capability with input condition so applied thatit will establish according to the product specification, the off (high-impedancel state at the output10ZH10ZLlOSIssPdNEWNRARiRLROFFRONtata(A)ta(CAS)tatE)ta(G)ta(PR)ta(RAS)tats)tctCRtCRFtCPGtCRMWtcwta(AD)ta(CE)ta(OE)ta(CS)tC(RD)tc (REF)tC(PG)tC(RMR)tC(WR)Off-state (high-impedance state) output current, with high-level voltage applied to the outputOff-state (high-impedance state) output current, with lOW-level voltage applied to the outputShort-circuit output currentSupply current from VssPower dissipationNumber of erase/write cyclesNumber of read access unrefreshedInput resistanceExternal load resistanceOff-state output resistanceOn-state output resistanceAccess time-the time interval between the application of a specified input pulse during a read cycle and the availability of valid data signal at an outputAddress access time-the time interval between the application of an address input pulse and the availability of valid data signals at an outputColumn address strobe access timeChip enable access timeOutput enable access timeData access time after programRow address strobe access timeChip select access timeCycle timeRead cycle time-the time interval between the start of a read cylce and the start of the next cycleRefresh cycle time-the time interval between successive signals that are intended to restore the level in a dynamic memory cell to its original levelPage-mode cycle timeRead-modify-write cycle time-the time interval between teh start of a cycle in which the memory is read and new data is entered, and the start ofthe next cycleWrite cycle time-the time interval between the start of a write cycle and the start of the next cycle• . MITSUBISHI..... ELECTRIC1-13


MITSUBISHI MICROCOMPUTERSSYMBOLOGYNew symbol Former symbolParameter-definitiontdtd (16)td (CAS-RAS)td(CAS-W) td(CAS'-WR)td (RAS-CAS)td(RAS-W) td(RAS-WR)tdis(R-Q) tdiS(R-DA)tdis(S) tpXZ(CS)tdis(W) tPXZ(WR)tDHL \tDLHten(A-Q) tPZV(A-DQ)ten (R-Q) tPZV(R-DQ)ten(S-Q) t PZX (CS-DQ)tfththeA) th(AD)theA-E) th(AD-CE)theA-PRJ th(AD-PRO)th(CAS-CA)th(CAS-D) th(CAS-DA)th(CAS-Q) th (CAS-OUT)th (CAS-RAS)th(CAS-W) th(CAS-WR)th(D) th(DA)th(D-PR) theDA-PRO)theE) th(CE)theE-D) ~h(CE-DA)theE-G) th(CE-OE)th(R) th(RD)th(RAS-CA)th(RAS-CAS)th(RAS-D) th(RAS-DA)th(RAS-W) th (RAS-WR)th(S) th(CS)thew) th(WR)th(W-CAS) th(WR-CAS)theW-D) th(WR-DA)th(W-RAS) th(WR-RAS)tpHLtpLHtrtrec(w) twrtreC(PD) tR(PD)tsuDelay time-the time between the specified reference points on two pulsesDelay time between clock pulses-e.g., symbology, delay time, clock 1 to clock 2 or clock 2 to clock 1Delay time, column address strobe to row address strobeDelay time, column address strobe to write. Delay time, row address. strobe to column address strobeDelay time, row address strobe to writeOutput disable time after readOutput disable time after chip selectOutput disable time after writeHigh-level to low-level delay time} the time interval between specified reference points on the input and on the output pulses, when theLow-level to high-level delay time output is going to the low (high) level and when the device is driven and loaded by specified networks.Output enable time after addressOutput enable time after readOutput enable time after chip selectFall timeHold time-the interval time during which a signal at a specified input terminal after an active transition occurs at another specified input terminalAddress hold timeChip enable hold time after addressProgram hold time after addressColumn address hold time after column address strobeData-in hold time after column address strobeData-out hold time after column address strobeRow address strobe hold time after column address strobeWrite hold time· after column address strobeData-in hold timeProgram hold time after data-inChip enable hold timeData-in hold time"after chip enableOutput enable hold time after chip enableRead hold timeColumn address hold time after row address strobeColumn address strobe hold time after row address strobeData-in hold time after row address strobeWrite hold time after row address strobeChip select hold timeWrite hold timeColumn address strobe hold time after writeData-in hold time after writeRow address hold time after writeHigh-level to lOw-level propagation time } the time interval betWeen specified reference points on the input and on the output pulses when the. output is going to the low (high) level and when the device is driven and loaded by typical devicesLow-level to high-level propagation time of stated typeRise timeWrite recovery time-the time interval between the termination of a write pulse and the i':1itiation 01a new cyclePower-down recovery timeSetup time-the time interval between the application of a signal which is maintained at a speciifed input terminal and a consecutive activetarnsition at another specified input terminaltsu (A) tsu (AD) Address setup timetsu (A-E) tsu (AD-CE) Chip enable setup time before ilddresstsu (A-W) tsu (AD-WR) Write setup time before addresstsu (CA-RAS)Row address strobe setup time before column address1-14 .• MITSUBisHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSSYMBOLOGYNew symbol Former symboltSU(D) tSU(DA)tSU(D-E) tsu (DA-CE)Data-in setup timeChip enable setup time before data-inParameter-definitionIItsu (D-W)tSU(DA-WR'Write setup time before data-intSU(E)tsu (CE)Chip enable setup timetSU(E-P)tSU(G-E)tSU(CE-P)tsu (OE-CE)Precharge setup time before chip enableChip enable setup time before output enable•tSU(P-E)tsu (P-CE)Chip enable setup time before prechargetSU(PD)Power-down setup timetSU(R)tSU(RD)Read setup timetSU(R-CAS) tsu (RA-CAS)Column address strobe setup time before readtsu (RA-CAS)Column address strobe setup time before row addresstSU(S)tSU(CS)Chip select setup timetSU(S-W)tsu (CS-WR)Write setup time before chip selecttSU(W)tSU(WR)Write setup timetTHLtTLHHigh-level to low-level transition time }Low-1evel- to high-level transition timethe time interval between specified reference points on the edge of the output pulse when the output isgoing to the low (high) level and when a specified input signal is applied through a specified network andthe output is loaded by another specified networktV(A)tv (E)tV(E)PRtv (G)tV(PR)tV(S)twtW(E)tW(EH)tW(EL)tW(PR)tW(R)tW(S)tW(W)tW(¢)TaToprTstgVBBVCCVDDVGGVIVIIiVILVaVOHVOLVSStdV(AD)tdV(CE)tv (CE)PRtv (OE)tv (CS)tW(CE)tW(CEH)tW(EL)tW(RD)tW(CS)tW(WR)Data valid time after addressData valid tin;e after chip enableData valid time after chip enable in program modeData valid time after output enableData valid time after programData valid time after chip selectPulse width (pulse duration) the time interval between specified reference points on the leading and training edges of the waveformsChip enable pulse widthChip enable high pu Ise widthChip enable low pulse widthProgram pu Ise widthRead pulse widthChip select pulse widthWrtie pulse widthClock pulse widthAmbient temperatureOperating temperatureStorage temperatureVBB supply voltageVee supply voltageVDD supply voltageVGG supply voltageInput voltageHigh-level input voltage-the value of the permitted high-state voltage at the inputLow-level input voltage-the value of the permitted low-state voltage at the inp~tOutput voltageHigh-level output voltage-the value of the guaranteed high-state voltage range at the outputLow-level output voltage-the value of the guaranteed low-state voltage range at the outputVss supply voltage., " ',MITSUBISH, I~'EtECTRIC1-15


. MITSUBISHI MICROCO.MPUTERSQUALITY ASSURANCE AND RELIABILITY".TESTING1 .. PLANNINGI n recent years, advances in integrated Circuits have beenrapid, with increasing density and speed accompanied bydecreasing cost. Because of th.ese advances, it is nowpractical and .economically justifiable to use these devicesin systems of greater complexity and in which they werepreviously considered too expensive. <strong>Al</strong>l of.. these advances~dd up to increased demand.We at Mitsubishi foresaw this increased demand andorganized our production facilities to meet it. We alsorealized that simply increasing production to meet thedemand was not enough and that positive steps would haveto be taken to assure the reliability of our products.This realization resulted in development of our QualityAssurance System. The system has resulted in improvedproducts, and Mitsubishi is able to supply its customers'needs with ICs of high reliability and stable quality. Thissystem is the key to future planning for improved design,production and quality assurance.2. QUALITY ASSURANCE SYSTEMThe Quality Assurance System imposes quality controlson Mitsubishi products from the initial conception of anew product to the final delivery of the product to thecustomer. A diagram of the total system is shqwn in Fig. 1.For ease of understanding, the system is divided into threestages.2.1 Quality Assurance in the Design StageThe characteristics of the breadboard devices are carefullychecked. to assure that all specifications are met. Standardintegrated circuits and high·quality discrete components areused. During the design stage, extensive use is made of asophisticated CAD program, which is updated to alwaysinclude the latest state-of-the-art techniques.2.2 Quality A.ssurance in the Limited-Manufacturing StageRigid controls are maintained on the environment, incomingmaterial and manufacturing equipment such as toolsand test equipment. The products and materials used aresubjected to stringent tests and inspections as they aremanufactured. Wafer production is closely monitored.Finally, a tough quality assurance testand inspection ismade before the product is released for delivery to acustomer. This final test includes a complete visual inspectionand electrical characteristics tests. A samplingtechnique is used to conduct tests under severe operatingconditions to assure that the products meet reliabilityspecifications.2.3 Quality Assurance in the Full Production StageFull production of a product is not started until it has beenconfirmed that it can be manufactured to meet quality andreliability specifications. The controls, tests and inspectionprocedures developed in §2.2 are continued. The closestmonitoring assures that they are complied with.3. RELIABll.ITY CONTROL3.1 Rel~ability TestsThe newly established Reliability Center for ElectronicComponents of Japan has established a qualification systemfor electronic components. ReliabilitY test methods andprocedures are developed to mainly meet MI L-STD-883and JIS C 7022 specifications. Details of typical tests usedon Mitsubishi ICs are shown in Table 1.Table 1 Typical reliability test items and conditionsGroupItemHigh temperatureoperating lifeHumidity (steadystate) lifeSoldering heatThermal shockTest conditionMaximum operating ambienl temperature l,o(lOhMaximum storage temperature65'C 95%RH260'C lOs0-IOO'C 15 cycles. 10min/cycleTemperaturecycle ~n~~c~: ~~ ~~~i~~m storage ~emperatllre.SolderingLead integrityVibrationShockConstantacceleration230·C. 5s. use rosin fluxTension 340g 30sBending stress: 225g. ± 30'. 3 times20G. X. Y. Z each direction. 4 times100-2000Hz-4 min/cycle1500G. 0.5ms in X,. y 1 and Z 1 direction. 5 time •.20000G. Y I direction. 1 minl000h500h3.2 Failure AnalysisDevices that have failed during [eliability or acceleration. tests are analyzed to determine the cause of failure, Thisinformation is fed back to the process engineering sectionand manufacturing section so that improvements can bemade to increase reliability. A summary of failure analysisprocedures is shown in Table 2.Table 2 Summary of failure analysis proceduresStep1. ExternaleJlaminationo Observation of characteristics by a synchroscope or a curve'2. Electrical teststracer and checking of important physical characteristics3. InternalexaminationlIDescriptiono Inspection of leads. plating. soldering and weldingo Inspection of materials. sealing. package and markingo Visual inspection of other items of the specificationsOUse of stereo microscopes .. meta.llurgical microscopes. X-rayphotographic eqUipment. fine leakage and gross leakagetesters in the examinationo Checking for open circuits. short circuits and parametricdegradation by electrical parameter measurementby electrical characteristicso Str'ess tests such as environmental or life tests. if requiredo Removal of the cover of the device. the optical inspectionof the internal structure of the deviceo Checking of the silicon chip surfaceo MeaSlIl"Il11>l1t of eleclrlcal characteristics by probes.if applicableo Use of SEM. XMA and Infrared microscanner if requiredo Use of metallurgical analYSIS techniques to supplementanalYSIS of the Internal examination4. Chip analysis' 0 SIi


MITSUBISHI MICROCOMPUTERSQUALITY ASSURANCE AND RELIABILITY TESTINGFig. 1 Quality assurance systemMARKETMARKETING,PRODUCTION PLANNING& PURCHASING DIVS,ENGINEERINGDIVWAFER ANDASSEMBLYDIVQUALITYCONTROLDIVQUALITYASSURANCEDIVMANUFUCTURINGCONTROLDIV.MAINSTANDARDSII"-..fDEVELOPMENnMARKET RESEARCH F !\PLANNING ./PURCHASING· SPECSJIS, MIL SPECSDEVELOPMENT ORDER JH----J)ltJEW PRODUC~~,----+-___ o-- ~lST- \QEVELOPMWV~ ''-'_T_YP_E.... T_E_S_T "I('P-R-E--P-R-OD-U-C-T-IO-N-O-R-D-E-R.... - TlCOUNCIL~R PRE-PRODUCTION\. PRE-PRODUCTION )--- 2ND TYPE TEST'---r-I--------~-----/J! Y COUNCIL FOR MASS-PRODUCTIONr MASS-PRODUCTION)' l'-+-____ -+_____ t-_____ --l._____-I-..{(fEGISmATION\',\. ORDER STANDARDS}1 T o~,-----1I------t----,---t-------+.,.....-----4I' PLANNING OF) Z_-----I---l{L..-_ I[ r \11MANUFACTURE 8~ ( PURCHASE t':R ) P~tJ\I------CT""';-S-T-4P-L!~N-N-IN-G---l-l W { ARR~~CS~)~PRODUCT DRAWINGPRODUCT SPECSSHIPPING SPECSPURCHASING SPECSPRODUCT INSPECTIONSPECSPURCHASING SPECS~ QUALITY ~NTROL I,N SUBCONTRACTING FA2fc;RIES }--+-----+-7\++-< fi ~'jj ~t-+--,----< I 'RECEIVING I.. , B 0 ~.~ ( INCOMING M~TERIALSIINSPECT;NI ~ ~ ~ ~ ~ B'-" t---+-----+----./-+-..... ------+-.-- J ~ 8 ~ ~ ~ ~~':"""'-+--_r__~'!!!M~ WAFER ~ -IIN·LlNE '1-+-----1 ~ ~ 0 ~ ~ 8\2 STO~OOM \ ~;'\. PROCESS JI~EVALUATION ~ ~ ~ , ~ ~ ~ ~~ 'l , ::J U ~ I-' " 1..+-----""1 0


MITSUBISHI MICROCOMPUTERSPRECAUTIONS IN HANDLING MOS IC/LSlsA MOS transistor h~s.a very thin oxide insu.lator .under thegate electrode on the silicon substrate. It is operated byaltering the conductance (gm)·· between source and drain tocontrol mobile charges in the channel formed by theappl iedgate voltage.If a high voltage were applied to a gate terminal, theinsulator-film under the gate electrode could be destroyed,and all Mitsubishi MOS IC/lSls contain internal protection.circuits at each input terminal to prevent this. It is inherentlynecessary to apply reverse bias to the P-N junctions of aMOS IC/lSI.Under certain conditions, however, it may be impossibleto completely avoid destruction of the thin insulator·filmdue to the application of unexpectedly high voltage orthermal destruction due to excessive current from aforward biased P-N junction. The following recommendationsshould be followed in handling MOS devices.1. KEEPING VOLTAGE AND CURRENT TO EACHTERMINAL BELOW MAXIMUM RATINGS1. The recommended ranges of operating conditionsprovide adequate safety margins. Operating within theselimits will assure maximum equipment performance andquality.2. Forward bias should not be applied to any terminal sinceexcessive current may cause thermal destruction.3. Output terminals should not be connected directly tothe power supply. Short-circuiting of a terminal to apower supply having low impedance may cause burn-outof the internal leads or thermal destruction due toexcessive current.2. KEEPING <strong>Al</strong>l TERMINALS AT THE SAMEPOTENTIAL DURING TRANSPORT ANDSTORAGEWhen MOS IC/lSls are not in use, both input and outputterminals can be in a very high impedance state so that theyare easily subjected to electrostatic induction from ACfields of the surrounding space or from charged objectsin their vicinity. For this reason, MOS' IC/lSIs should beprotected from electrostatic charges while being transportedand stored by conductive rubber foam, aluminum foil,shielded boxes or other protective precautions.3. KEEPING ELECTRICAL EQUIPMENT, WORKTABLES AND OPERATING PERSONNEL ATTHE SAME POTENTIAL1. <strong>Al</strong>l electric equipment, work table surfaces and operatingpersQnnelshould be grounded. W.ork tables shouldbe covered withcppper or aluminum plates of good~onductivity, and grounded. One method of groundingpersonnel, after making sure that there is no potentialdiffere~ce with elect~ic~1 equipment,· is by the us~ ~f awristwatch metallic ring, etc. attached around the wristand grounded in series with a 1 M n resistor. Be sure thatthe grounding meets national regulations on personnelsa!ety.2. Current leakage from electric equipment must beprevented not only for personnel safety, but also toavert the destruction of MOS IC/lSls, as describedabove. Items such as testers, curve-tracers and synchro·scopes must be checked for current leakage before beinggrounded.4. PRECAUTIONS FOR MOUNTING OF MOSIC/lSls1. The printed wiring lines to input and output terminalsof MOS IC/lSls should not be close to or parallel tohigh~voltageor high-power signal lines. Turning poweron while the device is short-circuited, either by a solderbridge made during assembly or by a probe duringadjusting and testing, may cause maximum ratings to beexceeded, which may result in the destruction of thedevice.2. When inputloutput, or input andlor output, terminalsof MOS IC/lSIs (now open-circuits) are connected,we must consider the possibility of current leakage andtake precautions similar to §2 above. To reduce suchundesirable trouble, it is recommended that an interfacecircuit be inserted at the input or output terminal, or aresistor with a resistance that does not exceed theoutput driving capability of the MOS IC/lSI be insertedbetween 'the power supply and the ground.3. A filter circuit should be inserted in the AC powersupply line to absorb surges which can frequently bestrong enough to destroy a MOS I C/lSI.4. Terminal connections should be made as described in thecatalog while being careful to meet specifications.5. Ungrounded metal plates should not be placed nearinput or output terminals of any MOS IC/lSls, sincedestruction of the insulation may result if they becomeelectrostatically charged.6. Equipment cases should provide shielding from electro·static charges for more reliable operation. When a plasticcase is used, it is desirable to coat the inside of the casewith conductive paint and to ground it. This is conside'rednecessary even for battery-operated equipment.1-18 • MITSUBISHI"ELECTRIC


MELPS 760 MICROCOMPUTERS


MITSUBISHI MICROCOMPUTERSMS0760·XXXP /MS0761.XXXPSINGLE-CHIP 4-BIT CMOS MICROCOMPUTERDESCRIPTIONThe M50760-XXXP and M50761-XXXP are single-chip 4-bitmicrocomputers fabricated using CMOS technology. Theycome in a 20-pin plastic molded OIL package.Differences between M50760-XXXP and M50761-XXXP.Name ROM capacity RAM capacity IM50760-XXX P 1024 word 48 word IM50761-XXXP 512 word 32 word IThe details given below relate to the M50760-XXX'P.FEATURES• Basic machine instructions ..................................... 37• Instruction execution time ( 1-word instruction at aclock frequency of 400kHz) .......................... 10tLs• Memory capacity ROM .. , ............... 1024 words X 8 bitsRAM ...................... 48 words X 4 bits• Single 5V power supply• Timer (7-bit timer)• Input/output ports (port F) ............ · .......................... · 4• Output ports (port D)" ............ 9 (including 4 I/O ports)• Sensing input (port S)APPLICATIONS• VTRs, audio equipment and TVs• Air conditioners, refrigerators, rice cookers• Remote-controlled receivers/transmitters• Electronic toys• Input/output circuits as sub-microcomputersPIN CONFIGURATION (TOP VIEW)INPUT/OUTPUT 03 ....PORT 0Voo (5V)OUTPUT {04 +-PORT 0 05 +-(OV) CNVssr- -+(OV) VssSENSING INPUTCLOCK INPUTOUTPUT 0 +-PORT 0 714 -+ XOUT CLOCK OUTPUT08 +- 13 +- RESET RESET INPUTINPUT/ {FO .... 912 .... F3} INPUT/OUTPUTOUTPUTPORT F Fl .... 10 11 .... F2 PORT FOutline 20P4IIBLOCK DIAGRAM CLOCK CLOCKRESET INPUT ·INPUT OUTPUTRESET CNVss(OV) X'N X OUT Voo(5V) Vss(OV):---rqr--15 ---,--r------------------;14II IIGE~~~~~ORRAMTIMER (7) ~ I, II ,II ,, II ,SENSING INPUT FO Fl F2 F3'----..r-----'INPUT/OUTPUT PORT FNote 1: The M50761-XXXP has a ROM capacity of 512 words X 8 bits.2 : The M50761-XXXP has a RAM capacity of 32 words X 4 bits.DO 01 02 03 04 05 06 07 08~ '--y-----/INPUT/OUTPUT OUTPUT PORT 0PORTO___ J• MITSUBISHI"ELECTRIC


MITSUBISHI MICROCOMPUTERS. MS0760·XXXP IMS0761·XXXPSINGLE·CHIP 4·BIT CMOS MICROCOM·PUTERPERFORMANCE SPECIFICATIONSPIN DESCRIPTIONPinVooVssFO-F3NameSupply voltageGroundInput/output port FInput or outputFunctionIn Positive power supply pin.In Ground pin.Port F is a 4-bit output-latched input/output port. N-channel transistor open-drain circuits are featured forInlout the outputs. When the port F output latch Is programmed to(1), the output floats (High-Impedance state),thereby enabling use of the port for Input.00-0 304-08Input/output port 0InloutOutPort 0 consists of 9 bits, each of which is Individually latched. N-channel transistor open-drain circuitsare featured for the outputs. Port 0 0 -0 3 pins have a 4-bit input function and when the output latch Isprogrammed to (1 ), the output floats (high-impedance state) thereby enabling use of the port for input.This pin has an active rising edge. When the S pin signal changes from low to high, the flag is set (1).SSenSing input SInNot only in case that the flag Is set 'il t, whennever you want to, you can test It. This enables testing andflag clearing using an instruction. You can test and clear it by using an instruction. The pin can be modifiedto a level active input pin with a mask option.X 1NXOUTClock inputClock outputInOutThese are the clock input and output pins to which an external resistor Is connected for RC oscillation ofthe clock generator or a ceramic resonator is connected. When an external clock Is used, connect thesource to XIN and leave XOUT open.RESETReset inputInThe device is reset when a low-level slngnal is applied for 2 or more machine cycles.CNVssCNVss inputInThis pin is connected to Vss and must have a low-level input applied to It (OV).2-4• MITSUBISHI..... ELECTRIC


~MITSUBISHI MICROCOMPUTERSMS0760·XXXP IMS0761.XXXPSINGLE-CHIP 4-BIT CMOS MICROCOMPUTERBASIC FUNCTION BLOCKSProgram Memory (ROM)This 1024-word X 8-bit mark programmable ROM can beprogrammed with machine instruction codes in accordancewith the customer's specifications.o address(OO) 16Reset startData Memory (RAM)This 48-word X 4-bit (192-bit) RAM is used to store bothprocessing and control data. One RAM word consists of 4bits with bit manipulation possible over the entire storagearea.~01a 1 2 33 2 1 0 3 2 1 a 3 2 1 a 3 2 1 0IIr--I"""1011Fig.3 RAM address mapNote: Y = 0-7 for the M50761-XXXP.1023 address( 3FF) 16Flg.1 ROM address mapProgram Counter (PC)This counter is to specify ROM addresses and the sequenceof read-out of instructions stored in the ROM. It is a10-bit polynomial counter.Fig.2 Program counter configurationNote: 1 a-bit configuration is also featured for the program counter in theM50761-XXXP.Stack Register (SK)This is used to temporarily store the contents of the PCwhile executing subroutines until the program returns to itsmain routine.Data Pointer (DP)These registers are used to designate RAM addresses andbit positions for output port D. Register X (the 2 most significantbits of the DP) designates the RAM file: register Y(the 4 least significant bits) designates the digit position ofthe RAM file.4-Bit' Arithmetic Logic UnitThis unit executes 4-bit arithmetic and logic operations. Itperforms subtraction, addition and logical comparisons.Register A and Carry Flag CYRegister A is a 4-bit accumulator that constitutes the basisfor arithmetic operations. The carry flag CY is used to storecarry or overflow after execution of arithmetic and logicaloperations by the arithmetic unit. It may also be used as a1-bit flag.Register BRegister B is composed of 4 bits and can be used as a 4-bit temporary storage register.TimerThe timer is implemented using a 7-bit counter which, afterrelease of reset, starts counting and divides the machinecycle by 100. It also sets the flag. Counting starts again afterthe flag has been set.The skip instruction (SNZT) can be used to test the flag.Both the timer and the flag can be reset using the systemreset and reset instruction (RSTM).• MITSUBISHI"ELECTRIC2-5


MITSUBISHI MICROCOMPUTERSMS0760-XXXP IMS0761-XXXP'SINGLE-CHIP 4-BIT CMOS MICROCOMPUTERInput/Output Ports(1) Port FThis 4-bit port is controlled for output and input by the OFAand IAF instructions respectively. When using a bit for input,that bit output latch must first be set to (1) to achievethe high-impedance mode.(2) Port 0This port consists of 9 bits which can be used for both outputand input functions by using the SO/RO and lAD instructionsrespectively. The output section provides individualbit latching and the contents of register Y can beusedto designate a single bit of port 0 for output.o 0 ...., 0 3 pins have a 4-bit input function. When using theport for input, the DO ....... 03 output latch must first be set to(1) to achieve the high-impedance mode.The outputs are n-channel open-drain circuits.(3) Port SThis is a rising edge active sensing port. The flag is set (1)when the S pin signal changes from low to high. The skipinstruction (SNZS) may be used for flag testing, and theflag is reset by the execution of this instruction. The flag isalso reset with system resetting.The port can also be used as a level active input pin with amask option, in which case the flag (S) is ineffective.Pin S can be tested using the skip instruction (SNZS) andskipping occurs when the pin is in the high-level mode.ResetWhen the RESET pin is kept low for at least 2 machine cycles,the reset state is enabled. After resetting,when the inputis driven high, the program execution will begin ataddress O.When the reset state is enable, the following operations areperformed.(1) The program counter is set to address O.(2) The two flags (timer flag, sensing input flag) are reset.(3) <strong>Al</strong>l output latchs of port 0 are set to (1) (highimpedance)(4) <strong>Al</strong>l output latchs of port F are set to (1) (hig'himpedance)Fig.4 shows an' example of the power-on resetting circuitClock Generator CircuitA clock generator circuit has been built in to allow controlof the frequency by means of an externally connected resistoror ceramic resonator. In addition, an external clockSignal may be applied at the X 1N pin, leaving the X OUT pinopen. External con'nection of the resister or ceramic resonatershould be specified as a mask option.Circuit examples are shown in Fig.5External registorcircuitExternally connectedceramic resonator circuitFlg.5 Clo,ck generator circuitsExternal signalExternal clockinput circuitDocumentation Required upon OrderingThe following information should be provided when orderinga custom mask.(1) M50760-XXXP mask confirmation sheet(2) ROM data EPROM 3 setsMask OptionsThe following mask options are available, specifiable at thetime of initial ordering.(1) Specify whether a resistor or ceramic resonator is to beused for the clock generator circuit.(2) Specify whether edge sensing or level sensing is to beprovided for port S.Flg.4 Power-on resetting circuitOV~.VDDOV~2 or more machine cycles2-6'. MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSMS0760·XXXP IMS0761.XXXPSINGLE-CHIP 4-BIT CMOS MICROCOMPUTERINSTRUCTION CODE TABLEI~e-t~ . 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111O'e o ,,;1}~11)"/}1!I1D3- &~DO0 1 2 3 4 5 6 7 8 9 A B C D E FRB0000 a NOPLYBLLA ATAM IAF0 0 0 0RB LY LA A0001 1 - BL - OFA1 1 1 1RB LY LA A0010 2 SZC BL - -2 2 2 2RB LY LA A0011 3 SNZS BL - -3 3 3 3SB0100 4 SNZTLYBLLA AXAMI INY0 4 4 4SB LY LA A0101 5 RSTM BL - TBA1 5 5 5SB LY LA A0110 6 RC BL - TYA BM BM BM BM B B B B2 6 6 6SB LY LA A0111 7 SC *BL- RAR3 7 7 7LX SZB LY LA A1000 8 BML - CMA0 0 8 8 8LX SZB LY LA A1001 9 BML - lAD1 1 9 9 9LX SZB LY LA A1010 A BML - TAY2 2 10 10 10LX SZB LY LA A1011 B BML - TAB3 3 11 11 11LY1100 C - RD BMLLA AXAM AMC12 12 12LY LA A1101 D - SD BML - -13 13 13LY LA A1110 E - - BML - SEA14 14 14LY LA A1111 F - RT *BML - SEAM15 15 15Notel: An instruction may cosist of one or two word but only the first word is listed.2 : The BL and BML codes marked with an asterisk are not available with the M50761-XXXP.II• MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPU,TERSMS0760·XXXP IMS0761·XXXPSI,NGLE-CHIP 4-BIT CMOS MICROCOMPUTERMACHINE INSTRUCTIONSParameterI~~~~~~Mnemonic07 06 Os 04g TAB 0 1 1 1.!. enGI ...... TBA '0 1 1 1·~.i~ TAY 0 1 1 1GI C> aIa:~-= TVA 0 1 1 1en~LY y 0 0 1 0GI.t;"C LXx 0 0 0 0aI:::!:«a: INY 0 1 1 1en en"C GI>-~'0 '0 ° Functions03 02 01 00 J6mal notation 0z0zInstruction code 15 u ,1 0 1 1 7 B 1 1 (A)-(B)0 1 0 1 7 5 1 1 (B)-(A)1 0 1 0 7 A 1 1 (A)-(Y)0 1 1 0 7 6 1 1 (Y)-(A)Y Y Y Y 2 Y 1 1 (Y)-y, y=c0-151 0 x x 0 8 1 1 (X)-x, x=0-3+x0 1 0 0 7 4 1 1 (Y)-(Y)+15 TAM 0 1 1 0iii"SE XAM 0 1 1 0~Oen0 ...alGI~"'Ui«!ija:~XAMI 0 1 1 0LA n 0 1 0 0An 0 1 0 16 AMC 0 1 1 1~GIa.0 SC 0 0 0 0:; ° RC 0 0 0 0E SZC 0 0 0 0E.( CMA 0 1 1 1RAR 0 1 1 10 0 0 0 6 0 1 1 (A)-(M(OP»1 1 0 0 6 C 1 1 (A)-(M(OP) )0 1 0 0 6 4 1 1 (A)-(M(OP», (Y)-(Y)+1n n n n 4 n 1 1 (A)-n, n=0-15n n n n 5 n 1 1 (A)-(A)+n, n=0-151 1 0 0 7 C 1 1 (A)-(A)+(M(OP))+(CY)( Cy) -carry0 1 1 1 0 7 1 1 (CY)-10 1 1 0 0 6 1 1 (CY)-O0 0 1 0 0 2 1 1 (CY)=O ?1 0 0 0 7 8 1 1 (A)-(A)0 1 1 1 7 7 1 1 [~IA3A2<strong>Al</strong> Aor-I6SB J 0 0 0 1~ RB J 0 0 0 1GIa.0iiiSZB J 0 0 0 1.~a;a.8()ena.~SEAM 0 1 1 1SEA n 0 1 1 10 1 0 0Ba 1 1 85 84BL p,8 0 0 1 1BM a0 Pa 85 a41 o as a4BML p,a 0 0 1 1o Pa as a4RT 0 0 0 1,6 SNZT 0 0 0 0... Q) ~ ...EQ)1=8'RSTM 0 0 0 00 1 J J 1 4 1 1 (Mj(OP»-1, j=O-3+J0 0 J J 1 0 1 1 (Mj(OP»-O, j=O-3+J1 0 J J 1 8 1 1 (Mj(OP»=O? j=0-3+J1 1 1 1 7 F 1 1 (A)=(M(OP»?\1 1 1 0 7 E 2 2 (A)=n?+n n n n 4 naa az a, aD C a 1 1 (PCL)-as_a 0+ao Pz P, Po 3 0 2 2 (PCH)-P3-PO+Paa 8Z a,ao P a (PCd-as-ao+aaa az 8, aD 8 a 1 1 (SK)-PC, (PCH)-O+a(PCL)-as-ao1 Pz p, Po 3 8 2 2 (SK)-PC,+Paa az a,. aD P a (PCH)-p 3-PO+a(PCL)-as-ao1 1 1 1 1 F 1 1 (PC)-(SK)0 1 0 0 0 4 1 1 (T)=1?After skip (T)-O0 1 0 1 0 5 1 1 Timer reset, (n-O2-8• MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSMS0760-XXXP IMS0761-XXXPSINGLE-CHIP 4-BIT CMOS MICROCOMPUTER>-()Skip conditions C)asu:::----Written successivelyWritten successively(y)=O--Description of operationTransfers contents of resister B to register A.Transfers contents of register A to register B.Transfers contents of register Y to register A.Transfers contents of register A to resister Y.Loads value of "y" into register Y.When L Y is written successively the first is executed and successive ones are skipped.Loads value of "x" into register X.When LX is written successively the first is executed and successive ones are skipped.Increments contents 6f register Y by 1. Skips next instruction when new contents of register Yare "0".Transfers the RAM contents addressed by the active DP to register A.Exchanges the contents of the RAM and register A.II(y)=OExchanges the contents of the RAM and register A.The contents of register Yare incremented by 1 and when the result is "0", the next instruction is skipped.Written successivelycarry = 0- 0/1- 1- 0(Cy)=o-Loads the value n in the instruction into register A.When LA is written successively, the first is executed and successive ones are skipped.Adds value of n to register A. The contents of flag CY remain unchanged.The next instruction is skipped unless any carry is produced.Adds the contents of the RAM and flag CY to register A.The result is stored in register A and the carry in the active flag CY.Sets active flag CY.Resets active flag CY.Skips next Instruction when the contents of the active flag CY are "0".Stores complement of register A in register A.- AORotates contents of register A and flag CY to right.--(Mj(DP»= 0,Sets the jth bit of the RAM addressed by the active DP.Resets the jth bit of the RAM addressed by the active DP.Skips next instruction when the contents of the jth bit of the RAM addressed by active DP are "0".(A)=(M(DP»Skips next instruction whim the contents of register A are equal to the RAM contents addressed by the active DP.(A)=nSkips next instruction when the contents of register A are equal to the value n in the instruction.--Jumps to the address indicated by (a5-aO), while PCH remains unchanged.Jumps to the address indicated by (p 3 -p 0' a 5 -a 0 ).--Calls subroutine starting from the address indicated by (O,a 5 -a 0)' replaced by 0 and PC l has been replaced by (a 5 -a 0)'Calls subroutine starting from the address indicated by (p 3 -p 0' a 5 -a 0)'(T)=l--Returns from subroutine to main routine.Skips the next instruction if timer flag -(T) is "'''.Timer flag is reset when the instruction is skipped.Resets timer and timer flag (T)• MITSUBISHI..... ELECTRIC


MITSUBISHI MICROCOMPUTERSMS0760-XXXP IMS0761-XXXPSINGLE-CHIP 4-BIT CMOS MICROCOMPUTERMACHINE INSTRUCTIONSPara- U> U>Q)meter Instruction code"C~ U~Mnemonic~'5\wei'5'of inst- Di D6 DS D4 D3 D2 D, DO 16mal notation c:i c:iruction z zso 0 0 0 1 1 1 0 1 1 0 1 1 (O(Y»-l8 RO 0 0 0 1 1 1 0 0 1 C 1 1 (D(Y»- 0~ IAF 0 1 1 1 0 0 0 0 7 0 1 1 (A)-(F)~~ OFA 0 1 1 1 0 0 0 1 7 1 1 1 (F)-(A)B SNZS 0 0 0 0 0 0 1 1 0 3 1 1 (S)= 1 ?::.::lCoAfter skipping (S)- 0E lAD 0 1 1 1 1 0 0 1 7 9 1 1 (A)-(D)Functions()U>:iNOP 0 0 0 0 0 0 0 0 0 0 1 1 (PC)-(PC)+ 1Symbol Contents Symbol ContentsA 4-bit register (accumulator) D 9-bit portB 4-bit register F 4-bit portX 2-bit register Shows direction of data flow-Y 4-bit register ( ) Indicates contents of register, memory, etc.DP 6-bit data pointer, combination of register XV xx 2-bit binary variablePC H The high-order 4 bits of the program counter yyyy 4-bit binary variablePCL The low-order 6 bits of the program counter nnnn 4-bit binary constantPC IO-bit program counter, combination of PCH, PCL ii 2-bit binary constantSK . IO-bit stack register -CY I-bit carry flag aaaaaa' Label used to indicate addressT I-bit timer overflow flag pppp Label used to indicate addressSI-bit portNote: When a skip has occurred, the next instruction only is ignored and,the program counter is not incremented by 2. Therefore, the number of cyclesdoes not change in accordance with the existence or non-existence of skip .2-10 • 'MITSUBISH..... ELECTRIC


MITSUBISHI MICROCOMPUTERSMS0760-XXXP IMS0761-XXXPSINGLE-CHIP 4-BIT CMOS MICROCOMPUTER>-()Skip conditions CI Description of operation.,ii:- Sets the bit of port 0 that is designated by register Y.- Resets the bit of port 0 that is designated by register Y.- Transfers port F input to register A.- Outputs contents of register A to port F.(8)=1 The next instruction is skipped when port S fiag (S) is "1". Flag (8) is reset when the Instruction is skipped.II- Transfers port DO -0 3 input to register A.- No operation.BASIC TIMING DIAGRAMMi Mi+ 1T( T1 T2 T3 T(Clock inputX 1NPort D outputPort D inputPort F outputFa-F3Port F inputFa-F3Port S inputSNote 1The crosshatch area indicates invalid input.. • MITSUBISHI;"'ELECTRIC2-11


MITSUBISHI MICROCOMPUTERSMS0760.XXXP1MS0761.XXXPSINGLE-CHIP 4-BIT CMOS MICROCOMPUTERABSOLUTE MAXIMUM RATINGS)Symbol Parameter Conditions LimitsVoo Supply voltage -0.3-7VI Input voltage, XIN. RESET -0.3- Voo + O. 3VI Input voltage. ports F, 00-03. S -0.3-11Vo Output voltage, XOUT -0.3- Voo + 0.3Vo Output voltage, ports F, 0 Output transistors cut-off -0.3-11Pd Power dissipation Ta = 2S'C 400Topr Operating temperature -10-70Tstg Siorage temperature -40-125UnitVVVVVmW"C·CRECOMMENDED OPERATING CONDITIONS (Ta= -IO-lOt. unless otherwise noted)Symbol Parameter ConditionsMinVoo Supply voltage 4VssSupply voltageV IH High-level input voltage. port.F, 00-03. S O. lXVooV IH High~level Input voltage, RESET, XIN O. 7XVooV IL Low-level input voltage 0IOL(Oeak Low-level peak output current. port o. -0 8IOL(peak Low-level peak oiJtput current, ports F, 0 0 - 3IOL(avg) Low-level average output current. ports O. -0 8 (Note 1)IOL(aVg) Low-level average outpilt current, ports F. 00-03 (Note 1)f(~) Internal clock oscillation frequency 200,LimitsNom0Max610VooO. 3XVoo2410125400UnitVVVVVmAmArnAmAkHzNotel: The low-level average output currents IOL (avg)are average values in lOOms period.ELECTRICAL CHARACTERISTICS (Ta = -IO-lOt. Voo = 5 V±IO%. f = 200-400kHz)SymbolVOLVOLIIHIIHIIH(rp)IlLIIL( rp)Ci100ParameterLow-level output voltage, port F, DO -03Low-level output voltage. ports 04-08High-level Input current. ports F, 00-08, SHigh-level input current, XOUT. RESETHigh-level input current. XINLow-level input current. F. DO -0 3, S, XOUT, RESETLow-level input current, XINClock input capacitanceSupply currentIOL = 1.SmAIOL = 12mAVI= lOVVI = VooVI=VOOVI=OVVI=OVf=l MHzf=400kHzTest conditionsMinLimitsTyp Max0.42101010-10-107 10400 900UnitVVf.,lAf.,lAf.,lAf.,lAf.,lApFf.,lA2-12• MITSUBISHI..... ELECTRIC


MELPS 740 MICROCOMPUTERSEJ


MITSUBISHI MICROCOMPUTERSMS0740-XXXSPSINGLE-CHIP a-BIT CMOS MICROCOMPUTERDESCRIPTIONThe M50740-XXXSP is a single-chip 8-bit microcomputerfabricated using CMOS technology and housed in a 52-pinshrink plastic molded OIL package. It is designed to suit forcontrolling home electrical appliances and consumerequipment with a simple instruction where the ROM andRAM use the same memory area.FEATURES'• Basic machine instructions······································ 70• Memory capacity ROM ·······························3072 bytesRAM··································· 96 bytes• Instruction execution time (with shortest instruction,at 4MHz) ··················································2,us (min.)• Single power supply .. ··································5V ±10%• Low power dissipation·· 15mW during operation (4MHz)• Subroutine nesting ............................. 48 levels (max.)• Interrupts··························· 5 sources, 32 levels (max.)• 8~bit timers·····························································3• Programmable input/output (ports PO, Pl, P2, P3) ······32APPLICATIONVTRs, tuners and audio equipmentPIN CONFIGURATION (TOP VIEW)INPUT/OUTPUTPORT P2INPUT/OUTPUTPORT POTIMER INPUT/O~NTrE~TR~~ POo - 17INPUT CNTR - 18INTERRU:;JPUT INT -+ 19NC 20I (OV)__CNVss -+ 21RESET INPUT RESET -+ 22CLOCK INPUTVee (5V)NC______..12-7 - Ra\INPUT/OUTPUTPORT p3INPUT/OUTPUTPORT pi35 - P1 7 RESET34 -+ RESET OUT OUTPUT '33 -+ CE CHIP ENABLE32 -+ R/W ~~f~ OUTPUT31 --+ if> TIMING OUTPUT29 - Rl !INPUT/OUTPUT28 _ R2 PORT ROutline 52P4BNC : NO CONNECTIONII(5V) (OV) (OV)Vec Vss CNVss--r-r---r-- -- -----;~--r----------------.------------------------r---------------a------,r--------.---IIIII ,27282930 434445464484950 12345678 3536 383940414 1011113115161CE R/W Ra Rl P37 P35 P33 P31 P27 P25 P23 P21 P17 P15 P13 P11 P07 POs P03 po,R2 Ro P36 P34 P32 P30 P26 P24 P22 P20 ~~L~I~o ~LfQLPQz....fQoCHIP READI I NPUT;---!NPUTI INPUTI INPUTI INPUT/ENABLE WRITE OUTPUT OUTPUT OUTPUT OUTPUT OUTPUTOUTPUT PORT R PORT P3 PORT P2 PORT Pl PORT POCNTRriMER X TX(BTIMERINPUT/OUTPUT ANDINTERRUPT INPUTI,CONTROL jSIGNAL---------• MITSUBISHI.... ELECTRIC3-3


MITSUBISHI MICROCOMPUTERSMS0740-XXXS PSINGLE-CHIP a-BIT CMOS MICROCOMPUTERPERFORMANCE SPECIFICATIONSParameterPerformanceNumber of basic Instructions 70Execution time of basic Instruction2I-Ls (with shortest instructions, 4MHz clock frequency)Clock frequency4MHzROM3072 bytesMemory capacityRAM96 bytesINT Input 1 bit X 1Input/output portsPO, P1, P2, P3 Input/output 8 bits X 4R Input/output 4 bits XlCNTR Input/output 1 bitX1Timers B-bit pre scalers x 2 + 8-bit timers x 3Subroutine nestingMax. 48 levelInterrupts External interrupts (2), internal timer interrupts (3)Clock gen~ratorBuilt-in (externally connected RC circuit, ceramic or quartz resonator)Supply voltage During operation 5V± 10%Power dissipationInput/output characteristicsMemory expansionHigh-speed operation15 mW (at 4MHz clock frequency)Low-speed operation100 I-LW (at 20kHz clock frequency)Input/output withstanding voltage12V(Ports PO, pt, P2,INT, CNTR)Output current10mA (Ports PO, P1, P2, P3)PossibleAmbient operating temperature-10-70·CDevice structureCMOS silicon gate processPackage52-pin shrink plastic molded OILPIN DESCRIPTIONPin Name Input or outputVeeVssSupply voltageInCNVss CNVss Input InRESET Reset input InX 1N Clock input InX OUTS Clock output OutX OUTF Clock output Out¢> Timing output OutCNTRTimer input/outputand Interrupt inputIn/outINT Interrupt input InPO O -P07 Input/output port PO In/outP1 0 -P1 7 Input/output port P1 In/outP2 0 -P2 7 Input/output port P2 In/outP3t1-P37 Input/output port P3 In/outR o -R 3 Input/output port R In/outR/W Read/write output OutCE Chip enable output OutRESETouT Reset outputOut5V ±10% supplied to Vee, OV supplied to VssTo be connected to Vss.FunctionWhen this input is kept low for at least 2I-Ls, the reset state is enabled.The clock generator circuit Is built-In. For setting the oscillation frequency, either connect the externalRC circuit to X1N and XOUTS or XOUTF or connect a ceramic or quartz resonator across X1N and XOUTS.When using an external clock source connect the clock generator source to X1N, leaving XOUTF andXOUTS open. For details, refer to the section on the clock generator circuit.Internal clock generator output. An RC circuit or ceramic or quartz resonator is connected between thisoutput and X1N to control the oscillation frequency. For details, refer to the section on the clock generatorcircuit.Internal clock generator output. An RC circuit is connected between this output and XIN to control theoscillation frequency. For details, refer to the section on the clock generator circuit.Timing outputTimer X input/output pin and interrupt input pin.Interrupt input pin.This 8-bit input/output port has a direction register and for each bit the port is programmed to serve forinput or output. The input mode is established during resetting. N-channel open-drain circuits are usedfor the outputs. For details, refer to the section on the inpi,lt/output pins.This is an 8-blt input/output port with virtually the same functions as those of port PO.This is an 8-bit input/output port 'with virtually the same functions as those of port PO.This is an 8"bit input/output port with virtually the same functions as those of port PO, but p-channelopen-drain circuits are used for the outputs.This 4-bit input/output port is used for connection with the I/O expander.Read/write signal output for I/O expander.Chip enable Signal output for I/O expander.Reset signal output for I/O expander.3-4•. MITSUBISHI"ELECTRIC


MITSUBISHI MICROCOMPUTERSMS0740-XXXSPSINGLE-CHIP 8-BIT CMOS MICROCOMPUTERBASIC FUNCTION BLOCKSMemoryFig. 1 shows the memory map. The 3072-byte ROM extendsfrom 1400 16 to 1 FFF 16 . The area from 1 F00 16 to 1 FFF 16 includesspecial addresses, and when the special pageaddressing mode is used with the JSR instruction, subroutineson these pages can be called with two bytes. Thearea from 1 FF4 16 to 1 FFF 16 includes the reset and interruptvector addresses. For details, refer to the section on interrupts.Zero pageROM (3072 bytes)RAM 1 0000 '(96 bytes)6005F, 60000, 6OODF, 6110, (OOE 0, 6timers, etc.SpecialsJt~~t:~~callOOFF, 61400, 66lFF4,6Not used1/0 expanderNot usedAddress L/address HAddress Uaddress HAddress Uaddress HDecimaloAddress Uaddress HTimer XAddress L/address HCNTRAddress L/address H1FFFi 68191 reset vectorThe addresses from 0000 16 to 00FF 16 are own as the zeropage and access to this page can be achieved with twobytes by using the zero page addressing mode, which reducesthe number of programming steps. The memoriesused frequently, such as the RAM, input/output ports andtimers, are allocated to the zero page.From 0000 16 to 005F 16 is the RAM space and the size is 96bytes. Apart from storing data, the RAM is also used as astack for subroutine calls or interrupts.95 /////255\\\\/\\/\\\//\\\\\\\\\\\INT\Timer 2 \\Timer 1 \///OOEO'6 PortO/OOE 1i 6 Data direction register of pat 0OOE 2 '6 Port 1OOE 3 '6 Data direction register of pat 1OOE 4 '6 Port 2OOE 5, 6 Data direction registe. of pat 2OOE 6, 6OOE 7, 6OOE 8, 6 Port3OOE 9, 6 Data direction register of pat 3OOEA, 6OOES, 6OOEC, 6OOED, 6OOEE, 6OOEF, 6OOF 0, 6OOF I, 6OOF 2, 6OOF 3, 6OOF 4, 6OOF 5, 6OOF 6, 6OOF 7, 6OOF 8, 600F9, 6 Prescaler for Timer 1 , 2OOFA, 6 Timer 1OOFS, 6 Timer2OOFC, 6 Prescaler for Timer X\\ OOFD, 6 Timer X\ OOFE, 6 Interrupt control register\\ OOF F'6 Timer control register\Details of 110, timer addressIII Flg.l Memory layout• MITSUBISHI;"EI-ECTRIC3-5


MITSUBISHI MICROCOMPUTERSMS0740·XXX5 PSINGLE.CHIP a·BIT CMOS MICROCOMPUTERCPUSix registers,as shown in Fig. 2, are contained inside theCPU. Each Of these register is now described in turn.Accumulator AThe accumulator is the 8-bit register and is heart of themicrocomputer. Arithmetic and logic operations, transfersand processing of input/output and other data are performedcentering on this register.Index Register X·This is an 8-bit register. In the index addressing modewhere this register serves as the index register, the Contentsof this register and the contents of the program c:ounteris added and the result is actual address. When flag Tin the program status register is "1 ,It the contents of indexregister X become the other operand address.Index . Register VThis is also an 8-bit register. In the index addressing modewhere this register serves as the index register, the contentsof this register and the contents of the program counteris added and the result is actual address.7 0IA I Accumulator7 0IX Index register XI7 0yIndex register YII7 0SI I Stack pointer15 7 0PCHPCL I Program counterIIProcessor status registerCarry flagZero flagInterrupt disable flagDecimal mode flagBreak flagX-modified arithmeticmode flagOverflow flagNegative flagFlg.2Register configuration3-6 • . MITSUBISHI"'ELECTRIC


MITSUBISHI MICROCOMPUTERSMS0740-XXXS PSINGLE-CHIP 8-BIT CMOS MICROCOMPUTERStack Pointer SThe stack pointer is an 8-bit register used for calling subroutinesand for interrupts. When an interrupt is acknowledged,the high-order contents of the program counter aresaved in the address where the low-order address are thecontents of the stack pointer and the high-order addressare "0," the contents of the stack pointer are then decrementedby 1, the low-order contents of the programcounter are saved in the address where the low-orderaadress are the contents of the stack pointer .and the highorderaddress are "0," the contents of the stack pointer arethen further decremented by 1, and the contents of theprogram status register are saved in the address where thelow-order address are the contents of the stack pointer andthe high-order address are "0."This operation is performed automatically when an interruptis acknowledged. The RTI instruction is used to return fromthe interrupt routine, and when it is executed, the stackp6inter is incremented by 1 and returned in the reversesequence to that described abo~e. Since the contents ofaccumulator are not saved automatically, the PHA instructionmust be used for this purpose. When the PHA instructionis executed, the contents of the accumulator are savedin the address where the low-order address are the contentsof the stack pointer and the high-order address are"0," and the contents of the stack pointer are decrementedby 1. The accumulator is returned by the PLA instruction.When this instruction is executed, the contents of the stackpointer are incremented by 1 and the contents of theaddress where the low-order address are the stack pointercontents and the high-order address are "0" enter theaccumulator.Similarly, the contents of the program status register aresaved and returned by the PHP and PLP instructions respectively.With a subroutine call, program counter savingonly is performed and this necessitates saving on the programfor registers which must not be destroyed. The RTSinstruction is employed to return from the subroutine.Program Counter PCThis is a 16-bit counter consisting of PC H and PCL, both is 8bit register. PC H is 8 bit register, but only 5 bits are actuallyused. The program counter specifies the address of theprogram memory whicA is to be executed next.Processor. Status Register PSThis 8-bit register consists of the flags that hold the statusimmediately after arithmetic and logic operations. The C, Z,V and· N flags can be tested and. branched using thebranch instructions. Each bit of the register is described indetail below.1. Carry Flag CThe carry flag C is used to store carry or overflow after executionof arithmetic and logic operations by the arithmeticlogic unit. It also undergoes change with the shift and rotateinstructions. It can be set or reset directly using the SECand CLC instructions.2. Zero Flag ZThis flag is set when the results of data transfer or arithmeticand logic operations are "0" and reset when they arenot "0."3. Interrupt Disable Flag IThis flag disables all interrupts when its contents are "1."When an interrupt is acknowledged, its contents are automaticallymade "1." The flag can be set or reset by theprogram using the SEI and CLI instructions.4. Decimal Mode Flag DThis flag determines whether additions and subtractions areto be undertaken by the binary or decimal mode. Theordinary binary mode is used when its contents are "0",while 1 word is processed as a 2-digit decimal numberwhen its contents are "1." Decimal corrections are performedautomatically. The SED and CLD instructions areused for setting and resetting.5. Break Flag BOperation is the same for interrupts when the BRK instructionis executed. This Instruction is used for debuggingprograms. The BRK instruction interrupt vector and the interruptvector of the lowest order of priority are located inthe same address. In order to discriminate whether or notan interrupt has occurred with the BRK instruction, the contentsof flag B are set to "1" when interrupted by the BRKinstruction; at all other times, the contents are set to "0"and saved. It is possible to ascertain whether an interrupthas occurred with BRK by investigating the bit saved in theinterrupt routine.6. X-modified Arithmetic Mode FlagArithmetic and logic operations are performed between theaccumulator and memory when the flag T contents is "0."When this bit is "1," the accumulator is bypassed and operationsare performed directly between the memories. Theresults of such operations between memory 1 and memory 2enter memory 1. The memory 1 address is specified by thecontents of index register X; the memory 2 address is specifiedby the ordinary addressing mode. The SET and CL Tinstructions are used for setting and resetting flag T.II• MITSUBISHI.... ELECTRIC3-7


MITSUBISHI MICROCOMPUTERSMS0740·XXXSPSINGLE·CHIP 8·BIT CMOS MICROCOMPUTER7 .. Overflow Flag VThis flag is significant when in the addition and subtructiona single word is treated as a signed binary number. It is setwhen the results of an addition or subtraction exceed + 127or -128. Apart from this, the 6th bit of the memory subjectto the execution of the BIT instruction enters the overflowflag when this instruction is executed. The ClV instructionis used to clear the overflow flag. A setting instruction is notprovided.8. Negative Flag NThis flag is set when the results of an arithmetic or logicoperation or of data transfer are negative (7th bit is "1"). Inaddition, the 7th bit. of the memory subject to the BIT instructionenters the negative flag when this instruction isexecuted. Instructions to set and reset this flag are not provided.Table 1Interrupt sourceRESETCNTRTimer XTimer 1Timer 2INT (BRK)Interrupt vector addresses and priorityPriority123456Vector address1FFF, 1FFE1FFD, 1FFC1FFB, 1FFA1FF9, 1FF81FF7, 1FF61FF5, 1FF4INTERRUPTSInterrupts include the interrupt from pin CNTR, the timer Xinterrupts, timer 1 interrupt, timer 2 interrupt, the interruptfrom pin INT and the interrupt based on the BRK instruction.The interrupts are vector interrupts and Table 1 showsthe vector table and priority. Resetting take the same actionas interrupt and so it is descried here.When an interrupt is acknowledged, the registers aresaved, as described in the above section on stack pointerS, the interrupt disable flag I is set and a jump is made tothe address indicated by the contents of the vector table.The i,nterrupt request bit is automatically cleared. Resettingis not disabled by any condition. Interrupts (exclusive ofresetting) are not acknowledged when the interrupt disableflag has been set. The interrupts from pin CNTR, timer X,timer 1, timer 2 and INT can be controlled individually bythe interrupt control and timer control registers. This isshown in Fig. 3. When the interrupt enable bit is "1," whenthe interrupt request bit is "1" and when the interrupt disableflag I is "0," the interrupt is acknowledged. When thelevel of pins CNTR and INT change from high to low orwhen the contents of timer X, timer 1 or timer 2 reach to "0,"the corresponding interrupt request bits are set.These bits can be reset by programming but cannot be set.The interrupt enable bit can be set and reset by programming.Whether interrupt is caused by the BRK instruction,can be verified by checking break flag B which has beensaved, as mentioned in the section on the break flag B.Interrupt control register (FE address)Bit 7: CNTR interrupt request bitBit 6: CNTR interrupt enable bitBit 5: Timer 1 interrupt request bitBit 4: Timer 1 interrupt enable bitBit 3: Timer 2 interrupt request bitBit 2: Timer 2 interrupt enable bitBit 1: INT interrupt request bitBit 0: INT interrupt enable bitTimer control register (FF address)InterruptrequestBit 7: Timer X interrupt request bitBit 6: Timer X interrupt enable bitBit 5: Timer X count stop bitBit 4: Not usedBit 3JBit 2: Timer X mode bitsBit 1 JBit 0: Processor mode bitsFig.3Interrupt control3-8 • MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSMS0740-XXXS PSINGLE·CHIP a·BIT CMOS MICROCOMPUTERTimersThere are 3 timers: timer X, timer 1 and timer 2. Timer X hasfour modes which are selected by the value of the timer Xmode bits (bit 2 and bit 3) in the timer control register.When the timer count stop bit (bit 5) is set to "1," all fourtimer X modes stop. Fig. 4 is a block diagram of timers X, 1and 2. Timer 1 and timer 2 have a common prescaler composedof 8 bits. The frequency division ratio is determinedby the prescaler contents. This ratio is 1/(n+2) when theprescaler latch contents are made n decimally. <strong>Al</strong>l the timershave 8-bit timer latches. The countdown system is featuredfor the timers, and the timer latch contents are reloadedinto the timer at the following cycle when the countercontents reach to "0."When the timer contents reach to "0," the interrupt requestbit (on the interrupt control register or on the timer controlregister located in the FE 16 or FF 16 address respectively)corresponding to the timer is set to "1." Any number except"0" should be entered in the prescaler latch and timerlatch.Refer to the section on interrupts for details. The fourmodes of timer X are now described.(1) Timer mode (00)In this mode the frequency produced by dividing theoscillation frequency by 16, is counted. When the timercontents reach to "0," the interrupt request bit is set to"1 ," the timer latch contents are re-Ioaded and thecount is continued.(2) Pulse output mode (01 )Every time the timer contents reach to "0," the signalon the pin CNTR changes the polarity.(3) Event counter mode (10)Operation is the same as in the timer mode except forcounting the signal from pin CNTR.aOscillatorFrequencydividerForciblyconnectedhere with theData busCNTR pinTo timer X interruptrequest bitPulse output modeTimer X count stop bit(5th bit of FF'6 address)To timer1 interruptrequestbitFig.4 Block diagram of timer X, timer 1, timer 2• MITSUBISHI.... ELECTRIC3-9


MIT~UBISHI MICROCOMPUTERSMS0740-XXXSPSINGLE-CHIP 8-BIT CMOS MICROCOMPUTER(4) Pulse width measurment mode (11 )The frequency, produced by dividing the oscillation frequencyby16, is counted only while the pin CNTR levelis low. When the counter contents reach to "0," the interruptrequest bit is set to "1," the timer latch contentsare re-Ioaded and the count is continued.Fig. 5 shows the relationship between the timer controlregister contents and the timer modes.<strong>Al</strong>so shown are the processor mode and other bits.When reset or the STP instruction is executed, the timerX prescaler is set in FF 16 and the timer X latch is setin 01 16 . When the STP instruction is executed, the frequencyproduced by dividing the oscillation frequencyby 16 serves as the timer X prescaler input, regardlessof the timer X mode bit. This mode is released eitherwhen the timer X interrupt request bit is set to "1" orwhen resetting is accomplished and resume the modedetermined by the timer X mode bit. For details on theoperation of the STP instruction, reference should bemade to the section on the oscillator circuit.r I I /XII J I ILL Timer control register (FF 16 address)Processor mode bits00: Single chip mocle01: Memory expansion mode10: Microprocessor modE!1 1: Evaluation chip mode(forcibly established whenCNVss pin is set high)Timer X mode bits00: Timer mode01: Pulse output mode1 0: Event counter mode1 1: Pulse width measurment modeTimer X count stop bit0: Count start1: Count stopTimer X interrupt enable bit0: Interrupt disable1: Interrupt enableTimer X interrupt request bit0"': No inter~upt request1: Interrupt request presentflg.SConfiguration of timer control registerf (91)RESETRESEToUT __ ~ __________________ ~SYNCAddressData8 clock cycle-15 clock cycle:depends on internal state ofmicrocomputer when resettingis undertaken.Note 1Note 2Reset addressbrought from vector tableThe relationship between ¢ and f( 91) is normally f( 91) = 4, 'II,but when the address is the 110 expander address (00 16 -DF 16 ), it is f(


MITSUBISHI MICROCOMPUTERSMS0740-XXXS PSINGLE.CHIP a·BIT CMOS MICROCOMPUTERReset CircuitWhen a supply voltage of 5V ±10% is being supplied to the.M50740-XXXSP and the RESET pin is returned to the highlevel after being kept at the low level for 2J1s or more, thereset is released in accordance with the sequence shownin Fig. 6, and the program starts from the address which isderived from the contents of the address 1 FFF 16 and 1 FFE 16,high-order address is the contents of address 1 FFF 16 andlow-order address is the contents of address 1 FFE 16 . Whenresetting is accomplished, the internal state of the microcomputeris as shown in Fig. 7.Fig. 8 shows an example of the reset circuit.The reset input voltage should be set to less than 0.6V atthat point when the supply voltage is passing through 4.5V.Address(1) Data direction ( E 1 16 )···1 o 0 16Iregister of port 0(2) Data direction ( E ~ 16 ) ... [ o 0 16Iregister of port 1) ···1 [(3) Data direction ( E 5 16 o 0 16register of port 2(4) Data direction ( E 9 16 ) .. ·1 o 0 16Iregister of port 3(5) Prescaler X ( F C 16) ... F F 16IPower onM50740~XXXSPOVM50740-XXXSPRESETVee'::2'::T 2 -----e52~ Supply voltager- ---.:..--~ detection circuitIIIIIIII~----~~ II, IIIIIIIIIL ________ JFig.8 Example of reset circuitII(6) Timer X ( F D 16) ... o 1 161(7) Interrupt control register ( FE 16 ) ...o 0 16 1(8) Timer control register ( F F 16 ) ... o 0 16I(9) Interrupt disable flag ( PS ) ...[on the processor statusregister1 1[ [1[ [I00) Program counter ( PC H(11) The oscillator output isconnected to pin X OUTF aswith the state establishedafter the FST instructionhas been executed.Fig.7) ... 1 contents of the ,Iaddress 1 FFF 16( P C L) .1 contents of th.e ; 1... address 1 FFE 16Internal state of microcomputer after resettingInput/Output Pins(1) Port POThis port is an 8-bit input/output port with n-channelopen-drain outputs. As shown in the memory map ofFig. 1, port PO is treated as the memory of address E0 16on the zero page. Port PO has a data direction register(address El l6 on zero page) and programming can beundertaken for individual bit to use the port for input oroutput. The pins where the data direction register isprogrammed to "1" are for output and those where theregister is programmed to "0" are for input. The datawritten into the pin programmed as an output pin arewritten into the port latch and supplied direct to theoutput pin. When reading. the. data from a pin programmedas an output pin! it is not the output pin contentswhich are read but the port latch contents. Consequently,since the LED or other similar part is drivendirectly, the value output previously can be read correctlyeven if the low-level output voltage rises. Thepin programmed as an input pin remains floating, soexternal signal can be read. When data are written,they are written into the port latch only and the pin remainsfloating.• MITSUBISHI.... ELECTRIC3-11


MITSUBISHI MICROCOMPUTERSMS0740-XXXSPSINGLE-CHIP a-BIT CMOS MICROCOMPUTER(2) Port P 1This has the same functions as port pO.(3) Port P 2This has the same functions as port pO.(4) Port P3Apart from the fact that this port has p-channel opendrainoutputs, its functions are the same as those forport PO. Fig.9 is a block diagram of port PO-P3.<strong>Al</strong>so indicated are the output structure of port R, CNTR,¢, R/W, CE and RESET OUT.(5) Port R'This port is for exchanging data with the I/O expander.When ¢ is high, the port address of the I/O expander issent; when it is low, data are sent to or received fromthe expander. The above data and addresses areeffective only when pin CE is low. Fig. lOis a timing diagram.(6) CEThis pin is set low when the address becomes the I/Oexpander address (0016-0F16)' It is used to inform theI/O expander that the port R address or data is effective.(7) R/WThis is set low while writing is being executed, and it isused to inform the I/O expander that either writing orreading is being undertaken.(8) ¢Normally output to this pin is a signal with a frequencyproduced by dividing the clock frequency by 4. However,when pin CE is low, an output with a frequencywhich is one-eighth of the clock frequency is output.The pin is used to provide synchronization with the I/Oexpander.(9) RESET OUTWhen the RESET pin is set low, this pin also goes low.When the RESET pin is set high, the pin also goes highafter between 8 and 15 clock cycles (this depends onthe internal state of the microcomputer). The RESET­OUT pin itself is used to reset the I/O expander.00) INTWhen an input which changes the level from high tolow is applied to this interrupt input pin, the INT interruptrequest bit (bit 1 of address FE16) is set to "1." .(11) CNTRThis pin serves both as the timer X input/output pinand as the interrupt input pin. When an input whichchanges its level from high to low is applied, the CNTRinterrupt request bit (bjt 7 of address FE16) is set to "1."The pin serves as the external pulse input pin in theevent counter mode. In the pulse output mode a pulsewhich reverses its polarity is output every time the timerX contents are reach to "0." In the pulse widthmeasument mode, the pulse to be measured is suppliedto this pin.Data busData busFlg,9CE \N-channel open-drain output--


MITSUBISHI MICROCOMPUTERSMS0740-XXXS PSINGLE-CHIP a-BIT CMOS MICROCOMPUTERClock Generator CircuitThe clock generator circuit is built-in, as shown in Fig. 11.When the STP instruction is executed, oscillation is stoppedwith the internal clock if> in the high-level. Furthermore, FF 16is set in prescaler X and 01 16 in timer X, and the output,one-sixteenth of the oscillator output, is forcibly connectedto the prescaler X input. This connection is released when,as mentioned in the timer section, timer X overflows orwhen resetting is accomplished. Oscillation re-starts whenan interrupt is acknowledged but the internal clock if> ,remains high until timer X: overflows. Only when timer Xoverflows is the internal clock if> supplied. This is becausetime is required for the oscillation to rise when a ceramicresonator or similar part is employed.When the FST instruction is executed, ,SWase closes andwhen the SLW instruction is executed, it opens. These instructionsare used when RC oscillation is emploied andthe oscillation frequency is changed. SWase is closed duringresetting.IIInterrupt requestInterrupt disable flag ISoSTP instruction -----I ROverflowSW{>CE=O~-'--~Intemal clock ¢>RESETRt----STP instructionFlg.l1Block diagram of clock generator circuit• MITSUBISHI"ELECTRIC3-13


. MITSUBISHI MICROCOMPUTERSMS0740-XXXSPSINGLE.CHIP a·BIT CMOS MICROCOMPUTERWhen the address becomes the I/O expander address(00 16 - OF 16 ) I SW


MITSUBISHI MICROCOMPUTERSM50740~XXXSPSINGLE·CHIP I·BIT CMOS MICROCOMPUTERAddressing ModesThe M50740-XXXSP has 17 addressing modes and an extremelypowerful memory access capability.When extracting data required for arithmetic and logic operationsfrom the memory or when storing the results ofsuch operations in a memory using the appropriate instructionsfor this purpose, the memory address must be specified.Even when jumping to an address during a program,that particular address must be specified. The specificationof the memory address is called addressing., The data requiredfor addressing and the registers involved are nowdescribed. The M50740-XXXSP's instructions can be classifiedinto three kinds, as shown in Fig. 15, by the byte numberin the program memory required for configuring the instruction:1-byte, 2-byte and 3-byte instructions. In eachcase, the first byte is known as the "operation code" whichforms the basis of the instruction. The second or third byteis called the "operand" which affects the addressing. Thecontents of index registers X and Y also effect the addressing.However many the addressing modes, there is no differencein the sense that a particular memory is specified.What differs is whether the operand or the index registercontents or a combination of both should be used to specifythe memory or jump destination. Based on these 3 methods,the range of variation is increased and the M50740-XXXSP'soperation is enhanced by combinations of the bit operationinstructions, jump instruction and arithmetic instructions.The accumulator or register is specified with a 1-byte instructionand so there is no operand byte, which is the partspecifying the memory.Actual addressing modes are now described by type.IIl-byte instruction 2-byte instruction 3-byte instruction-.----.... -......---....OpcodeI Operand I IOpcodeI Operand I I... I Operand II IIIIIIndex registerxy"""-1,...00Fig.15Instruction byte configuration• MITSUBISHI.... ELECTRIC3-15


MITSUBISHI MICROCOMPUTERSMS0740·XXX5 PSINGLE-CHIP a-BIT CMOS MICROCOMPUTERNameFunction: Immediate addressing mode: Operand follow immediate afteropcode.Instructions: ADC, AND, CMP, CPX, CPY,EOR, LOA, LOX, LOY, ORA,sacExample : Mnemonic Machine code-ADC :1* $AS 69 16 AS 16f* This symbol designates the immediateaddressing mode.A-A+C+~MemoryOpcode (69,8)Operand (AS,8).--1,...000Name : Accumulator addressing modeFunction : Operation is performed on accumulator.Instructions: ASL, DEC, INC, LSR, ROL,RORExample : MnemonicROL AMachine code2A 16L[;.Carry flagBit 7Accumulator3-16•. MITSUBISHI"ELECTRIC


Name : Zero page addressing modeFunction : Operation is performed on thezero page memory (0016-FF16)Instructions : ADC, AND, ASL, BIT, CMP,COM, CPX, CPY, DEC, EOR,INC, LDA, LDM, LDX, LDY,LSR, ORA, ROL, ROR, RRF,SBC,STA,STX,STY,TSTExampleNameFunctionMITSUBISHI MICROCOMPUTERSMS0740·XXX5 PSINGLE·CHIP a·BIT CMOS MICROCOMPUTERMemory00'8Zero pageA -- A + C + I Data 1--02,e--: Mnemonic Machine codeADC $02 6516 0216FF'8---------~Zero page~specificationOpcode (65,8)Operand (02,8)~: Zero page X addressing mode: Operation is performed on thememory which address is spe'"Memorycified by adding the operandand contents of index registerZero pageX.A--A+C+ I Data 1-- DataSTY: Mnemonic Machine code .Zero page XADC $1E,X 75 16 1E specification16Instructions : ADD, AND, ASL, CMP, DEC,EOR, INC, LDA, LDY, LSR,ORA, ROL, ROR, SBC, STA,ExampleIIOperand (1E,8) +'"~~Er;'~Contents of1WtIgnored'.MITSUBISHI.... ELECTRIC3-17


60 16 12 16 A0 16 AOC $A012AbsoluteMITSUBISHI MICROCOMPUTERSMS0740-XXXSPSINGLE.CHlp· a·BIT CMOS MICROCOMPUTERName : Zero page Y addressing modeFunction : Operation is performed on thememory which address is specifiedby adding the operandMemoryand contents of index registerY.Instructions : LOX, STXDataZeropageExample : Mnemonic Machine codeLOX $02,Y~-------Zero page Y~~~specificationContents ofindex register YOpcode (86 16 )Operand (02 18 )- -- -+~Name : Absolute addressing modeFunction : Operation is performed on thememory which address is specifiedby first and secondMemory- ---operand.Instructions: AOC, AND, ASL, BIT, CMP,-'"CPX, CPY, DEC, EOR, INC,Opcode (6D 16 )JMP, JSR, LOA, LOX, LOY,Operand I (12 18 )LSR, ORA, ROL, ROR, SBC,Operand II (AD 18 )}-----.STA,STX, STYExample : Mnemonic Machine codespecification~~A-A+C+ I Data I~Data- .-~-3-18.MITSUBISHI.... ELECTRIC.


NameFunction: Absolute X addressing mode: Operation is performed on thememory which address is specifiedby adding the contents ofindex register X and value indicatedfirst and second operand.Instructions: ADC, AND, ASL, CMP, DEC,EOR, INC, LDA, LDY, LSR,ORA, ROL, ROR, SBC, STAExample : Mnemonic Machine codeADC $AD12,X 7D 16 12 16 AD 16NameFunction: Absolute Y addressing mode: Operation is performed on thememory which address is specifiedby adding the contents ofindex register Y and value indicatedfirst and second operand.Instructions: ADC, AND, CMP, EOR, LDA,LDX,ORA,SBC,STAExample : MnemonicADC $AD12,YMachine codeMITSUBISHI MICROCOMPUTERSMS0740-XXXS PSINGLE.CHIP 8·BIT CMOS MICROCOMPUTERMemory",--Contents ofOpcode (70,s)Operand I (12,s)Operand II (AD,s)~~Absolute XspecificationA-A+C+~~DataAEOO,s ~------'" -Memory,- - -Contents ofindex register YOpcode (79,s)Operand I (12,6)Operand II (AD,s)~} + ~ ~ L...--....r--'II;=:::-Absolute YspecificationA-A+C+~+--DataAEOO'6 +-___ ...J- - - -• MITSUBISHI.... ELECTRIC3-19


MITSUBISHI MICROCOMPUTERSMS0740·XXXSPSINGLE-CHIP a-BIT CMOS MICROCOMPUTERNameFunction: Implied addressing mode: Implied addressing mode needno operand.Instructions : SRK, ClC, ClD, CLI, Cl T,ClV, DEX, DEY, FST, INX, INY,NOP, PHA, PHP, PLA, PlP,RTI, RTS, SEC, SED, SEI, SET,, SlW; STP, TAX, TSX, TAY,TXA, TVAExample : Mnemonic Machine codeClC18 18 'PSPSNameFunction: Relative addressing mode: Jumps to address which is producedby adding the contentsof program counter and thecontents of operand.Instructions: SCC, SCS, SEQ, SMI, SNE,SPl,SRA,SVC,SVSExample : Mnemonic Machine codeSCC * -12 90 18 F4 18Jumps to - 12 address whencarry flag(c) is cleared.~-MemoryAddress to beexecuted nextProceed to next address whencarry flag( c) is set.Memory- - -Opcode (90 18 )Operand (F4 18 )Address tQ beexecuted next· *Opcode (90 18 )Operand (F4 18 )101""" --*- -- -3-20.• ·MITSUBISHI;"ELECTRIC


MITSUBISHI MICROCOMPUTERSMS0740-XXXSPSINGLE-CHIP 8-BIT CMOS MICROCOFt1PUTERName : Indirect X addressing modeFunction : Operation is performed on theMemorymemory at address indicatedby contents of consecutive 2Zero pagebyte memory which firstDatal (00address is formed by adding{18 )Datall (14 16 )operand and contents of indexregister X.Zero page XindirectInstructions : ADC, AND, CMP, EOR, LOA,~-------.specificationORA,SBC,STA~Example : Mnemonic Machine codeContents ofindex register XADC ($1E,X) 61 16 1E 16Opcode (61 16 )Operand (1 E 16) +~~1r:~Ignoret~~ Data- -In this example. 00 16 as data I and 14 16 as data II have beenstored beforehand.Name : Indirect Y addressing modeFunction : Operation is performed on thememory addressed by addingMemorythe contents of index register Yand contents of consecutive 2byte zero page memory whichfirst address is specified by ~ Datal (01 118 )operand.Datall (12 16 )+ I E;181='----r----I1Instructions: ADC, AND, CMP, EOR, LOA,Contents ofORA,SBC,STAindex register YZero pageExample: Mnemonic Machine code indirect~-------.ADC ($1E),Y 71 16 1E specification~~16IIOpcode (71 18 )L--- Operand (1 E 18 ),~~Absolute Y specificationData.~Data....--- ---In this example. 00 16 as data I and 12 16 as Data II have beenstored beforehand.• MITSUBISHI.... ELECTRIC3-21


MITSUBISHI MICROCOMPUTERSMS0740-XXXS PSINGLE.CHIP 8·BIT CMOS MICROCOMPUTERName : Indirect absolute addressingmodeFunction : Specifies consecutive 2-bytememories by contents of firstand second operand and jumpsto address indicated by contentsof these memories.Instructions : JMP, JSRExample : MnemonicJMP $1400Machine code6C 16 00 16 14 16-C· Memory~ ..........-Opcode (6C 16 )Operand I (00 16 )Operand II (14 16 )IndirectspecificationDatal (FF 16 )Data II (1E 16 )Address to beexecuted next-.......-Jump*-----JAbsolutespecificationIn this example, FF 16 as data I and 1 E 16 as data II have beenstored beforehand.Name : Zero page indirect absoluteaddressing modeFunction : Specifies consecutive 2-bytememories in zero page area byoperand contents and jumps toadddress indicated by contentsof these memories.Instructions: JMP, JSRExample: MnemonicJMP $05Machine codeB2 16 05 16Zero pageindirectspecification-MemoryDatal (FF 16 )Data II (1E 1S )---------;.Absolutespec.ificationOpcode (82 16 )'---Operand (05 16 )*Address to beexecuted next--- --In this example, FF 16 as data I and 1 E 16 as data II have beenstored beforehand.3-22• MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSMS0740-XXXS PSINGLE-CHIP a-BIT CMOS MICROCOMPUTERName : Special page addressing modeFunction : Jumps to address in specialpage area. 8 high-orderaddress and 8 low-orderaddress of jump distination is1 F 16 and contents of operandrespectively.Instruction : JSRExample : Mnemonic Machine codeJSR ¥$1FEO 22 16 E0 16*rThis symbol denotes specialpage mode.MemoryOperand (E0 16 )*IIAddress to beexecuted nextName : Zero page bit addressingmodeFunction : Operation is performed on thebit specified by 3 high-orderbits of opcode, memoryaddress containing this bit isspecified by operand.Instructions: CLB, SEBExample : MnemonicCLB 5,$04Machine codeBF 16 04 16Zero pagespecificationMemoryBit5~ PI'----r---------~ -;:Bitspecification Opcode+ t1 01 I 10011---Operand (04 16 )1Bit5• MITSUBISHI.... ELECTRIC3-23


MITSUBISHI MICROCOMPUTERSMS0740.XXX5 PSINGLE.CHIP a.BIT CMOS MICROCOMPUTERName : Accumulator bit addressingmodeFunction : Specifies bit in. accumulator by3 high-order bits of opcode.Instructions : CLB, SEBExample : Mnemonic Machine codeCLB 5,ABB 16AccumulatorBlt5Memory-Bi;-specification Opcode.. t101111111----IAccumulator I I ° INameFunction: Zero page bit addressingmode: Operation is performed on thebit specified by 3 high-orderbits of opcode, memoryaddress containing this bit isspecified by operand.Instructions : CLB, SEBExample : MnemonicCLB 5~$04Machine codeBF 16 04 16When accumulator bit 5 isclearedBit5Accumulator ..... , ...,,\,'...0.1.' ___......Jump to * -12 addressMemoryWhen accumulator bit 5 is setAccumulator '_......Bit5'Advance to * addressMemory'_1...'____Address ~x~~uted next * - 1 2Bitspecification OpcodeBitspecification+Opcode+1 ° 1 1 01 1 1Operand (F4,.)Address ~~~guted nest **3-24• MITSUBISHI"'ELECTRIC


MITSUBISHI MICROCOMPUTERSMS0740-XXXS PSINGLE-CHIP a-BIT CMOS MICROCOMPUTERName : Zero page bit relative addressingmodeFunction : Operation is performed on thebit specified by 3 high-orderbits of opcode, memoryaddress containing this bit isspecified by first operand and,depending on the state of thisspecial bit, jumps to theaddress indicated by the valueproduced by adding thesecond operand contents to thecontents of the programcounter.Instructions : BBC, BBS: Mnemonic Machine codeBBC 5,$04,-12 B7 16 04 16 F4 16Jump to * - 12 address when04 16 address bit 5 is cleared.MemoryBit5,..- 101;


MITSUBISHI MICROCOMPUTERSMS0740·XXX5PSINGLE.CHIP a·BIT CMOS MICROCOMPUTERMACHINE INSTRUCTIONSSymbolADC(Note 1)AND(Note 1)FunctionWhen T=OA-A+M+CWhen T=lM (X) -M (X) +M+CWhen T=OA-AI\MWhen T=lM (X) -M (X) 1\ MASL 7 0C - c::=J -0DetailsAdds the carry, accumulato,r and memory contents.The results are entered Into the accumulator.Adds the contents a the memory in the address indicatedby index register X. the cartents a thememory specified by the addressing modes in thecolumns on the right, and the contents a the carry.The results are entered into the memory at theaddress indicated by Index register X."AND-s" the accumulator and memory contents.The results are entered into the accumulator."AND-s" the contents a the memory a the addressindicated by index register X and the cartents a thememory specified by the addressing modes In thecolumns on the right The results are entered into thememory at the address indicated by index register X.l-bit shifts the contents of accumulator or contentsof memory to the left. "0" enters Oth bit ofmemory or accumulator and the contents of the7th bit enter carry flag.IMPOP nAddressing modeIMM A BIT,A ZP BIT,ZP# OP n # OP n # OP n # OP n # OP n #69 2 2 65 3 229 2 2 25 3 2OA 2 1 06 5 2BBC(Note 4)Ab or Mb=O?Branches when the contents of the bit specifiedin the accumulator or memory are "0".134 2~i ~i17 5 3BBS(Note 4)Ab or Mb=l?Branches when the contents of the bit specifiedin the accumulator or memory are "1".07~ 4 22i ~i5 3BCC(Note 4)BCS(Note 4)BEQ(Note 4)BITC=O?C=l?Z=l?AI\MBranches when the contents of carry flag are"0".Branches when the contents of carry flag are"1".Branches when the contents of zero flag are"1"."AND-s" the contents of accumulator and memory.The results are not entered anywhere.24 3 2BMI(Note 4)BNE(Note 4)BPL(Note 4)BRAN=l?Z=O?N=O?PC-PC±offsetBRK B-1M(S)-PCH5-S-1M(5)-PCL5-S-1M(S)-PS5-S-1PCL-ADLPCH-ADHBranches when the contents of negative flagare "1",Branches when the contents of zero flag are"0".Branches when the contents of negative flagare "0".Jumps to address where offset has been addedto the program counter.Executes software interrupt. 00713-26• MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSMS0740·XXX5PSINGLE-CHIP a-BIT CMOS MICROCOMPUTERAddressing modeProcessor status registerZP,X ZP,Y ABS ABS,X ABS,Y INO ZP,INO INO,X INO,Y REL SP 7 6 5 4 3 2 1 0OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # N V T B 0 I Z C75 4 2 60 4 3 70 5 3 79 5 361 6 2 71 6 2 N V· · · · Z C35 4 2 20 43 3D 5 3 39 5 321 6 231 62 N· · · · · Z ·II16 6 2 OE 63 1E 7 3N· · · · · Z C2C 43··90 2 2·BO 2 2FO 2 2··M730 2 2·DO 2 2·10 2 2·80 4 2· · · · · · ·· · · · · · ·· · · · · · ·· · · · · · ·· · · · · · ·M6 •· · · ·Z· · · · · · ·· · · · · ·· · · · · · ·· · · · · ·· · 1 · 1 · ·• MITSUBISHI.... ELECTRIC3-27


MITSUBISHI MICROCOMPUTERSMS0740·XXX5PSINGLE-CHIP a-BIT CMOS MICROCOMPUTERAddressing modeSymbolFunctionBVC V=O?(Note 4)BVS V=l?(Note 4)CLB Ab or Mb-OCLC C-OCLD 0-0CLI 1-0CLT T-OCLV V-ODetailsBranches when the contents of overflow flagare "0."Branches when the contents of overflow flagare "1."Clears the contents of the bit specified in theaccumulator or memory to "0."IMPOP nClears the contents of the carry flag to "0." 18 2Clears the contents of decimal mode flag to 08 2"0."Clears the contents of interrupt disable flag to 58 2"0."Clears the contents of X-modified arithmetic 12 2mode flag to "0."Clears the contents overflow flag to "0." B8 2IMM A BIT,A ZP BIT,ZP# OP n # OP n # OP n # OP n # OP n #111111,2i2 1 1F~i5 2CMP(Note 3)WhenT=OA-MWhen T=lM(X)-MCompares the contents of accumulator andmemory.Compares the contents of the memory specifiedby addressing modes in the columns onthe right with the contents of the address indi-C9 2 2 C5 3 2cated by index register X.COMM-MFormes one's complement of contents of mem-44 5 2ory, and store it into memory.CPXX-MCompares the contents of index register X andmemory.EO 2 2 E4 3 2CPYY-MCompares the contents of index register Y andmemory.CO 2 2 C4 3 2DECA-A-lorM-M-lDecrements the contents of accumulator ormemory by 1.1A 2 1 C6 5 2OEXX-X-1Decrements the contents of index register X by CA 21.1DEYY-Y-1Decrements the contents of index register Y by 88 21.1EOR(Note 1)When T=OA-A¥MWhen T=lM (X) -M (X)¥M"Exclusive-ORs" the contents of accumulatorand memory. The results are stored into theaccumulator."Exclusive-ORs" the contents of the memoryspecified by the addressing modes in the columnson the right and the contents of the mem-49 2 2 45 3 2ory at the address indicated by index registerX. The results are stored into the memory at theaddress indicated by index register X.FSTConnects oscillator output to XOUTF. E2 21INCA-A+lorM-M+lIncrements the contents of accumulator ormemory by 1.3A 2 1 E6 5 2INXX-X+lIncrements the contents of index register X by E8 21.1INYY-Y+lIncrements the contents of index register Y by C8 21.13-28• MITSUBISHI '.... ELECTRIC


MITSUBISHI MICROCOMPUTERSMS0740·XXXSPSINGLE-CHIP 8-BIT CMOS MICROCOMPUTER05 4 2 CD 4Addressing modeProcessor status registerZP.X ZP.Y ABS ABS.X ABS.Y INO ZP.INO INO.X INO.Y REL SP 7 6 5 4 3 2 1 0OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n3 DO 5 3 09 5 3C1 6 2 016# OP n # OP n # N50 2 2·70 2 2······2 NV T B 0 I Z C· · · · · · ·· · · · · · ·· · · · · · ·· · · · · · 0· · · 0 · · ·· · · · 0 · ·· 0 · · · · ·0· · · · · ·· · · · · Z CIIEC 4CC '406 6 2 CE 655 4 2 40 4333 DE 7 33 50 5 3 59 5 341 6 2 516NNNNNN2 N· · · · · Z ·· · · · · Z C· · · · · Z C· · · · · Z ·· · · · · Z ·· · · · · Z ·· · · · · Z ·F6 6 2 EE 63 FE 7 3·NNN· · · · · · ·· · · · · Z ·· · · · · Z ·· · · · · Z ·• MITSUBISHI.... ELECTRIC3-29


MITSUBISHI MICROCOMPUTERSMS0740-XXXSPSINGLE.CHIP I·BIT CMOS MICROCOMPUTERAddressing modeSymbolFunctionDetailsIMPIMMA BIT.A ZP BIT.ZPJMPJSRLDA(Note 2)LDMIf addressing mode is ASSPCL-ADLPCH-ADHIf addressing mode is INDPCL - (ADH• ADL)PCH-(ADH• ADL+1)If addressing mode is ZP, INDPCL - (00. ADL)PCH- (00. ADL + 1)M(S)-PCHS-S-lM(S)-PCLS-S-lAfter executing the above,if addressing mode is ASS,PCL-ADLPCH-ADHIf addressing mode Is SP,PCL-ADLPCH-FFIf addressing mode Is ZP, IND.PCL - (00. ADL)PCH- (00. ADL + 1)When T=OA-MWhen T=lM(X)-MM-IMMJumps to new address.After storing contents of program counter Instack, and jumps to new address.Load accumulator with contents of memory.Load memory indicated by index register X withcontents of memory specified by addressingmode shown in right column.Load memory with Immediate value.OP n:1* OP nA9 2:1* OP n :1* OP n :1* OP n :1* OP n :1*2 A5 3 23C 4 3LDXX-MLoad index register X with contents of memory.A2 22 A6 3 2LDYY-MLoad index register Y with contents of memory.AO 22 A4 3 2LSR 7 0O-CJ-CShift the contents of accumulator or memory tothe right by one bit.Oth bit of accumulator or memory is stored incarry, 7th bit is cleared.4A 2 1 46 5 2NOPORA(Note 1)PC-PC+1When T=OA-AVMWhen T=lM (X) -M (X) VMNo operation. EA 2Produce the logical OR of the contents of memoryand accumulator. The result Is stored inaccumulator.produce the logical OR of contents of memoryindicated by index register X and contents ofmemory specified by addressing mode shownin right column. The result is stored in memoryof address specified by index register X.109 22 05 3 23-30• MITSUBISHI"ELECTRIC


MITSUBISHI MICROCOMPUTERSMS0740·XXX5PSINGLE-CHIP a-BIT CMOS MICROCOMPUTERzp,x ZP,Y ABSOP n# OP n # OP n4C 3Addressing modeProcessor status registerABS,X ABS,Y IND ZP,IND IND,X IND,Y REL SP 7 6 5 4 3 2 1 0# OP n # OP n #.OP n3 6C 5# OF n # OP n # OP n3 B2 4 2# OP n # OP n #N V T B D I Z C· · · · · · · ·20 6302 7 222 5 2· · · · · · ·~IIB5 4 2 AD 43 BD 5 3 B9 5 3A1 62 B162N· · · · · Z ·B6 4 2 AE 4B4 4 2 AC 43 BE 5 33 BC 5 3· · · · · · · ·N ..· · · · Z ·N· · · · · Z ·56 6 2 4E 63 5E 7 30· · · · • Z C15 4 2 OD 43 1D 5 3 19 5 301 6 21162· · · · · · · ·N.· · · · · Z .•f• MITSUBISHI.... ELECTRIC3-31


MITSUBISHI MICROCOMPUTERSMS0740-XXXS PSINGLE.CHIP 8·.IT CMOS MICROCOMPUTERAddressing modeSymbolPHAPHPPLAPLPM(S)-A8-S-1M(S)-PS8-S-18-S+1A-M(S)8-S+1PS-M(S)FunctionROL 7 0CCJ-iQl:JROR 7 0CiQl-+CJ:::::JRRF 7 0~DetailsIMPOP nSaves the contents cI the accumulator in the memory 48 3at the address Indicated by the stack pointer anddecrements the contents cI stack pointer by 1.Saves the contents of processor status register 08 3in the memory at the address indicated by thestack pOinter and decrements the contents ofstack pointer by 1 .Increments the contents cI stack pointer by 1 and 68 4pulls from the memory at the address indicated bythe stack pointer, and store it in accumulator.Increments the contents' of stack pointer by 1 28 4and pulls from the memory at the address indicatedby the stack pointer, and store it in processorstatus register.Connects the carry flag and the accumulator ormemory and rotates the contents to the left by 1bit.Connects the carry flag and the accumulator ormemory and rotates the contents to the right by1 bit.Rotates the contents of memory to the right by 4bits.IMM A BIT,A ZP BIT,ZP:1* OP n :1* OP n :1* OP n :1* OP n :1* OP n :1*11112A 2 1 26 5 26A 2 1 66 5 282 8 2RTIRTSSBC(Note 1)SEBSEC C-1SED 0-18-S+1PS-M(S)8-S+1PCL-M(S)8-S+1PCH-M(S)8-S+1PCL-M(S)8-S+1PCH-M(S)When T=OA-A-M-CWhen T=1M(X)-M(X)-M-CAb or Mb-1Returns from the i,nterrupt routine to the main 40 6routine.Returns from the subroutine to the main routine. 60 6Subtracts the contents of memory and carry flagfrom the contents of accumulator. The resultsare stored into the accumulator.Subtracts contents of carry flag and contents ofthe memory indicated by the addressing modesshown in the columns on the right from thememory at the address indicated by index registerX. The results are stored into the memoryof the address indicated by index register X.Sets the specified bit contents of accumulatoror memory to "I."Sets th~ contents of carry flag to "I." 38 2Sets the contents of decimal mode flag to "I ." F8 21111E9 2 2 E5 3 2C?rB 2 1 Of 5 22i2iSEI 1-1SET T-1SLWSets the contents of interrupt disable flag to 78 2"1."Sets the contents of X-modified arithmetic 32 2mode flag to "I ."Releases the connection between the oscillator C2 2output and pin XOUTF.1113-32.• MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSMS0740-XXXSPSINGLE-CHIP a-BIT CMOS MICROCOMPUTERAddressing modeProcessor status registerZP,X ZP,Y ABSOP n # OP n # OP nABS,X ABS,Y INO ZP,INO INO,X INO,Y REL SP 7 6 5 4 3 2 1 0# OP n # OP n # OP n# OP n # OP n # OP n# OP n # OP n # N··V T B 0 I Z C· · ". · · · ·· · · · · · ·.'N· · · · Z ·(Value saved in stack)II36 6 2 2E 63 3E 7 3N· · · · · Z C76 6 2 6E 63 7E 7 3N· · · · · Z C·· · · · · · ·(Value saved in stack)·· · · · · · ·F5 4 2 ED 43 FO 5 3 F9 5 3E1 6 2F1 62 NV· · · · Z C······ · · · · · ·· · · · · · 1· · · 1 · ·· · · · 1 · ·· 1 · · · ·· · · · · · ·• MITSUBISHI.... ELECTRIC3-33


MITSUBISHI MICROCOMPUTERSMSf)740·XXX5PSINGLE.CHIP a·BIT CMOS MICROCOMPUTERSymbolSTASTPSTXSTYTAXTAYTSTTSXTXATXSTYANote 12Addressing modeFunction Details IMP IMM A BIT,A ZP BIT,ZPOP n :1* OP n :1* OP n :1* OP n :1* OP n :1* OP n :1*M-A Stores the contents of accumulator in the 85 4 2memory.Stops the oscillation of the oscillator. 42 2 1M-X Stores the contents of index register X in the 86 4 2memory.M-Y Stores the contents of index register Y in the 84 4 2memory.X-A Transfers the contents of accumulator to index AA 2 1register X.V-A Transfers the contents of accumulator to index A8 2 1register Y.M=O? Tests whether the contents of memory are "0" 64 3 2or not.X-S Transfers the contents of stack pOinter to index BA 2 1register X.A-X Transfers the contents of index register X to the 8A 2 1accumulator.S-X Transfers the contents of Index register X to the 9A 2 1stack pOinter.A-Y Transfers the contents of index register Y to the 98 2 1accumulator.The number of cycles "n" is added by 3 when T is 1.The number of cycles "n" is added by 2 when T is 1.The number of cycles "n" is added by 1 when T is 1.The number of cycles "n" is added by 2 when branching has occurred.;IMPIMMABIT, AZPBIT, ZPZP,XZP,YABSABS,XABS, YINDZP,INDIND,XIND, YRELSPCZI0BTVNSymbol Contents Symbol ContentsImplied ,addressin~ mode +Immediate addressing mode -Accumulator or accumulator addressing modeAccumulator bit relative addressing mode ¥Zero page addressing mode-Zero page bit relative addressing modeZero page X addressing modeZero page Y addressing modeAbsolute addressing modeAbsolute X addressing modeAbsolute Y addressing modeIndirect absolute addressing modeZero page indirect absolute addressing modeIndirect X addressing modeIndirect Y addressing modeRelative addressing modeSpecial page addressing mode" VXYSPCPSPCHPCLADHADL(ADH, ADL)(00, ADdFFMCarry flagM (X)Zero flagInterrupt disable flag M (8)Decimal mode flagAbBreak flagMbX-modified arithmetic mode flagOPOverflow flagnNegative flag :1*AdditionSubtractionANDORExclusive-ORNegationShows direction of data flowIndex register XIndex register YStack pOinterProgram counterProcessor status registerB high-order bits of program counterB low-order bits of program counterB high-order bits of addressB low-order bits of addressContents of memory at address indicated by ADH andADL, in ADH is B high-order bits and ADL is low-order bits.Contents of address indicated by zero page ADLFF in Hexadecimal notationMemory specified by address deSignation of anyaddressing modeMemory of address indicated by contents of indexregister XMemory of address indicated by contents of stack pointer, bit of accumulator, bit of memoryOpcodeNumber of cyclesNumber of bytes3-34., . MITSUBISH. I..... ELECTRIC.


MITSUBISHI MICROCOMPUTERSMS0740-XXXS PSINGLE-CHIP I-BIT CMOS MICROCOMPUTER96 5 2 8E 594 5 2 8C 5Addressing modeProcessor status registerZP,X ZP,Y ABS ABS,X ABS,Y IND ZP,IND IND,X IND,Y REL SP 7 6 5 4 3 2 1 0OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP nV T B D I Z C95 5 208D 5 3 9D 6 3 99 6 381 7 2 91 7· ·33# OP n # OP n # N2···NNNNN·N., 0· ·· · · · · · ·· · · · · · ·· · · · · ·Z· · · · · ·Z· · · · · ·Z· · · · · ·Z· · · · · ·Z· · · · · · ·· · · · · ·ZII'. MITSUBISHI..... ELECTRIC3-35


MITSUBISHI MICROCOMPUTERSMS0740-XXXSPSINGLE-CHIP a-lilT CMOS MICROCOMPUTERLIST OF INSTRUCTION CODES0 3- Do 0000 0001 0010 0011 01 00 0101 all a 0111 1000 1001 1010 1011 11 00 11 01 1110 111 1A B C00000001ASEB0, ACLB0010001101000101011001111000100110101011110011011110111 13-byte instruction2-byte instruction3-36 • 'MITSUBISHI.... ELECTR.C


MITSUBISHI MICROCOMPUTERSMS0740-XXXS PSINGLE-CHIP a-BIT CMOS MICROCOMPUTERABSOLUTE MAXIMUM RATINGSSymbol Parameter Conditions LimitsVee Supply voltage -0.3-7VI Input voltage, Ro-R3, CNVss, RESET, XIN -0.3-7VI Input voltage, P30-P37 -3. O-Vee+O. 3Input voltage, INT POO-P07, Pl o-P1 7,VI-0.3-13P20-P27, CNTRWith respect to VSS;Va Output voltage, Ro-R3 -0.3-7output transistors cut-offVaOutput voltage, P30-P37, XOUTF, XOUTS,


~~MITSUBISHI MICROCOMPUTERSMS0740-XXXSPSINGLE-CHIP 8-BIT CMOS MICROCOMPUTERTIMING REQUIREMENTSSINGLE CHIP MODE (Vee = 5V±10%, Vss = OV, Ta = 25·C, f (~)= 4MHz, unless otherwise noted)LimitsSymbol Parameter Test conditionsMin Typ Max' Unittsu (POD-\6) Port PO input setup time 270 nstsu (P1D-\6) Port PI input setup time 270 nstsu (P2D-\6) Port P2 input setup time 270 nstsu (P3D-\6) Port P3 input setup time 270 nstsu (RD-\6) Port R input setup time 330 nsth ( ..... POD) Port PO input hold time 0 nsth ( ..... P1D) Port PI input hold time 0 nsth ( ..... P2D) Port P2 input hold time 0 nsth (


MITSUBISHI MICROCOMPUTERSMS0740-XXXSPSINGLE·CHIP a·BIT CMOS MICROCOMPUTERTIMING DIAGRAMSSingle chip modePort PO outputPort PO inputtsuCPOD-¢)IIthC¢ -POD)Port Pl outputPort Pl inputPort P2 outputPort P2 inputPort P3 outputPort P3 inputthc¢ -P3D)• MITSUBISHI.... ELECTRIC3-39


MITSUBISHI MICROCOMPUTERSMS0740·XXX5 PSINGLE-CHIP 8-BIT CMOS MICROCOMPUTERSingle chip mode (continued evaluation)Port R outputtsU(RD- ¢»Port R inputCER/Wf(cP)3--'40• MITSUBISHI.... ELECTRIC


MELPS 8-48 MICROCOMPUTERS


IMITSUBISHI MICROCOMPUTERSMELPS 8-48 MICROCOMPUTERSFUNCTION OF MELPS 8-48 MICROCOMPUTERSDESCRIPTIONThe MELPSS-4S LSI is a family of cost-efficient single-chipmicrocomputers in which all of such necessary compomentsas the CPU, ROM, RAM, input/output ports, timer etc. areintegrated. The MELPSS-4S family consists of the followingtwelve members of different kinds and ROM/RAM capacities.Each chip is provided with a timer and interrupt inputand its I/O capabilities are simply expanded by use of 110expanding chip M5LS243P or M5MS2C43P (CMOS version),in addition the program memory can also be expanded to4K bytes.Each of M5LS04S-XXXP, M5LS049-XXXP, M5LS049H­XXXP, M5M8050H-XXXP, M5MS050L-XXXP and M5MSOC49-XXXP (CMOS version) has a built-in masked ROM and issuited for mass produciton. M5LS035LP has functionsequivalent to M5L8048-XXXP, M5LS039P to M5L8049-XXXP,M5L8039HLP to M5L8049H-5(XXP, M5M8040HP toM5M8050H-XXXP, M5M8040LP to M5M8050L-XXXP andM5M80C39P-6 to M5MSOC49-XXXP where the programmemory (ROM) is set externally.The family is provided with the MELPSS-4S crossassembler as a support for software development.IIMELPS 8-48 single-chip microcomputer familySymbolInput clock(MHz)Memory and input/output capacityROMRAMI/O(Bytes) (Bytes)(Port)StructureM5LB04B-XXXP 61K64 27ED NMOSM5LB035LP 6External64 27ED NMOSM5LB049-XXXP-6 62K12B 27ED NMOSM5LB049-XXXP-8 82K128 27ED NMOSM5L8049-XXXP 82K128 27ED NMOSM5L8039P-6 6External128 27ED NMOSM5L8039P-8 8External128 27ED NMOSM5L8039P-11 11External12B 27ED NMOSM5L8049H-XXXP 112K128 27ED NMOSM5LB039HLP 11External128 27ED NMOSM5M8050H-XXXP 114K256 27ED NMOSM5M8040HP 11External256 27ED NMOSM5M8050L-XXXP 64K256 27ED NMOSM5M8040L-XXXP 6External256 27ED NMOSM5MBOC49-XXXP 62K128 27CMOSM5MBOC39P-6 6External12B 27CMOS• MITSUBISHI;"ELECTRIC4-3


MITSUBISHI MICROCOMPUTERSMELPS 8-~8 MICROCOMPUTERSFUNCTION OF MELPS 8·48 MICROCOMPUTERSMSL8048·XXXP Block DiagramPl. Ph Pl. PI, P2, P2, P2. pZ.PI, Ph Ph Ph P2, P2" P2. P2,T,(SV) VeeRD REGISTER 0Rl REGISTER'R2REGISTERz 0R3REGISTER 3 ~R4REGISTER 4 ~~ R5REGISTERs COo RSREGISTER68 R7REGISTER7~ STACK~ RDREGISTER 0w R1REGISTERlis R2REGISTERz~ R3REGISTERl -R4REGISTER4 ~R5REGIS. TEtJR


MITSUBISHI MICROCOMPUTERSMELPS 8-48 MICROCOMPUTERSFUNCTION OF MELPS 8-48 MICROCOMPUTERSM5L8049H-XXXP Block Diagram( 5V) v FDD(5V) Vee 0(OV) Vss 20FOR POWER RAM SUPPLYRAM (128 BYTES)L--{I.H~}-l6}-{4)--{25}-{7.K2)-{.J}-{n}-{9}--{5)-{8)-{IO)- ---- ---- ---- ---- ---- -To INT PROG Xl ALE SS WRTl RESET EA X 2 PSEN RDT'IIIIIIIJIIM5M8050H-XXXP Block DiagramPIO PI2 PI4 PI6 P20 PZ2 P14 P26PI, PI3 PI5 P1700DI01{))O.OS[),()JRJ REGISTeR 3:LR4RE;GISHR 4 ~(C R5 REGISTER 5 en~ R6 REGISTER 68 R7 REGISTER 7~ STACK(f) RO REGISTE R 0~ Rl REGISTER 12S R2 REGISTER 2 -o R3 REGISTER 3 :L


MITSUBISHI MICROCOMPUTERSMELPS 8-48 MICROCOMPUTERSFUNCTION OF MELPS 8-48 MICROCOMPUTERSM5M8050L-XXXP Block DiagramI--~~~~~~~------------'I ~!i T, !IIIIu~8~gCzz


MITSUBISHI MICROCOMPUTERSMELPS 8·48 MICROCOMPUTERSFUNCTION OF MELPS 8-48 MICROCOMPUTERSBASIC FUNCTION BLOCKSProgram Memory (ROM)The M5L8048-XXXP contain 1024 bytes of ROM. TheM5L8049-XXXP contains 2048 bytes of ROM. The programfor the users application is stored in this ROM. Addresses 0,3, 7 of the ROM are reserved f~r special functions. Table 1shows the meaning and function of these three specialaddresses.Table 1 Reserved, defined addresses and theirmeanings and functionsAddressMeaning and functionThe first instruction executed after a system reset.The first instruction executed after an external interrupt isaccepted.The first instruction executed after a timer interrupt is accepted.The ROM can be used to store constants and other 8-bitfixed data in addition to the program. Instructions such asMOVP A, @A and MOVP3 A, @A can be Used to accessthe constants and data. The data could be in the form oftables, and can be easily looked up.Data Memory (RAM)The M5L8048-XXXP and M5L8748S contain 64 bytes ofRAM. The M5L8049-XXXP contains 128 bytes of RAM.The RAM is used for data storage and manipulation and isdivided into sections for more efficient processing. Addresses()-7 and 24-31 form two banks of general purposeregisters that can be directly addressed. Addresses ()-7compose bank 0 and are numbered RO-R7. Addresses24-31 compose bank 1 and are also numbered RO-R7.Only one bank is active at a time. The instructions SELRBO and SEL RB1 are used to select the working bank.Fig. 1 shows the division of the RAM and its mapping.Addresses 8-23 compose an 8-level program counterstack. The details for using the stack wi" be found in the"Program Counter and Stack" section. Please refer to thatsection for details.The remaining section, addresses 32 and above, mustbe accessed indirectly using the general-purpose registersRO or R1. Of course a" addresses can be indirectly addressedusing the general-purpose registers RO and R 1.A good practice to simplify programming is to reservegeneral-purpose register bank 0 for use of the main programand register bank 1 for interrupt programs. For example ifregister bank 0 (addressed 0-7) is reserved for processingdata by the main program, when an interrupt is acceptedthe first instruction would be to switch the working registersfrom bank 0 to bank 1. This would save the data ofthe main program· (addresses 0-7). The interrupt programcan then freely use register bank1 (addresses 24-31) withoutdestroying or altering data of the main program. Whenthe interrupt processing is complete and control is returnedto the main program by the RETR instruction, registerbank 0 (in this example) is automatically restored as theworking register bank at the same time the main programcounter is restored.Addresses ()-31 have special functions, but when nota" of the registers are required, the ones not needed can beused for general storage. This includes both banks of general-purposeregisters and the stack.3231252423USER RAM32X 8R7I!IR1RO8-LEVEL STACK16x 8R7IIR1RO1Fig_ 4 Data memory (RAM)]}GENERAL_PLJRPOSE REGISTERSREGISTER BANK 1GENERAL_PURPOSE REGISTERSREGISTER BANK 0PROGRAM COUNTER (PC) AND STACK (SK)The MELPS 8-48 program counter is composed of a 12-bitbinary counter as shown in Fig. 5. The low-order 10 bitscan address 1024 bytes of memory. When the high-order 2bits are zero, the internal, on chip memory is accessed. Thehigh-order 2 bits can have the values 1-3, which allows theuser to add up to three banks of 1024 bytes. The programcounter can address up to 4096 bytes of memory.Addresses 8-23 of RAM are used for the stack (programcounter stack). The stack provides an easy and automaticmeans of saving the program counter and other controlinformation when an interrupt is accepted or a subroutineis called. For example, if control is with the main programand an interrupt is accepted, the contents of the 12-bit PC(program counter) is saved in the top of the stack, so it canbe restored when control is returned to the main program.In addition to the PC, the high-order 4 bits of the PSW(program status word) are saved in the stack and restoredalong with the PC. A total of 16 bits are saved, the 12-bitII• MITSUBISHI"ELECTRIC4-7


MITSUBISHI MICRoCOMPUTERSMELPS 8-48 MICROCOMPUTERS. FUNCTION OF MELPS 8-48 MICROCOMPUTERSPC and 4 bits of the P5W. A 3-bit stack pointer is associatedwith the stack. This pointer is a part of the P5W andindicates the top of the stack. The stack pointer indicatesthe next empty location (top of the stack), in Clise of anempty stack the top of the stack is the bottom of the stack.The data memory addresses associated with the stackpointer along with the data storage sequence are shown inFig. 6.Fig. 5 Program counterSTACK POINTERRAM REGISTER NUMBER(DATA MEMORY ADDRESS)S2 SI S a1 I R23IR22I R210I R20o 1 I R19I R18o 0 I R17I R161I R15I R14II R130I R12I R11o 1IR10PS",,(4)jPCg_ll R9o 0PC4-7IpCa- 3 R8MSB LSBPROGRAM STATUS WORD (PSW)The P5W (program status word) is stored in 8 bits ofregister storage. The configuration of the PSW is shown inFig. 7.1he high-order 4 bits of the PSW are s~ored in thestack, along with the PC, when an interrupt is accepted ora subroutine call executed. When control is returned tothe main program by RETR both the PC and the highorder4 bits of PSW are restored. When control is returnedby RET only the PC is restored, so care must be taken to, assure that the contents of the P5W was not unintentionallychanged.The order and meaning of the 8 bits of the P5W areshown below.Bit 0-2:5tackpointer (50,5 1 ,5 2 )Bit 3: Unused (always 1)Bit 4: Working register bank indicator0= Bank 01 = Bank 1Bit 5: Flag 0 (value is set by the user and can be tested)Bit 6: Auxiliary carry (AC) (it is set/reset by instructionsADD and ADC and used by instruction DA A).Bit 7: Carry bit (t) (indicates an overflow after execution)HIGH-ORDER 4 BITS STOREDALONG WITH THE PC IN-THE STACKC CARRYAC : AUXILIARY CARRY' (CARRY FROM THELOW-ORDER 4 BITS OF ALU)Fa FLAG 0BS WORKING REGISTER BANK INDICATORSTACK POINTERFig. 6 Relation between the program counterstack and the stack pointerFig. 7 Pr.ogram status word4-8 • MITSUBISHI..... ELECTRIC


MITSUBISHI MICROCOMPUTERSMELPS 8-48 MICROCOMPUTERSFUNCTION OF MELPS 8-48 MICROCOMPUTERSI/O PORTSThe MELPS 8-48 has three 8-bi~ ports, which are calleddata bus, port 1 and port 2.Port 1 and Port 2Ports 1 and 2 and both 8-bit ports with identical properties.The output data of these ports are retained and do notchange until another output is loaded into them. Whenused as inputs the input data is not retained so the inputsignals must be maintained until an input instruction isexecuted and completed.Ports 1 and 2 so-called quasi-bidirectional ports havea special circuit configuration to accomplish this. Thespecial circuit is shown in Fig. 8. <strong>Al</strong>l terminals of ports1 and 2 can be used for input or output.CPUINTERNALBUSRESETWRITEPULSEFig. 8 I/O ports 1 and 2 circuitInternal on chip pull-up resistors are . provided for allthe ports. Through the use of pull-up resistors, TTL standardhigh-level or low-level signals can be supplied. Thereforeeach terminal can be used for both input and output. Toshorten switching time from low-level to high-level, when 1sare output, a device of about 5kn or lower is inserted fora short time (about 500ns when using a 6MHz crystal oscillator).A port used for input must output all 1 s before it readsthe data from the input terminal. After resetting, a port isset to an input port and remains in this state, therefore itis not necessary to output all 1 s if it is to be used for input.In short a port being used for output must output 1 s beforeit can be used for input.The individual terminals of quasi-bidirectional portscan be used for input or output. Therefore some terminalscan be in the input mode while the remaining terminalsof a port are in the output mode. This capability of ports1 and 2 is convenient for inputting or outputting 1-bit ordata with few bits. The logical instructions ANL and ORLcan easily be used to manipulate the input or output ofthese ports.Data Bus (Port 0)The data bus is an 8-bit bidirectional port, which is usedwith I/O strobed signals. When the data bus is used foroutput the output data is latched, but if it is used for inputthe data is not latched. Unlike ports 1 and 2, which canhave individual terminals in the input or output mode, allterminals of the data bus are in the input or output mode.When the data bus is used as a static port the OUTL instructioncan be used to output data and the I NS instructionto input data. Strobe pulse RD is generated while theINS instruction is being executed or WR while OUTL is.being executed.The data bus read/write using MOVX instructions, butthen the data bus is a bidirectional port. To write into thedata bus a WR signal is generated and the data is vaiid whenWR goes high. When reading from the data bus, an RD signalis generated. The input levels must be maintained untilRD goes high. When the data bus is not reading/writing, itis in the high-impedance state.CONDITIONAL JUMPS USING TERMINALS To.Tl and INTConditional jump instructions are used to alter programdepending on internal and external conditions (states).Details of the jump instructions for the MELPS 8-48 canbe found in the section on machine instructions.The input signal status of To, T 1 and I NT can be checkedby the conditional jump. instructions. These inputterminals, through conditional jump instructions such asJTO and JNTO, can be used to control a program. Programsand processing time can be reduced by being ableto test data in input terminal rather than reading the datainto a register and then testing it in the register.Terminal To, Tl and INT have other functions and usesthat are not related to conditional jump instructions. Thedetails of these other functions and uses can be found inthe section on terminal functions.II• MITSUBISHI.... ELECTRIC4-9


, MITSUBISHI MICROCOMPUTERSMELPS 8-48 MICROCOMPUTERSFUNCTION OF MELPS 8-48 MICROCOMPUTERSINTERRUPTThe. CPU recognizes an external interrupt by a low-levelstate at the INT terminal. A ''Wired-OR'' connection canbe used for checking multiple interrupts.The INT terminal is tested for an interrupt request at theALE signal output of every machine cycle. When an interruptis recognized and accepted, control is transferred tothe interrupt handling program. This is accomplished by anunconditional jump to address 3 of program memor¥,which is the start of the interrupt handling program, at thesame time the program counter and 4 high-order bits ofPSW are automatically moved to the top of the stack.The interrupt level is one, so the next interrupt cannotbe accepted until the current interrupt processing has beencomple~d. The RETR instruction terminates the interruptprocessing. That is to say, the next interrupt can not be accepteduntil the RETR instruction is executed. The nextinterrupt can be accepted at the start of the second cycle ofthe R ETR instruction (2-cycle instruction). Time/eventcounter overflow which causes an interupt request also willnot be accepted.After the processing for an interrupt is completed controlis returned to the main program. This is accomplishedby executing RETR which restores the program counterand PSW automatical and checks INT and the time/eventcounter overflow for an interrupt request. If there is aninterrupt request, the control will not be returned to themain program but will be transferred to the interrupt handlingprogram.An external interrupt has a higher priority than a timerinterrupt. This means that, if an external and timer interruptrequest are generated at the same time, the externalinterrupt has the priority and will be accepted first.When a second level of external interrupt is required,the timer interrupt, if not being used, can provide this.The procedure for this is to first disable the timer interrupt,set the timer/event counter to FF16 and put the CPUin the event counter mode. After this has been done, if T 1input is changed to low-level from high-level, an interruptis generated in address 7.Terminal INT can also be tested using a conditionaljump instruction. For more details on this procedure, checkthe "Conditional Jumps Using Terminals To, T 1 and I NT"section.TIMER/EVENT COUNTERThe timer/event counter for the MELPS 8-48 is an 8-bitcounter, that is used to measure time delays or count externalevents. The same counter is used to measure time delaysor count external events by simply changing the inputto the counter.The. counter can be initialized by executing an MOV T,A instruction. The value of the counter can be read forchecking by executing an MOV A, T instruction. Reset willstop the counting but the counter is not cleared, so countingcan be resumed.The largest number the counter can contain is FF16 . Ifit is incremented by 1 when it contains FF16 , the counterwill be reset to 0, the overflow flag is set and a timer interruptrequest is generated.The conditional jump instruction JTF can be used totest the overflow flag. Care must be used in executing theJTF instruction because the overflow flag is cleared (reset)when executed. When a timer interrupt is accepted, thecontrol is transferred to address 7 of program memory.When both a timer and external interrupt request areg,enerated at the same time, the external interrupt is givenpriority and will be accepted first by automatically jumpingto address 3 of program memory. The timer interruptrequest is kept and will be processed when the externalinterrupt has been completed and a PETR is executed. <strong>Al</strong>atched timer interrupt request is cancelled when a timerinterrupt request is generated. A timer interrupt request canbe disabled by executing a 0 IS TCNTI instruction.The STRT CNT instruction is used to change the counterto an event counter. Then terminal T 1 signal becomesthe input to the event counter and an event is counted eachfull cycle (low-high-Iow one event). The maximum rate thatcan be counted is one time in 3 machine cycles (7.5J.Lswhen using 6MHz crystal). The high-level at Tl must bemaintained at least 1/5 of the cycle time (500ns whenusing 6MHz crystal).4-10 • . MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSMELPS 8-48 MICROCOMPUTERSFUNCTION OF MELPS 8-48 MICROCOMPUTERSThe STRT T instruction is used to change the counterto a timer. The internal clock signal becomes the input tothe timer. The internal clock is 1/32 of 400kHz (whenusing 6M Hz crystal) or 12.5kHz. The timer is thereforecounted up every 80ps. Fig. 9 shows the timer/eventcounter.The counter can be initialized by executing an MOV T,A instruction. The timer can be used to measure 80ps'"20ms in multiples of 80ps. When it is necessary to measureover 20ms (maximum count 256x80ps) of delay time thenumber of overflows,one every 20ms, can be counted bythe program. To measure times of less than 80ps; externalclock pulses can be input through T 1 while the counter isin the event counter mode. Every third (or more) ALE signalcan be used instead of an external clock.I, irONDI:ONAjJUMPMELPS 8-48 CYCLE TIMINGThe output of the state counter is 1/3 the input frequencyfrom the oscillator. When a 6MHz crystal is used for input,the output would be 2MHz (500ns). A eLK signal is generatedevery 500ns (one state cycle) which is used for thedemarcation of each machine state. The instruction ENTOeLK will output the elK signal through terminal To. Theinput of the cycle counter is eLK (state cycle) and the outputis an ALE signal which is generated every 5 statecycles.Fig. 11 Shows the relationship between clock and generatedcycles.One machine cycle contains 5 states with a eLK signalfor demarcation of each state. The MELPS 8-48 instructions.are executed in one machine cycle or two machine cycles.An instruction cycle can be one or two machine cyclesas shown in Fig.12.IIT1I JTFI TI~ERIOVERFLOW,FLAGINTERRUPT ENABLEINTERRUPTREQUESTFig. 9 Timer/event counterFig.10 Clocking cycle generation_I~ClK(OUTPUT TO To)500ns(WHEN USING A 6MHz CRYSTAL)52 53 54 55 51 52 53 54 55~~WL~~,...I1..J"1.~~~ALEr-h r-II.P5ENRDWR ~PROGIFlg.11 Clock and generated cycle sIgnalsINSTRUCTION EXECUTION2 MACH I NE CYCLES 1--+--+-___5o --'i)l_s____-iFig.12 Instruction execution timing• MITSUBISHI"ELECTRIC4-11


MITSUBISHI MICROCOMPUTERSMELPS 8-48 MICROCOMPUTERSFUNCTION OF MELPS 8·48 MICROCOMPUTERSRESE.The reset terminal is for resetting the CPU. A Schmitt triggercircuit along with a pull-up register are connected to iton the chip. A reset can easily be generated by attaching al~F as capacitor as shown in Fig. 13. An external resetpulse applied at RESET must remain at low-level for atleast 50ms after power has been turned on and reached itsnornial level.The reset function causes the following initializationwithin the CPU.1. Program counter is reset to O.2. Stack pointer is reset to O.3. Register bank is reset to O.4. Memory bank is reset to O. '5. Data bus is cleared to high-impedance state.6. Ports 1 and 2 are reset to input mode.7. External and timer interrupts are reset to disablestate.8. Timer is stopped.9. Timer overflow flag is cleared.10. Flags Fo and F. are cleared.11. Clock output for terminal To is disabled.Note 1:On the M5L8748S the RESET terminal, in addition to being used for thereset function, is also used when reading and writing data inthe EPROMon the ch ip. Oetails on this will be found in the section on reading andwriting data in th~ M5L8748S,SING LE-STEP OPERATIONThe terminal SS on the MELPS 8-48 is provided to facilitatesingle-step operation. In single-step operation, the CPUstops after the execution of each instruction is completedand the memory address (12 bits) of the next instructionto be fetched is output through the data bus (8 bits) plusthe low-order 4 bits of port 2 (P 20 ""P 23 ). The user can'use this to trace the flow of this pro~ram instruction byinstruction and will find this an aid in program debugging.Single-step operation is controlled through SS and ALE asshown in Fig. 14.5V(a)SINGLE·STEPMODE5V5VCLOCK10kQBUFFERExample of single step circuit55M5L8048-XXXPALEMELPS8-485VDATA BUS ~ :00- 08 TH, E, LOW-ORDER 8 BITS OF PC(PCa-- PC7)~--~------~~--------~THELOW-ORDER4 BITS OFPORT 2P2o- P2 3THE HIGH·ORDER 4 BITS OF PC(PCs-PC,,)1 Ff tLW,10VABOUT200kn(b) Single-step operation timingIEXECUTING"IEINSTRUCTIONFig. 13 Example of a reset circuitFig.14 Single-step operation circuit and timingA type D flip-flop with preset and reset terminals, as shownin Fig. 11, is used to generate the signal for SS. When thepreset terminal goes to low-level, SS goes to high-level,which puts the CPU in RUN mode. When the preset terminalis grounded it goes to high-level. Then SS goes to lowlevel.When SS goes to low-level, the CPU stops. Then whenthe push-button switch is pushed, a pulse is sent to theclock terminal of the type D flip-flop which turns SS tohigh-level. When SS goes to high-level the CPU fetches the4-12 'MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSMELPS 8·48 MICROCOMPUTERSFUNCTION OF MELPS 8-48 MICROCOMPUTERSnext instruction and begins to execute it, but then an ALEsignal is sent to the reset terminal of the type D flip-flopwhich turns SS to low-leveL The CPU again stops as soonas execution of the current instruction is completed. Whenthe push-button switch is again pushed, the cycle is repeatedand the CPU is in single-step operation as shown in Fig.12. While the CPU is stopped in single-step operation, thedata bus and the low-order 4 bits of port 2 are used to outputthe memory address of the next instruction to be fetched.This interferes with input and output, but essentialinput/output can be latched by using the rising edge ofALE as clock.Central Processing Unit (CPU)Central Processing Unit (CPU) is composed of an 8-bit parallelarithmetic unit, accumulator, flag flip-flop and instructiondecoder. The 8-bit parallel arithmetic unit has circuitry to perform the four basic arithmetic operations(plus, minus, multiply and divide) as well as logical operationssuch as AND and OR. The flag flip-flop is used toindicate status such as carry and zero. The accumu latorcontains one of the operations and the result is usuallyretained in the accumulator.WHEN SS IS LOW, THE CPU RECOGNIZES THATIT IS TO STOP.~WHEN THE NEXT INSTRUCTION IS FETCHED,THE CPU SETS SWITCHES SO IT WI LL STOP AFTERTHE EXECUTION OF THE INSTRUCTION IS COM-PLETED.~WHEN ALE IS HIGH, THE MEMORY ADDRESS OFTHE NEXT INSTRUCTION TO BE FETCHED IS OUT-PUT THROUGH THE DATA BUS 18 BITS) AND THELOW-ORDER 4 BITS OF PORT 2.~WHEN SS IS RETURN'ED TO HIGH LEVEL THECPU RECOGNIZES THAT IT IS IN THE RUN MODE.THEN THE ALE SIGNAL GOES TO LOW-LEVELWHICH INDICATES THE CPU IS IN THE RUN MODEAND THAT IT IS EXECUTING INSTRUCTIONS.~IF THE CPU IS IN THE SINGLE-STEP MODE IPRE-SET TERMINAL GROUNDED). AS SOON AS ALEGOES TO LOW-LEVEL, SS GOES TO LOW-LEVELISTOP). IF THE CPU IS THE RUN-MODE IPRE-SET TERMINAL NOT GROUNDED), SS WILL RE-MAIN AT HIGH-LEVEL.IIFig. 15 CPU operation in single-step mode• MITSUBISHI"ELECTRIC4-13


MITSUBISHI MICROCOMPUTERSMELPS 8·48 MICROCOMPUTERSFUNCTION OF MELPS 8-48 MICROCOMPUTERSMACHINE INSTRUCTIONS'S TypeMnemonicMOV A. ;i:nI nstruction code0706 Os 04 030201 Do0 0 1 0 0 0 1 1"7"8"5"4 "3"2"'"0Hexadecimal23ID~ Uco ~2 ,2 (A)~nFunctionEffectedcarryQ)0 AO 0zDescriptionTransfers data n to register A.MOV A. PSW1 1 0 0 0 1 1 1C7(A)~(PSW)Transfers the contents of'the program statusword to register A.MOV A. Rr1 1 1 1 1 r 2 r,r OF8+(A)~(Rr)r= 0 - 7Transfers the contents of register Rr toregisterA.MOV A. @Rr1 1 1 1 0 0 oroFO+(A)~(M(Rr»r=O-lTransfers the contents of memory location,of the current page, whose address is in registerRr to register A.MOV PSW. A1 1 0 1 0 1 1 107(PSW)~(A)(0)~(A7), (AO)~(A6)Transfers the contents of register A to theprogram status word.MOV Rr. A1 0 1 0 1 r 2 r,r OA8+(Rr)~(A)r=0-7Transfers the contents of register A to registerRr.MOV Rr. ;i:n1 0 1. 1 1 r2 r, ro"7"11"5"4 "3"2"'"0B8+(Rr)~nr=0-7Transfers data n to register R r .J Q;MOV @Rr. A~.=MOV @Rr. #nMOVP A. @A1 0 1 0 0 0 oro1 0 1 1 0 0 Oro"7"11"5"4 "3"2"'"01 0 1 0 0 0 1 1AO+BO+A3(M(Rr»~(A)r=O-l(M(Rr»~nr=O-l(A)~(M(A»Transfers the contents of register A to memorylocatipn, of the current page. whose addressis in register R r.Transfers data n to memory location, of thecurrent page, whose address is in register Rr.Transfers the data of memory location, ofthe current page, whose address is in registerA to register A.MOVP3 A. @A1 1 1 0 0 0 1 1E3(A)~(M(page 3, A»Transfers the data of memory location, ofpage 3, whose address is in register A toregister A.MOVX @Rr. A10 0 1 0 0 oro90+(Mx(Rr»~(A)-r=O-lTransfers the contents of register A to memorylocatior" of the current page, whoseaddress is in register Rr.MOVX A. i!>Rr1 0 0 0 0 0 oro80+(A)~(Mx(Rr»r=O-lTransfers the contents of memory location,of the current page, whose address is in registerRr to register A.XCH A. Rr0 0 1 0 1 r 2 r,r O28+(A)~(Rr)r=0-7Exchanges the contents of register Rr withthe contents of register A.Ju~XCH A. @RrXCHD A. @RrADD A. #nADD A. RrADD A. (aRrADOC A. ;i:nAODC A. RrADDC A. @Rr0 0 1 0 0 0 oro0 0 1 1 0 0 oro0 0 0 0 0 0 1 1"7"11"5"4 "3"2"'"00 1 1 0 1 r 2 r,r O0 1 1 0 0 0 oro0 0 0 1 0 0 1 1"7"11"5"4 "3"2"'"00 1 1 1 1 r 2 r,r O0 1 1 1 0 0 oro20+30+0388+60+1378+70+(A)~(M(Rr»r=O-l(Ao-A3)+----+(M (Rro-Rr3»r=O-l(A)~(A)+n(A)~(A)+(Rr)r=0-7(A)~(A)+(M(Rr»r=O-l(A) ~ (A)+ n+(O)(A) ~ (A)+(Rr)+(O)r=0-7(A) ~ (A)+(M (Rr» + (0)r=O-lExchanges the contents of memory location,of the current page, whose address is in registerRr with the contents of register A.Exchanges the contents of the low-order fourbits of register A with the low-order fourbits of memory location, of the currentpage, whose address is in register R r.Adds data n to the contents of register Aand sets the carry flags to0 0 11 if t here is anoverflow otherwise resets the carry flagsto O. The resu It is stored in register A.Adds the contents of register R r to the con-0 0 1tents of register A and sets the carry flags to 1 ifthere is an overflow otherwise resets,the'carryflags to O. The result is stored in register A.Adds the contents ot register A and the contentsof memory location, of the current page,0 0 1 whose address is in register A and sets the carryflags to 1 if there is an overflow otherwise resetsthe carry flags toO.Theresult is stored in registerA.Adds the carry and data n to the contents of0 0 1register A and sets the carry flags to 1 ifthere is an overflow otherwise resets thecarry flags to O. The result is stored in registerA.Adds the carry. and the contents of registerRr to the contents of register A and sets the0 0 1 carry f lags to 1 if there is an overflowotherwise resets the carry flags to O. Theresult is stored in register A.Adds the carry and the contents ot memorylocation, of the current page, whose address is0 0 1 in register R r to the contents of register A andsets the carry flags.to 1 if there is an (lverflowotherwise resets thecarryflagstoO. The resultis stored in register A.4-14• MITSU. BISHI..... ELECTRIC


MITSUBISHI MICROCOMPUTERSMELPS 8-48 MICROCOMPUTERSFUNCTION OF MELPS 8-48 MICROCOMPUTERS~ TypeMnemonicANL A, ItnANL A, RrANL A, (gRrI nstruc'tion codeD7 D6D5 O. 0 3 02 0 1 0 00 1 0 1 0 0 1 1"7"6"5"4 "3"2"'"00 1 0 1 1 r.2 r, r 00 1 0 1 0 0 o roHexadecimal5358+50+., ~>-Uco >-UFunction(A)~(A)An(A)~(A)A(Rr)r=0-7(A)~(A) A(M(Rr»r=O-1Effectedcarry.,C AC 0zDescriptionThe logical product of the contents of registerA and data n, is stored in register A.The logical product of the contents of registerA and the contents of register R" isstored in register A.The logical product of the contents ofregister A and the contents of memory location,of the current page, whose address isin register R" is stored in register A.ORL A, ItnORL A, RrORL A, (gRrXRL A, Itn0 1 0 0 0 0 1 1"7"6"5"4 "3"2","00 1 0 0 1 r2 r, ro0 1 0 0 0 0 oro1 1 0 1 0 0 1 1"7"6"5"4 "3"2"'"01 1 0 1 1 r 2 r, r 0u XRL A, Rr;:;~1 1 0 1 0XRL A, cgRr~INC A0 oro0 0 0 1 0 1 1 14348+40+0308+DO+1 7(A) ~ (A)Vn(A) ~ (A) V (Rr)r=0-7(A)~(A)V (M(Rr»r=O-12 (A)~(A)Vn(A) ~ (A)V- (Rr)r=I-7(A)~(A)V (M(Rr»r=O-1(A)~(A)+1The logical sum of the contents of registerA and data n, is stored in register AThe logical sum of the contents of register Aand the contents of register R, is stored inregister A.The logical sum of the contents of register Aand the contents of memory location, ofthe current page, whose address is in registerR" is stored in register A.The exclusive OR of the contents of registerA and data n, is stored in register A.The exclusive OR of the contents of registerA and the contents of register R, is storedin registerA.The exclusive 0 R of the contents of registerA and the contents of memory location, ofthe current page, whose address is in registerR" is stored in register A.I ncrements the contents of register A by 1.The result is stored in register A, and the carriesare unchanged.IIDEC A0 0 0 0 0 1 1 107(A)~(A)-1Decrements the contents of register A by 1_The result is stored in register A, and the Carriesare unchanged.CLR A0 0 1 0 0 1 1 127(A)~OClears the contents of register A, resets toO.CPL A0 0 1 1 0 1 1 137(A)~(A)Forms 1 's complement of register A, andstores it in register ADA ASWAP A0 1 0 1 0 1 1 10 1 0 0 0 1 1 15747(A)~(A) 10 Hexadecimal(A4-A7)~ (Ao-A3)0 0 1The contents of register A is converted to bi narycoded decimal notion, and it is stored in registerA.lf the contents of register Aare morethan99the carry flags are set to 1 otherwise they arereset to O.Exchanges the contents of bits 0-3 of regis:ter A with the contents of bits 4-7 of registerARL A1 1 1 0 0 1 1 1E 7(An+,)~(An)(Ao)~(A7) n=0-6Shifts the contents of register A left one bit.A7 the MSB is rotated to Ao the LSBRLC A1 1 1 1 0 1 1 1F 7(An+,)~(An)(Ao)~(C)(C)~(A7) n=0-60Shifts the contents of register A left one bit.A7 the MSB is shifted to the carry flag andthe carry flag is shifted to Ao the LSB.RR A0 1 1 1 0 1 1 177(An)~(An+l)(A7)~ (Ao) n=0-6Shifts the contents of register A right onebit. Ao the LSB is rotated to A7 the MSB.RRC A0 1 1 0 0 1 1 167(An)~(An+l)(A7)~(C)(C)~(Ao) n=O- 60Shifts the contents of register A right onebit. Ao the LSB is sh if ted to the carry flagand the carry flag is shifted to A7 the MSB.INCRrI;:;INC cgRr'g>a: * DEC Rr0 0 0 1 1 r2r,rO0 0 0 1 0 0 o ro1 1 0 0 1 r2r,rO18+10-+C8+(Rr)~(Rr)+lr=0-7(M(Rr»~(M(Rr» + 1r=O-1(Rr)~(Rr)-lr= 0- 71 ncrements the contents of register R, by1. The result is stored in register R, and thecarries are unchanged.Increments the contents of the memorylocation, of the current page, whose addressis in register R, by 1. Register R, uses bit0-5.Decrements the contents of register R, by1. The result is stored in register R, and thecarries are unchanged.• MITSUBISHI.... ELECTRIC4-15


MITSUBIS,HI MICROCOMPUTERSMELPS 8-48 MICROCOMPUTERSFUNCTION OF MELPS 8-48 MICROCOMPUTERS~.TypeMnemon'icInstruction codeHexa-07060S 0 4 03 0 2 0 1 0 0 decimal1 2b 7 be b s 1 0 0 1 0JBb m + 2m7me mSm4 m3 m 2 ml m ObX2mJTF mJNI m0 0 0 1 0 1 1 0 16m7 me mSm4 m3 m 2 ml m O m1 0 0 0 0 1 1 0 8 6m7n1&m5m4 m3m2ml mO m04JMP m ml0m g ma O 0 1 0 0 .+(mB- ml0) 2m7me mSm4 m3 m2 m ,mOX2mJMPP @A 1 0 1 1 0 0 1 1 B3 1E81 1 1 0 1 r 2 r 1 roDJNZ Rr, m +rm7 me mS,m4 m3 m 2 ml m O mJC m1 1 1 1 0 1 1 0 F6m7me mSm4 m3 m2 m,mO m1 1 1 0 0 1 1 0 E6JNC ma.m7me mSm4 m3 m2 m,mO m~ 1 1 0 0 0 1 1 0 C6JZ mm7me mSm4 m3 m2 m,mO m~en222222~u0Function(Ab)=1 then (PCO-PC7)+-m2 (Ab) =0 then (PC) +- (PC) +2b7b6bs= 0 - 722(TF) = 1 then (PCO-PC7)+-m(TF) =0then (PC)+-(PC) + 2(PCa-PC?) - m when (INT) = 0(PC) +- (PC) + 2 when (INT) = 1(PCs-PC 10)+-ms-mlO2 ( PC O-PC7)+-mO-m7(PCll) +- (MBF)2 (PCo-PC7)+-(M (A»(Rr) +- (Rr)-1 r=0-72 (RrH'O then (PCO-PC7)+-m(Rr)=O then (PC)+-(PC)+ 2222(C)=1 then (PCO-PC7)+-m(C)=O then (PC) +- (PC) + 2(C)=O then (PCO-PC7)+-m(C)=1 then (PC) +- (PC) +2(A)=O then ( PC O- PC 7)+-m(A)*O then (PC)+-(PC)+2Effectedcarry'"zC AC 0DescriptionJumps to address m of the current page whenbit b of register A is 1. Executes the nextinstruction when bit b of register A is O.Jumps to address m of the current pagewhen the overflow flag of the timer is 1otherwise the next instruction is executed.F lag is cleared after executing.This instruction causes a jump to theaddress indicated by the second byte if theexternal interrupt pin INT is low.Jumps to address m on page ml0 mg ms inthe memory bank indicated by MBF.Jumps to the memory location, of the currentpage, whose address is in register A.'But when the instruction executed was inaddress 255, jumps to next p.age.Decrements the contents of register R, by 1.Jumps to address m of the current pagewhen the result is not 0, otherwise thenextinstruction is executed.Jumps to address m of the current page ifthe carry flag C is I, otherwise the nextinstruction is executed.Jumps to address m of the current page ifthe carry flag C is 0, otherwise the nextinstruction is executed.Jumps to address m of the current pagewhen the contents of register A are 0,otherwise the next instruction is executed.JNZ m1 0 0 1 0 1 1 0 96m7mBmS~ m3 m2 m,mO m22(A)*O then ( PC O- PC 7)+-m(A)=O then (PC) +- (PC) +2Jumps to address m of the current pagewhen the contents of register A are not 0,otherwise the next instruction is executed.JTO m0 0 1 1 0 1 1 0 36m7 me mSm4 m3 m2 m,mO m?2(To) =1 then ( PCO- PC 7)+-m(To) =0 then (PC)+-(PC)+2Jumps to address m of the current pagewhen 'flag To is 1 otherwise the next instruc·tion is executed.JNTO m0 0 1 0 0 1 1 0 26m7me mS m4 m3 rn2 m,mO m22(To) =0 then (PCO- PC 7)+-m(To) =1 then (PC) ~- (PC) + 2Jumps to address m of the current pagewhen flag To is 0, otherwise the next instructionis executedJT1 m0 1 0 1 0 1 1 0 56m7 me mSm4 m3 m2 m ,mO m22(Tl) =1 then ( PC O- PC 7)+-m(T 1 )=0 then (PC) +- (PC) +2Jumps to address m of the current pagewhen flag Tl is 1. otherwise the next instructionis executed,JNT1 m0 1 0 0 0 1 1 0 46m7me mS m4 m3 m2 m,mO m22(Tl)=O then ( PCO- PC 7)+-m(T 1 )=1 then (PC)+-(PC)+2Jumps to address m of the current pagewhen flag Tl is O. otherwise the next instructionis executed.1 0 1 1 0 1 1 0 B6JFO m 2m7 me mSm4 m3 m 2 ml m O m2(Fa) =1 then ( PC O- PC 7)+-m(Fo) =0 then (PC)+-(PC)+2Jumps to address m of the current pagewhen flag Fo is 1.JF1 m0 1 1 1 0 1 1 0 76m7me mSm4 m3 m 2 ml m O m22(Fl) =1 then (PCO- PC 7)+-m(F 1 ) =0 then (PC) +- (PC) + 2Jumps to address m of the current pagewhen flag F 1 is 1.CLR C1 0 0 1 0 1 1 19711 (C) +- 00Clear~ the carry flag C, resets it to O. AC isn9t affected,CPL C1 0 1 0 0 1 1 1A7 11 (C)+-(O)0Complements the carry flag C. AC is notaffected.g CLR Fo 1 0 0 0 0 1 0 1885 1C>coLi: CPL Fo1 0 0 1 0 1 0 195 11 (Fo) +-01 (Fa) +-


MITSUBISHI MICROCOMPUTERSMELPS 8-48 MICROCOMPUTERSFUNCTION OF MELPS 8-48 MICROCOMPUTERSIS TypeMnemonicI nstruction codeD, D6 D5D4 D 3 'D z D, DoCALL m m10m9ma 1 0 1 0 0 14+ems-m,o)X2m7 me mS rn4 m3 m 2 m 1 m O~Q)c: RET 1 0 0 0 0 0 1 1 83::J0.0::J(/)RETR10 0 1 0 0 1 1 93IN A, Pp 0 0 0 0 1 0 p, Po 08+POUTL Pp, A 0 0 1 1 1 0 P,PoANL Pp, ltn 1 0 0 1 1 o p, Po"7"8"5"4 "3"2"'"0OR!: Pp, ltn 1 0 0 0 1 o p, Po"7"&"5"4 "3"2"'"038+p98+Pn88+PnINS A, BUS 0 0 0 0 1 0 0 0 08Q)>coEffectedcarryQ)U Function Description6«SP» ~ (PC) (PSW4- PSw,)(SP) ,- (SP) + 1(PCo·,o)~mQ)C AC 0zCalls subroutine from address m. The programcounter and the 4 high-order bits ofthe PSW are stored in the address indicatedby the stack pointer (SP). The SP is incre-. (PC,,) ~- MBF mented by 1 and m is transferred to PCo-PC lO and the MBF is transferred to PC'IThe SP is decremented by 1. The program(SP) ~- (SP)-1 counter is restored to the saved setting inthe stack indicated by the stack pointer(PC)~«SP»The PSW is not changed and interrupt disabledis maintaineJ(SP) ~ (SP) -1,(PC) (PSW4- PSW7)~« SP»(A)~ (Pp)p=1-2(Pp) ~(A)P=1-2(pp)~(Pp)1I np=1-2(Pp)~(Pp)V np=1-2(A)~(BUS)The SP is decremented by 1. The programcounter and the 4 high-order bits of thePSW are restored with the saved data in thestack indicated by the stack pointer. Theinterrupt becomes enabled after the executionis completed.Loads the contents of Pp to register A.Output latches the contents of register A toPpLogical ANDs the contents of Pp and datan. Outputs the result to PpLogical 0 Rs the contents of P p and datan. Outputs the resu It to P pEnters the contents of data bus (port 0)to register AIIOUTL BUS, A 0 0 0 0 0 0 1 0 02~0() ANL BUS, ltn 1 0 0 1 1 0 0 0 98::J"7"8"5"4 "3"2"'"0Hexadecimal.8-


MITSUBISHI MICROCOMPUTERSMELPS 8-48 MICROCOMPUTERSFUNCTION OF MELPS 8·48 MICROCOMPUTERSS~Typ decimal zEffectedIhstruction code~ carryMnemonic U FunctionHexa- co 0'"D, D6 Ds D4 D3 D2 D, Do C AC 15DescriptionEN I 0 0 0 0 0 1 0 1 05 1 1 (INTF)~ 1 Enables outside interrupt.eC0U:::J%DIS I 0 0 0 1 0 1 0 1 15 1 1 (lNTF) ~O Disables outside interrupt.SEL RBo 1 1 0 0 0 1 0 1 C5 1 1 (BS)~O Selects working register bank O.SEL RB, 1 1 0 1 0 1 0 1 05 1 1 (BS)~1 Selects work ing register bank 1.0:;:,~SEL MBo 1 1 1 0 0 1 0 1 E5 1 1 (MBF)~ a Selects memory bank O.SEL MB, 1 1 1 1 0 1 0 1 F5 1 t (MBF)~ 1 Selects memory bank 1.ENTO CLK 0 1 1 1 0 1 0 1 75 1 1Enables output of clock signal from terminalToMOV A. T 0 1 0 0 0 0 1 0 42 1 1 (A)~(T))MOV T. A 0 1 1 0 0 0 1 0 62 1 1 (T)~(A)Transfers the contents of timer/event counterto register A.Transfers the contents of register A to timer/event counter.~8~ST.RT T 0 1 0 1 0 1 0 1 55 1 1Starts timer oPeration of timer/event counterm.Minimum count cycle is BOils.Starts operation as event counter of time/event counter. Counts up when terminatedSTRT CNT 0 1 0 0 0 1 0 1 45 1 1T, changes to input high-level for input lowlevel.Minimum count cycle is 7.5Ils.8e~STOP TCNT 0 1 1 0 0 1 0 1 65 1 1Stops operation of timer or event counter.~f.=EN TeNTI 0 0 1 0 0 1 0 1 25 1 1 (TCNTF)~ 1 Enables interrupt of timer/event counterDisables interrupt of timer/event counter.DIS TCNTI 0 0 1 1 0 1 0 1 35 1 1 (TCNTF) ~ aResets interrupt flip-flop of CPU which isset during the CPU stands-by. Timer overflowflag isn't affected.~ NOP 0 0 0 0 0 0 0 0 00 1 1 No operation. Execution time is 1 cycle~Note 1: Executing an instruction may produce a carry (overflow or underflow). The carry may be disregarded (lost) or it may be transferred to C/AC (saved). The saving ofa carry is not shown in the function equations, but is instead shown in the carry columns C and ",C. The detail affection of carries for instructions ADD ADDC andDA is as follows:(C) +-1 at overflow of the accumulator is produced.(C) +-0 at no overflow of the accumulator is produced.(AC)+-1 at overflow of the bit 3 of the accumulator.(AC) +-0 at no overflow.4-18'. MITSUBISHI"ELECTRIC


MITSUBISHI MICROCOMPUTERSMELPS 8-48 MICROCOMPUTERSFUNCTION OF MELPS 8-48 MICROCOMPUTERSSymbolMeaningSymbolMeaningA8-bit register (accumlator)POProgram counterAo-A3The low-order 4 bits of the register APOO-P07The low-order 8 bits of the program counterA4- A 7Ao-An,An+,The high-order 4 bits of the register AThe bits of the register APOS-PO'OPSWThe high-order 3 bits of the program counterProgram status wordbThe value of the bits 5-7 of the first byte machine codeb7 b6 bSThe bits 5- 7 of the first byte machine codeRrRegister designatorBSBUSRegister bank selectCorresponds to the port 0 (bus I/O port)rrORegister numberThe value of bit o ,of the machine coderzr,rOThe value of bits 0-2 of the machine codeAOAuxiliary carry flag 525 ,50The value of bits 0-2 of the stack pointer0Carry flagSPStack pointerDBBData bus bufferST4-ST7Bits 4-7 of the status registerFoFlINTFISFmm7m6mSm4m3m2mlmOmlO m 9 ma(M (A»(M(Rr»(Mx(Rr»MBFSTSFlag 0TFlag 1ToInterrupt flagT1Input buffer full flagTONTFThe value of the 11 -bit addressTFThe second byte (low-order 8 bits) machine code of the11-bit addressThe bits 5-7 of the first byte (high-order 3 bits) machinecode of at he 11 -bit address':j:j:The content of the memory location addressed by the register A@The content of rhe memory location addressed by the register RrThe content of the external memory location addressffiby the register Rr--Memory bank flag +--+System statusTimer / event counterTest pin 0Test pin 1Timer / event counter overflow interrupt flagTimer flagSymbol to indicate the immediate dataSymbol to indicate the cuntent of the memory locationaddress by the registerShows direction of data flowExchanges the contents of dataIInThe value of the immediate data ( )Contents of register. memory location or flagn 7n 6n Sn 4n 3n 2n 1 n 0\OSFPPpThe immediate data of the second byte machine code 1\Output buffer full flagVVPort number -Port designator0Logical A~DInclusive ORExclusive ORNegationContent of flag is set Qr reset after executionP1POThe bits of the machine code corresponding to the port number• MITSUBISHI.... ELECTRIC4-19


MITSUBISHI MICROCOMPUTERSMELPS 8-48 MICROCOMPUTERSFUNCTION OF MELPS 8-48 MICROCOMPUTERS'Instruction Code List0000 0001 0010 0011 01000101 0110 0111 10001001 1010 1011 1100 1101 1110 1111Hexadecimala 2 3 45 6 7 89 A B C 0 E F0000 a NOPINC@ROANLXRLA, @RO0001INCXRL0010 20011 30100 40101 50110 60111 7 AA A A1000 8ANLA,ROADDA,RO1001 9ANLA,RlADDA,Rl1010 AANLA,R2ADDA,R21011 BANLA,R3ADDA, R31100 CANLA,R4ADDA,R41101 0ANLA,R5ADDA,R51110 EANLA,R6ADDA,R61111 FANLA,R7ADDA,R7•2-byte, 2-cycle instruction@J 1-byte, 2-cycle instruction4-20." MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSMSL8048-XXXP/MSL803SLPSINGLE-CHIP 8-BIT MICROCOMPUTERDESCRIPTIONThe M5L8048-XXXP and M5L8035LP are 8-bit parallelmicrocomputer fabricated on a single chip using highspeedN-channel silicon-gate ED-MaS technology.FEATURES• Single 5V power supply• Instruction cycle ................. 2.5J.ls (min)• Basic machine instructions: ................ 961-byte instructions: 682-byte instructions: 28• Direct addressing ...... .• I nternal ROM .............. .(for M5L8048-XXXP only). up to 4096 bytes1024 bytes• Internal RAM ..................... 64 bytes• Built-in timer/event counter ..... . .... 8 bits• I/O Ports .................. .27 lines• Easily expandable Memory and I/O• Subroutine nesting ............. . 8 levels• External and timer/event counter interrupt. 1 level each• Low power standby mode• External RAM ..................... 256 bytes• Interchangeable with i 8048 and i 8035L in pin configurationand electrical characteristicsAPPLICATION• Control processor or CPU for a wide variety of applicationsPIN CONFIGURATION (TOP VIEW)CLOCK INPUT 2 X2 -+ 3RESET INPUT RESET-+ 4SINGLE·STEP INPUT SS -+ 5REQ0~H~~~0t INT-+ 6EXTERNAL ACCESS EA -+ 7READ RD +- 8STOR~REPNGfB't~ PSEN +- 9WRITE WR +- 10LATCHA~~:~r~ ALE +- 11DATA BUS( 0 V) Vss--,-----.....Outline 40P4Vee (5V)39 +- T, TEST PIN 127 *Pl026 Voo (5V)I/O PORT 125 ~PROG F/~TERNALCONTROL24 * P 2 3} OUTPUT23 *P22 I/O PORT 222 "P2,21 *P20FUNCTIONThe M5L8048-XXXP and M5L8035LP are integrated 8-bitCPU, with memory (ROM, RAM) and timer/event counterinterrupt all contained on a single chip.IIBLOCK DIAGRAMosc F REO(5V) VeeROREGISTER 0Rl REGISTER IR2REGISTER 2 aR3REGISTER 3 >


MITSUBISHI MI~ROCOMPUTERSMSL8048-XXXP/MSL803SLPSINGLE.CHIP a·BIT MICROCOMPUTERPIN DESCRIPTIONPinNameVss GroundVee Main power supplyVoo Power supplyTo Test pin 0X" X2 Crystal inputsRESET ResetSS Single stepĪNT InterruptEA External access- RO Read controlPSEN Program store enable- WR Write controlALE Address latch enable0 0 -0 7 Data busP20-P2 7 Port 2PROG ProgramPl o-P1 7 Port 1T, Test pin 1Input or outputInputOutputInputInputInputInputInputOutputOutputOutputOutputInput/outputInput/outputOutputInput/outputOutputInput/outputInputNormally connected to ,ground (OV).Connected t05V power supply.Q)Connected to 5V power supply.CVUsed for memory hold when Vcc is cut.FunctionQ)Control signal from an external source for conditional jumping in a program. Jumping Is dependent onexternal condition,s (JTO/JNTO).CVUsed for outputting the internal clock signal (ENTO ClK).External crystal oscillator or RC circuit input for generating internal clock signals.An external clock signal can be input through X, or X 2•Control used to initialize the CPU.Control signal used in conjunction with ALE to stop the CPU through each instruction, in the single-stepmode.Q)Control signal from an external source for conditional jumping in a program. Jumping is dependent onexternal conditions (JNI).CVUsed for external interrupt to CPU.Q)Normally maintained at OV.CVWhen the level is raised to 5V, external memory will be accessed even when the address is less than400'6 (1024). The M5lB035lP is raised t05V.Read control signal used when the CPU requests data from external data memory or external device tobe transferred to the data bus.(MOVX A, @R r , and INS A, BUS)Strobe signal to fetch external program memory.Write control signal used when the CPU sends data through th'e data bus to external data memory or externaldevice.(MOVX @R r , A and OUTl BUS, A)A signal used for latching the address on the data bus. An ALE signal occurs once during each cycle.Q)Provides true bidirectional bus transfer of instructions and data between the CPU and external memory.Synchronizing is done with signals RD/WR. The output data is latched.CVWhen using external program memory, the output of the low-order B bits of the program counter aresynchronized with ALE. Aft,er that, the transfer of the instruction code, or data from the external program--memory is synchronized with PSEN.@The output of addresses for data using the external data memory is synchronized with ALE. After that,--the transfer of data with the external data memory is synchronized with RD/WR.(MOVX A, @R r , and MOVX @R r , A)Q)Quasi-bidirectional port. When used as an input port, FF,6 must first be output to this port. After reset,when not used as an output port, nothing needs to be output.CVP20-P2 3 output high-order 4 bits of the program counter when using external program memory.@P2o-P2 3 serve as a4-bit I/O expander bus for the M5lB243P.Strobe signal for M5lB243P I/O expander.Quasi-bidirectional port. When used as an iryput port, FF,6 must first be output to this port. After reset,when not used as an output port, nothing needs to be output.Q)Control signal from an external source for conditional jumping in a program. Jumping is dependent onexternal conditions (JT1 / J NT1 ) .CVWhen enabled, event signals are transferred to the timer/event counter (STRT CNT) .4-22• ' MITSUBISHI"ELECTRIC


~MITSUBISHI MICROCOMPUTERSMSL8048-XXXP IMSL803SLPSINGLE-CHIP a-BIT MICROCOMPUTERSWITCHI NG CHARACTERISTICS (Ta= -20-75"C. Vee =Voo=5Vt 10%. VSS=OV. unless otherwise noted)SymbolParameter<strong>Al</strong>ternativesymbolLimitsMin Typ Maxtw (ALE) ALE pulse width t LL 400 nstd (A·<strong>Al</strong>E) Delay time. address to ALE signal tAL 120 nstv (ALE-A) Address valid time after ALE tLA 80 nstw (PSEN) PSEN pulse width tcc 700 nstw (R) lID pulse width tcc 700 nstw(W) W11 pulse width tcc 700 ns-td(Q-W) Delay time. data to iNA signaltow 500 nsf--'-'---'--tV(W-Q) Data valid time after WI1 two 120 nstd(A-W) Delay time. address to WR signal tAW 230 nstd (AZ-R) Delay time. address disatile to RU signal tAFC 0 nstd (AZ-PSEN) Delay time. address disable to PSE N signal tAFC 0 nstd (PC-PROG) Delay time. port control to PROG signal tcp 110 nstv (PROG-PC) Port control valid time after PROG tpc 100 nstp(Q-PROG) Delay time. data to PROG signal top 250 nstv (PROG-Q) Data valid time after PROG tpo 65 nstw (PROGl) PROG low pulse width tpp 1200 nstd (Q-<strong>Al</strong>E) Delay time. data to ALE Signal tPL 350 nstv (<strong>Al</strong>E-Q) Data valid time after ALE t LP 150 ns_.Note 2: Conditions of measurement: control output CL =80pFdata bus output. pOrt output C l = 150p F. tc=2. 5,u s3: Reference levels for the input/output voltages are low level=O.8V and high level =2VUnitTIMING DIAGRAMRead from External Data MemoryWrite to External Data MemoryALEALERD ---------; t-.:..:..'-'-~jl._------WR --------,1th (R-O)tv (W-Q)BUSBUS----~~~--r-~~~-------Instruction Fetch from External Program MemoryPort 2ALEALEPSEN -------~----.BUStsu (A-D)th(PSEN-O)DURINGINPUTPORT CONTROL INPUT DATAtd (PCoPROG)~ I, (PRO:'PC)PROG --------------cs-.~PROGL) ~""----4-24 ' •. MITSUBISHI..... ELECTRIC


MITSUBISHI MICROCOMPUTERSMSL8049·XXXP, P.8, P·6MSL8039P.l1,P.8,P·6SINGLE-CHIP a-BIT MICROCOMPUTERDESCRIPTIONThe M5L8049-XXXP, P-8, P-6 and M5L8039P-11, P-8, P-6are 8-bit parallel microcomputers fabricated on a single chipusing high-speed N-channel silicon gate EO-MOS technology.Sp~e Internal ROM TypeExternal ROM Tv.pe11 MHz Type M5L8049-XXXP M5L8039P- 118 MHz Type M5L8049-XXXP-8 M5L8039P-86 MHz Type M5L8049-XXXP-6 M5L8039P-6FEATURES• Single 5V power supply• Basic machine instructions . . . . . . . . . . . . . . . .. 961-byte instructions: 682-byte instructions: 28• Direct addressing .............. up to 4096 bytes• Internal RAM ..................... 128 bytes• Built-in timer/event counter . . . . . . . . . . . . .. 8 bits• I/O Ports. . . . . . . . . . . . . . . . . . . . . 27 lines• Easily expandable Memory and I/O:• Subroutine nesting ................... 8 levels• External and timer/event counter interrupt . 1 level each• External RAM ....................... 256 bytes• M5L8049-XXXP/M5L8039P-ll, P-6 are interchangeablewith i 8049/i 8039, i 8039-6 in pin configuration and electricalcharacteristics.APPLICATION• Control processor or CPU for a wide variety of applicationsPIN CONFIGURATION (TOP VIEW)CLOCK INPUT 2 Xz -+ 3RESET INPUT RESET-+ 4SINGLE-STEP INPUT SS -+ 5REOl~~~f~~~E~INT-+ 6EXTERNAL ACCESS EA -+ 7READ RD +- 8STOR~R~NG:BAL~ PSEN +- 9WRITE WR ~ 10ADDRESS LATCH ALE +- 11ENABLEDATA BUS( 0 V) VSSVee (SV)39 ~ Tl TEST PIN 138 .. P2 1 }37 .. P26 I/O PORT 236 .. P25354+ P2 427 .. P1 026 Voo (SV)-, __________ ~-21~ .. P20Outline 40P4I/O PORT 125 ~PROG ~/~TERNAL24 .. P2 3} CONTROLOUTPUT23 .. P2z I/O PORT 2224+P2,FUNCTIONThe M5L8049-XXXP and M5L8039P are integrated 8-bitCPUs, with memory (ROM, RAM) and timer/event counterinterrupt all contained on a single chip.IIBLOCK DIAGRAMPl0 Ph Pl. P16 P20 P22 P2, P26Ph Ph Ph Ph~~~~=,""=.~.=T,(5V) Vee(OV) Vss~ ROREGISTEROw R1REGISTER 1~ R2REGISTER2~ :!~~g:~i~~: ~ ,R5REGISTERtJ~R6REGISTER6R7REGISTER 7To T, INTRESETPROG EA XI X2 ALE PSEN SS AD ViRRAM 128 BYTES------------------------.MITSUBISHI.... ELECTRIC4-25


MITSUBISHI MICROCOMPUTERSMSL8049-XXXP,P-8,P-6MSL8039P-ll,P-8,P-6SINGLE·CHIP a·BIT MICROCOMPUTERABSOLUTE MAXIMUM RATINGSSymbolVeeVooVIVoPdToprTst!jParameterSupply voltageSupply voltageInput voltageOutput voltagePower dissipationOperating free-air temperature rangeStorage temperature rangeWith respect to VssConditions Limits Unit-0.5-7 V-----0.5-7 V-0.5-7 V-0.5-7 VTa = 25'C 1.5 W-20-75 'C-65-150 'CRECOMMENDED OPERATING CONDITIONS (Ta =-20-75"C,unlessotherwisenoted)LimitsSymbol Parameter UnitMin Nom Maxf-Vee Supply voltage 4.5 5 5.5 VVoo Supply voltage 4.5 5 5.5 VVss Supply voltage 0 VVIHl High·level input voltage, except for XI, X" RESET 2 Vee VVIH2 High-level input voltage, XI. X2 , J'iE-sEI 3.8 Vee VVIL Low-level input voltage -0.5 0.8 VIIELECTRICAL CHARACTERISTICS (Ta=-20-75·C, Vee=Voo=5V± 10%, VSS'=OV, unlessolherwise noted)Symbol Parameter Test conditionsMinVOL Low-level output voltage, BUS, RD, WR, PSEN, ALE IOL=2rnAVOLl Low-level output voltage, except for the above and PROG IOL= 1.6rnAVOL2 Low-level output voltage PROG IOL= lrnAVOH High-level output voltage, BUS, RD, WR, PSEN, ALE IOH= -100"A 2.4VOHl High-level output voltage, except for the above IOH= -50,IIA 2.4I I L Input leak current, Tl, INT VSS~VIN~Vee -10IOL Output leak current, BUS, TO, high-impedance state Vss+ 0.45~VIN~Vee -10I Lll Input current during low-level input, port VIL =0.8VILl2 Input current during low-level input, REET,"SS VIL =0.8V100 Supply current from Voo Ta = 25 'Cloo+lee Supply current from Voo and Vee Ta=25"CLimitsTyp Max0.450.450.451010-0.2-0.0525 50100 170';UnitVVVVV/1A/1 ArnArnArnArnATIMING REQUI REMENTS (T a =-20-75·C,Vee=Voo=5V ± 10%. Vss=OV. unless otherwise noted)LimitsSymbolParameter<strong>Al</strong>ternative M5LB049-XXXPsymbol M5 LB039P-ll (Note 2M5LB049-XXXP-8M5LB039P-BM5LB049-XXXP-6M5LB039P-6UnitMinTypMaxMin Typ MaxMin Typ MaxtoCycle timeteY 1.3615.01.875 15.02.5 15.0f-lSth (PSEN-D)Data hold time after PSENt DR 01000 1500 200nsth (R-D)tsu (PSEN-D)Data hold time after RDData setup time after PSENtDR 0t RD1002500 1503500 200500nsnstsu (R-Dtsu (A-D)Data setup time after RDData setup time after addresst RDtAD250400350650500950nsnstsu (PROG-D)Data setup time after PROGtpR650700810nsth (PROG-D)Data hold time before PROGtpF 01500 1500, 150nsNote 12The input voltage are V 1L =0. 45V and VIH=2. 4V.T a =0-70·C. • MITSUBISHI"'ELECTRIC4-27


· MITSUBISHI MICROCOMPUTERSMSL8049~XXXP,P';'8,P-6·MSL8039P-ll,P-8,P-6SINGLE·CHIP a·BIT MICROCOMPUTERSWITCHING CHARACTERISTICS (Ta=-20~75·C. Vee = VDD = 5V±10%, Vss = OV, unless otherwise noted)LimitsAI ternative M5LS049-XXXP M5LS049-XXXP-S M5LS049-XXXP-6Symbol Parameter symbol M5LS039-11 (Note 2) M5LS039P-S M5LS039P-6Min Typ Max Min Typ Max Min Typ MaxtW(ALE) ALE pulse width t LL 150 300 400td (A-ALE) Delay time, address to ALE signal tAL 70 120 150tv (ALE-A) Address valid time after ALE t LA 50 70 80tW(PSEN) PSEN pulse width tcc 300 500 700tW(R) RD pulse width tcc 300 500 700td (W) WR pulse width tcc 300 500 700tv (Q-W) Delay time, data to WR signal tow 250 380 500td (W-Q) Data valid time after WR two 40 80 120td (A-W) Delay time, address to WR signal tAW 200 220 230td (AZ-R) Delay time, address disable to RD signal tAFC -10 -5 0td (AZ-PSEN) Delay time, address disable to PSEN signal tAFC -10 -5. 0td (PC-PROG) Delay time, port control to PROG signal tcp 100 105 110tv (PROG-PC) Port control valid time after PROG tpc 60 100 130tp (Q-PROG) Delay time, data to PROG signal top 200 210 220tv (PROG-Q) Data valid time after PROG tpo 20 45 65tW(PROGL) PROG low pulse width tpp 700 1150 1510td (Q-ALE) Delay time, data to ALE signal tpL 150 300 400tv (ALE-Q) Data valid time after ALE t LP 20 100 150UnitnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsNoteConditions of measurement: control output C L =SOpFdata bus output, port output CL =l50pF4 Reference levels for the input/output voltages are low level=O.SV and high level=2V.TIMING DIAGRAMRead from External Data MemoryWrite to External Data MemoryALEALEtW(R)RD-------------;I~~~~----------th (R-O)WR ----------------'1tv (W-Q)BUSDATAInstruCtion Fetch from External Program MemoryPort 2ALEP2g~~~d-'~--~~----~-----J~ ____ ~ __ -n~~~ __ __INPUTtsu (A-D)PROG------------------~~~~~~~~-----4-28•. . MITSUBISHI..... ELECTRIC


MITSUBISHI MICROCOMPUTERSMSL8049H-XXXP/MSL8039HLPSINGLE-CHIP a-BIT MICROCOMPUTERDESCRIPTIONThe M5L8049H-XXXP and M5L8039HLP are 8-bit parallelmicrocomputers fabricated on a sinQle chip using N­channel silicon gate ED-MO~ technology.FEATURES• Single 5V power supply• Low power dissipation···························· 275mW (typ.)• Instruction cycle .. ·.. ································1.36,us (min.)• Basic machine instructions···· '96( 1-byte instructions: 68)• 4K-bytes memory addressing possible(direct addressing possible in 2K-bytes memory)• Memory capacity ROM···························:····· 2K-bytesRAM································· ·128 bytes• Built-in timer/event counter ................................ 8 bits• I/O ports .........................................··············27 lines• Easily expandable memory and I/O• Subroutine nesting······································ .. · 8 levels• External and timer/event counter interrupt, 1 level each• Low power standby mode• M5L8049H-XXXP/M5L8039HLP are interchangeable withi 8049H/i 8039HL in pin configuration and electrical characteristics.APPLICATIONControl processor or CPU for a wide variety of applicationsPIN CONFIGURATION (TOP VIEW)TEST PIN 0 To" 1CLOCK INPUT 1 Xl --+ 2CLOCK INPUT 2 X 2 --+ 3RESET INPUT RESET --+ 4SINGLE-STEP INPUT SS --+ 5INTFf:~~:JT INPUTINT--+ 6EXTERNAL ACCESS EA --+ 7READ RD ...... 8PROGRAM --STORE ENABLE PSEN...... 9WRITE WR ...... 10ADDRES~~~1t~ ALE ...... 11Do" 12Outline40P4Vee (5V)I/OPORT 1IIFUNCTIONThe M5L8049H-XXXP and M5L8039HLP are integrated 8-bitCPUs, with memory (ROM (Except M5L8039HLP) , RAM)and timer/event counter interrupt all contained on a singlechip.BLOCK DIAGRAMr-,.L-L-L-L-L..L..LJ.,~~~IIIIF( 5V) V.DD FOR POWER RAM SUPPLY~(5V) Vee 0(OV) Vss 20ToTl~TF~~rTIMrR FLAGCARRYACCACC BIT TESTRAM (128 BYTES)L..---Q.)--Q!!~~~>-Q.;f-{2)--{3)>-®--{9jI--{5:k8}-(1c~ ---- ---- ---- ---- ---- -To INT PROG Xl ALE SS WRTl RESET EA X 2 PSEN RDT'IIIIIIIJ• . MITSUBISHI.... ELECTRIC4-29


MITSUBISHI MICROCOMPUTERSMSL8049H-XXXP/MSL8039HLPSINGLE-CHIP a-BIT MICROCOMPUTERPIN DESCRIPTIONPinNameVss GroundVee Main power supplyVoo Power supplyToTest pinOX1• X 2 Crystal inputsRESET Reset- SS Single stepĪNT InterruptEA External access- RO Read controlPSEN Program store enable- WR Write controlALE Address latch enable0 0 -0 7 Data busP20-P2 7 Port 2PROG ProgramPl o-P1 7 Port 1T1 Test pin 1Input or outputInputOutputInputInputInputInputInputOutputOutputOutputOutputInput/outputInput/outputOutputInput/outputOutputInput/outputInputNormally connected to ground (OV).Connected to 5V power supply.Q)Connected t05V power supply.~Used for memory hold when Vee Is cut.FunctionQ)Control signal from an external source for conditional jumping in a program. Jumping is dependent onexternal conditions (JTOI J NTO).~Used for outputting the Internal clock signal (ENTO ClK).External crystal oscillator or RC circuit Input for generating internal clock signals.An external clock signal can be input through X1 or X2.Control used to Initialize the CPU.Control signal used in conjunction with ALE to stop the CPU through each instruction. in the single-stepmode.Q)Control signal from an external source for conditional jumping in a program. Jumping is dependent onexternal conditions (JNI).~Used for external interrupt to CPU.Q)Normally maintained atOV.~When the level is raised to 5V. external memory will be accessed even when the address is less than40016 (2048). The M5L8039HlP is raised t05V.Read control signal used when the CPU requests data from external data memory or external device tobe transferred to the data bus.(MOVX A. @Rr• and INS A. BUS)Strobe signal to fetch external program memory.Write control signal used when the CPU sends data through the data bus to exte~nal data memory or externaldevice.(MOVX @R r • A and OUTl BUS. A)A signal used for latching the address on the data bus. An ALE signal occurs once during each cycle.Q)Provides true bidirectional bus transfer of instructions and data between the CPU and external memory.Synchronizing is done with Signals RD/WR. The. output data is latched.~When using external program memory. the output of the low-order 8 bits of the program counter aresynchronized with ALE. After that. the transfer of the instruction code or data from the external programmemory is synchronized with PSEN.@The output of addresses for data using the external data memory Is synchronized with ALE. After that.the transf,er of data with the external data memory is synchronized with RD/WR.(MOVX A. @R r • and MOVX @R r • A)~Q)Quasi-bidirectional port When used as an input port. FF16 must first be output to this port. After reset.when not used as an output port. nothing needs to be output.~P20-P23 output high-order 4 bits of the program counter when using external program memory.@P2 0-P23 serve as a4-bit 1/0 expander bus for the M5l8243P.Strobe signal for M5l8243P 1/0 expander.Quasi-bidirectional port. When used as an input port. FF16 must first be output to this port. After reset.when not used as an output port. nothing needs to be output.Q)Control signal from an external source for conditional jumping in a program. Jumping is dependent onexternal conditions (JT1/JNT1).~When enabled. event signals are transferred to the tlmerlevent counter (STRT CNT) .4-30• '. MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSMSL8049H-XXXP/MSL8039HLPSINGLE-CHIP a-BIT MICROCOMPUTERABSOLUTE MAXIMUM RATINGSSymbol Parameter Conditions Limits UnitVee Supply voltage -0.5-7 VVoo Supply voltage -0.5-7 VWith respect to VssVI Input voltage-0.5-7 VVo Output voltage -0.5-7 VPd Power dissipation Ta= 25"


. MITSUBISHI MICROCOMPUTERSMSL8049H-XXXP IMSL8039H LPSINGLE-CHIP 8-BIT MICROCOMPUTERTIMING REQUIREMENTS (Ta =O-70'C, Vcc=Voo=5V±10%. Vss=ov, unless otherwise noted)SymbolParameterRelationship to <strong>Al</strong>tematlve Limitscycle time (tc) symbol Min Typte Cycle time. 11 (f>


MITSUBISHI MICROCOMPUTERSMSL8049H-XXXP/MSL8039HLPSINGLE-CHIP 8-BIT MICROCOMPUTERTIMING DIAGRAMExternal Data Memory ReadALEExternal·Oata Memory WriteALERD --------------ilBUS----~~DmDR~E~~~--t---~:IDDA[~[)~----------External Program Memory Instruction Fetch Port 2ALEALE11E---"'*"o-------tI4--~ td (PSEN-ALE) P2 0-P2 3PSEN ---------+li-------IIIDURINGOUTPUTtd (PROG-ALE)IItsu (PSEN-O)P20-P23DURINGINPUTPROG --------------------~• MITSUBISHI.... ELECTRIC4-33


MITSUBISHI MICROCOMPUTERSMSM80S0H-XXXP/MSM8040HPSINGLE-CHIP a-BIT MICROCOMPUTERDESCRIPTIONThe M5M8050H-XXXP/M5M8040HP is an 8-bit parallel microcomputerfabricated on a single chip using N-channel silicongate EO-MOS technology.M5M8050H-XXXPM5M8040HPInternal ROM Type (4K Bytes)External ROM TypeFEATURES• Single 5V power supply• Instruction cycle .. . . . . . . . . . . . . . . . .. 1. 36,us (min)• Basic machine instructions .. 96 (1-byte instructions: 68)• 4K-bytes memory addressing possible(direct addressing possible in 2K bytes memory)• Memory capacity: ROM. . . . . . . . . . . . . .. 4K bytesRAM. . . . . . . . . . . . . .. 256 bytes• Built-in timer/event counter ................. 8 bits• I/O ports .............................. 27 lines• Easily expandable Memory and I/O• Subroutine nesting ...................... 81evels• External and timer/event counter interrupt, 1 level each• Low power standby modeAPPLICATIONControl processor or CPU for a wide variety of applicationsPIN CONFIGURATION (TOP VIEW)CLOCK INPUT 2 Xz -+ 3RESET INPUTAESET-+ 4SINGLE·STEP INPUT SS-+ 5REQJ~~-i~~~~i INT -+ 6EXTERNA'L ACCESS EA -+ 7READ AD +- 8STOR~R?NGfB1~ PSEN+- 9WRITE WA +- 10ADDRESSE~~1I.~ ALE +- 11DATtI BUS( 0 V) VssVee (SV)39 ... TI TEST PIN 138 .. P2 7 }3 7 .. P2 61/0 PORT 236 .. P2535 .. P2 4Zs" P1 1ZJ.. Plo'--____ --Jr Ẕ -' .. P 2 0Outline 40P41/0 PORT 1Z6 VDD (SV)Z5 ~PAOG ~/;TERNALZ4.. P2 3} CONTROLOUTPUTZ3 .. P2z 1/0 PORT 22l "P21FUNCTIONThe M5M8050H-XXXP/M5M8040HP is. an 8-bit CPU, withmemory (ROM, RAM) and timer/event counter interrupt allcontained a single chip.,,--BLOCKDIAGRAMRO REGISTER 0RI. REGISTER IR2 REGISTER 2 0R3 REGISTER 3 :.


MITSUBISHI MICROCOMPUTERSMSM80S0H-XXXP/MSM8040HPSINGLE-CHIP a-BIT MICROCOMPUTERPIN DESCRIPTION'V ssVeeVooPin Name Input or outputGroundMain power supplyPower supplyTo Test pin 0InputOutputXl, X 2 Crystal inputs InputRESET Reset Input- SS Single step InputĪNT I f!terrupt InputEA External access Input- RO Read control OutputPSEN Program store enable Output- WR Write control OutputALE Address latch enable Output0 0-07 Data bus Input/outputP20-P27 Port 2Input/outputOutputInput/outputPROG Program OutputPl o -P1 7 Port 1 Input/outputTl Test pin 1 InputNormally connected to ground (OV).Connected t05V power supply.(DConnected t05V power supply.®Used for memory hold when Vcc is cut.Function(DControl signal from an external source for conditional jumping in a program. Jumping is dependent onexternal conditions (JTOfJNTO).®Used for outputting the internal clock signal (ENTO ClK).External crystal .oscillator or RC circuit input for generating internal clock signals.An external clock signal can be input through Xl or X2•Control used to initialize the CPU.Control signal used in conjunction with ALE to stop the CPU through each instruction, in the single-stepmode.(DControl signal from an external source for conditional jumping in a program. Jumping is dependent onexternal conditions (JNI).®Used for external interrupt to CPU.(DNormally maintained atOV.®When the level is raised t05V, external memory will be accessed. The M5M8040HP is raised t05V.Read control signal used when the CPU requests data from external data memory or external device tobe transferred to the data bus.(MOVX A, @R r , and INS A, BUS)Strobe signal to fetch external program memory.Write control signal used when the CPU sends data through the data bus to external data memory or externaldevice.(MOVX @Rr, A and OUTl BUS, A)A signal used for latching the address on the data bus. An ALE signal occurs once during each cycle.(DProvides true bidirectional bus transfer of instructions and data between the CPU and exterQal mem---ory. Synchronizing is done with signals RO/WR. The output data is latched.®When using external program memory, the output of the low-order 8 bits of the program counter aresynchronized with ALE. After that, the transfer of the instruction code or data from the external program--memory is synchronized with PSEN.@The output of addresses for data using the external data memory is synchronized with ALE. After that,--the transfer of data with the external data memory is synchronized with RO/WR.(MOVX A, @R r , and MOVX @R r , A)(DQuasi-bidirectional port. When used as an input port, FF 16 must first be output to this port. After reset,when not used as an output port, nothing needs to be output.®P2o-P2 3 output high-order 4 bits of the program counter when using external program memory.@P2 0 -P2 3 serve as a 4-bit I/O expander bus for the M5l8243P.Strobe signal for M5l8243P I/O expander.Quasi-bidirectional port. When used as an input port, FF 16 must first be output to this port. After reset,when not used as an output port, nothing needs to be output.(DControl signal from an external source for conditional jumping in a program. Jumping is dependent onexternal conditions (JT1/JNT1).®When enabled, event signals are transferred to the timer/event counter (STRT CNT).II.• MITSUBISHI.... ELECTRIC4-35


MITSUBISHI MICROCOMPUTERSMSM80S0H-XXXPlMSM8040HPSINGLE-CHIP a-BIT MICROCOMPUTERABSOLUTE MAXIMUM RATINGSSymbol Parameter Conditions LimitsVee Supply voltage -0.5-7Voo Supply voltage -0.5-7With respect to V 5SVI I nput voltage-0.5-7Vo Outp' ,t voltage -0.5-7Pd Power dissipation Ta=25"C 1.5Topr Operating free-air temperature range 0-70Tstg Storage temperature range -65 - .150UnitVVVVW"C"CR ECOMMENDE DOPE RA TI NG CON D ITI ONS (T a = 0 -70"C, unless otherwise noted)LimitsSymbol Parameter UnitMin Nom MaxVee Supply voltage 4.5 5 5.5 VVOO Supply voltage 4.5 5 5.5 VV SS Supply voltage 0 VVIH1 High-level input voltage, except Xl. X 2 and R E 5 E T 2 Vee VV I H2 High-level input voltage, Xl. X 2 and R E 5 E T 3_ 8 Vee VVIL1 Low-level input voltag~, except Xl. X 2 and R E 5 E f -0.5 0.8 VV I L2 Low-level input voltage, Xl. X 2 and R E 5 E T -0_5 0.6 VELECTRICAL CHARACTERISTICS (Ta=0-70"C. Vee =Voo =5V ± 10%. Vss = OV, unless otherwise noted)SymbolParameterTest conditionsMinLimitsTypMaxUnitVOL Low-level output voltage (BU 5)IOL=2mA0.45 VVOL1Low-level output voltage CRO. WR. P5EN. ALE)I OL =1.8mA0.45 VVOL2Low-level output voltage (PROG)I OL =1 mA0.45 VVOULow-level output voltage (for other outputs)I OL =1.6mA0.45 VVOH High-level output voltage (BU 5)I OH = -400j.lA2.4VVOH1High-level output voltage (RD. WR. P5EN. ALE)I OH= -100j.lA2.4VVOH2High-level output voltage (for other outputs)I OH= -40j.lA2.4VIIInput leak current (T 1. INT)VSS ~VIN~Vee-1010 j.l<strong>Al</strong>ozOutput leak current (BU 5. To ) high, impedance stateVSS +0.45~VIN ~VCC-1010 I-'A111 Input leak current (PORT)Vss +0.45~ VI N ~VCC- 0.2-0.5 mAI 12 Input leak current (RE5E T. 55)Vss +0.45~VIN ~VCC-0.05mA100 Supply current from Voo1020 mAI DO +1 CCSupply current from Voo and Vee70140 rnA4-36• MITSUBISHI"ELECTRIC


MITSUBISHI MICROCOMPUTERSMSM80S0H-XXXP IMSM8040HPSINGLE-CHIP a-BIT MICROCOMPUTERTIMING REQUIREMENTS (Ta=0-70"C, Vcc=Voo=5V± 10%, VSS =0 V, unless otherwise noted)UnitSymbolParameterRelationship to <strong>Al</strong>ternativeLimitscycle time (to) symbol Min Typ MaxtW(To) TO pulse period 3/15·tet OPRR 270 nste Cycle time l/(fxTAL -;-.15) tCY 1. 36 15 liSt h(PSEN-O) Data hold time after P SEN 1/10·te -30 tOR 0 110 nsth(R-O) Data hold time after R D 1/10,te-30 tOR 0 110 nstSU(PSEN-O) Data setup time after P SEN 3/10·te-200 tR02 210 nstSU(R-O) Data setup time after R D 2/5·te-200 tROI 350 nstsul (A-O)Data setup time after address(external data memory read cycle)7/10-te-22OtAOInstSU2(A-O)Data setup time after address(external program memory read cycle) 1/2·te-2OO tA02 460 nstsu (PROG-O) Data setup time after PROG 6/10·te-120 tpR 700 nsth (PROG-O) Data hold time after PROG 1/10-te tpF 0 140 nsNote 1: The input voltages are V IL = 0,45 V and V I H = 2 , 4 V.2: f ~TAL is the oscillator frequency entered at the crystal input terminals (X I , X 2 ).SymbolParameterRelationship to <strong>Al</strong>ternativeLimitscycle time (te) symbol Min Typ MaxUnittW(ALE) ALE pulse width 7/30-te-170 t LL 150nstd (A-ALE) Delay time, address to ALE signal 2/15- te-110 tAL 70nstv (ALE-A) Address valid time after ALE 1/ 15·te -40t LA 50nstW(PSEN) P SEN pulse width 2/5·te-200tCC2 350nstW(R) RD pulse width 1/2·te-200 tCCI 480nstw(W) WR pulse width 1/2·te-200 tCCI 480nstd (Q-W) Delay time, data to W R signal 13/30' te - 200 tow 390nstv (W-Q) Data valid time after WR 1/15·te-50 two 40nstd (A-W) Delay time, address to W R signal 1/3-tc-15O tAW 300nstd (AZ-R) Delay time, address disable to R D signal 2/ 15-te -40t AFCI 140nstd (AZ-W) Delay time, address disable to WR signal 2/15-te-40t AFCI .,40nstd (AZ-PSEN) Delay time, address disable to P SEN signal 1/30·te-40t AFC2 10nstd (ALE-R) Delay time, ALE to RD signal 1/5·te-75t LAFCI 200nstd (ALE-W) Delay time, ALE to W R signal 1/5·te-75t LAFCI 200nstd (ALE-PSEN) Delay time, ALE to PSEN signal 1/10·te-75t LAFC2 60nstd (R-ALE) Delay time, RD to ALE signal 1/15·te -40 tCAI 50nstd (W-ALE) Delay time, WR to ALE signal 1/15·te-40 tCAI 50nstd (PROG-ALE). Delay time, PROG to ALE signal 1/15·te-40 tCAI 50nstd (PSEN-ALE) Delay time, PSEN to ALE signal 4/15-tc-40tCA2 320nstd (PC-PROG) Delay time, Port control to PROG signal 2/15- t c-;-80 tcp 100nstv (PROG-PC) Port control valid time after PROG 4/15·te-200 t pc 160nstd (Q-PROG) Delay time, Data to PROG signal 2/5·te-150 top 400nstv (PROG-Q) Data valid time after PROG 1/10·te-50t po 90nstW(PROGL) PROG low pulse width 7/10·te-250 tpp 700nstd (Q-ALE) Delay time, Daia to ALE signal 4/15·te-200 t pL 160nstv (ALE-Q) Data valid time after ALE 1/10·te-l00 t LP 40nstd (ALE-Q) Delay time, A LE to data 3/10·te + 100 t pv 510 nsSWITCHING CHARACTERISTICS (Ta=0-70"C, V cc =V 00 =5V ± 10%. V SS =OV, unlessotlierwise noted)aNote 3: Conditions of measurement: control output CL =8OpF data bus output, port output C L=150pF.4: Reference levels for input/output voltages are low-level=0.8V and high-level=2V.• MITSUBISHI.... ELECTRIC4-37


MITSUBISHI MICROCOMPUTERSMSM80S0H-XXXP/MSM8040HPSINGLE-CHIP a-BIT MICROCOMPUTERTIMING DIAGRAMRead from External Data MemoryWrite to External Data Memorytd (ALE-W)ALEALEWR --------------~Itd(AZ-R) tSU(R-D)ADDRESS ~-1BUS _____ ~~====~--~--~£D~AT~A~~---------BUS ----~~===:~--~~@b~~~----------tSU1(A-D)Instruction Fetch from External Program Memory Port 2td(PROG-ALE)ALEPSEN ---------#----~BUStSU 2(A-D)4-38 • MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSMSM80S0L-XXXP/MSM8040LPSINGLE-CHIP I-BIT MICROCOMPUTERDESCRIPTIONThe M5M8050L-XXXP and M5M8040LP are 8-bit parallelmicrocomputers fabricated on a single chip using N­channel silicon gate ED-MOS technology.FEATURES• Single 5V power supply• Low power dissipation ····························300mW (typ.)• Instruction cycle·······································2.5,us (min.)• Basic machine instructions ·····96(1-byte instructions: 68)• 4K-bytes memory addressing possible(direct addressing possible in 2K bytes memory)• Memory capacity: ROM ................................ 4K bytesRAM····················· ············256 bytes• Built-in timer/event counter··· ................ ·············8 bits• I/O ports······················································· 27 lines• Easily expandable memory and I/O• Subroutine nesting········································· 8 levels• External and timer/event counter interrupt, 1 level each• Low power standby modeAPPLICATIONControl processor or CPU for a wide variety of applicationsFUNCTIONThe M5M8050L-XXXP and M5M8040LP are integrated 8 bitCPUs, with memory (ROM (except M5M8040LP), RAM)and timer/event counter interrupt all contained on a singlechip.PIN CONFIGURATION (TOP VIEW)TEST PIN 0CLOCK INPUT 1CLOCK INPUT 2 x 2 -+ 3RESET INPUT RESET -+ 4SINGLE-STEP INPUT SS -+ 5INTE~~g~~ST INPUT INT -+ 6EXTERNAL ACCESS EA -+ 7READPROGRAMSTORE ENABLEWRITEADDRESSLATCH ENABLEDATA BUSVee (5V)TEST PIN 127 - P1 026 Voo (5V)~ _____.F2...1 - P2 0Outline40P41/0 PORT 125 -+ PROG r}gERNA24 - P23j CONTROL23 _ P2 OUTPUT222 _ P2 1/0 PORT 21IIBLOCK DIAGRAMDo 02I--~~~~~~~-----------,,III(5V) Voo 26(5V) VeeT, IIIIIIIITlRD•. MITSUBISHI.... ELECTRIC4-39


MITSUBISHI MICROCOMPUTERS. MSM80S0L-XXXP/MSM8040LPSINGLE-CHIP a-BIT MICROCOMPUTERPIN DESCRIPTIONPinNameVssGround ...Vee Main power supplyVoo Power supplyToTest pinOX 1 • X 2 Crystal InputsRESET Reset- SS Single stepĪNT InterruptEAExternal access- RO Read controlPSEN Program store enable- WR Write controlALE Address latch enable0 0 -0 7 Data busP20-P27 Port 2PROG ProgramPl o-P1 7 Port 1Tl Test pin 1Input or outputInputOutputInputInputInputInputInputOutputOutputOutputOutputInput/outputInput/outputOutputInput/outputOutputInput/outputInputNormally connected to ground (OV).Connected to 5V power supply.(DConnected to 5V power supply.~Used for memory hold when Vee is cut.Function(i)Control signal from an external source for conditional jumping In a program. Jumping Is dependent onexternal conditions (JTO/JNTO).~Used for ciutputtlng the internal clock signal (ENTO ClK).External crystal OSCillator or RC circuit input for generating intemal clock signals.An external clock signal can be Input through Xl or X2.Control used to Initialize the CPU.Control signal used in conjunction with ALE to stop the CPU through each instruction; in the single-stepmode.(DControl signal from an external source for conditional jumping In a program. Jumping Is dependent onexternal conditions (JNI).~Used for external interrupt to CPU.(DNormally maintained at OV.~When the level is raised to 5V. external program memory will be accessed:Read control signal used when the CPU requests data from external data memory or external device tobe transferred to the data bus.(MOVX A. @Rr• and INS A. BUS)Strobe Signal to fetch external program memory.Write control signal used when the CPU sends data through the data bus to external data memory or externaldevice.(MOVX @R r • A and OUTl BUS. A)A signal used for latching the address on the data bus. An ALE signal occurs once during each cycle.(DProvides true bidirectional bus transfer of Instructions and data between the CPU and external memory.Synchronizing is done with signals RD/WR. The output data is latched.~When using external program memory. the output of the low-order B bits of the program counter aresynchronized with ALE. After that. the transfer of the instruction code or data from the external program--memory Is synchronized with PSEN.@The output of addresses for data using the external data memory is synchronized with ALE. After that.--the transfer of data with the external data memory is synchronized with RD/WR.(MOVX A, @Rr, and MOVX @Rr• A)(DQuasl-bidlrectional port. When used a~ an input port. FF 16 must first be output to this port. After reset.when not used as an output port, nothing needs to be output.~P2o-P23 output high-order 4 bits of the program counter when using external program memory.@P2 0 -P23 serve as a 4-bit I/O expander bus for the M5lB243P.Strobe signal for M5lB243P I/O expander.Quasi-bidirectional port. When used as an input port. FF 16 must first be outputto this port. After reset,when not used as an output port. nothing needs to be output.(DControl signal from an ex,ernal source for conditional jumping In a program. Jumping is dependent onexternal conditions (JT1/JNT1).~When enabled. event signals are transferred to the timer/event counter (STRT CNT).4-40.• MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSMSM80S0L-XXXP/MSM8040LPSINGLE-CHIP a-BIT MicROCOMPUTERABSOLUTE MAXIMUM RATINGSSymbol Parameter Conditions Limits UnitVee Supply voltage -0.5-7 VVoo Supply voltage -0.5-7 VWith respect to VssVI Input voltage-0.5-7 VVo, Output voltage -0.5-7 VPd Power dissipation Ta = 25'C 1.5 WTopr Operating free-air temperature range 0-70 ·CTstg Storage temperature range -65-150 ·CRECOMMENDED OPERATING CONDITIONS (Ta = 0-70·C, unless otherwise noted)LimitsSymbol ParameterMin Nom MaxUnitVee Supply voltage 4.5 5 5.5 VV DD Supply voltage 4.5 5 5.5 VVss Supply voltage 0 VV IH1 High-level input voltage, except Xl, X2 and RESET 2 Vee VV IH2 High-level input voltage, Xl, X2and RESET 3.8 Vee VV ILl Low-level input voltage, except Xl, X2 and RESET -0.5 0.8 VV IL2 Low-level input voltage, Xl, X2 and RESET --0.5 0.6 VIIELECTRICAL CHARACTERISTICS (Ta = 0-70·C, Vcc = Voo = 5V±10%, Vss = ov, unless otherwise noted)SymbolVOLV OLlV OL2V OL3V OHV OH1V OH2IIloz111112100100 + IccParameterLow-level output voltage (BUS)Low-level output voltage' (RD, WR, PSEN, ALE)Low-level output voltage (PROG)Low-level output voltage (for other outputs)High-level output voltage (BUS)High-level output voltage (RD, WR, PSEN, ALE)High-level output voltage (for other outputs)Input leak current (Tl, INT)Output leak current (BUS, To), high-impedance stateInput leak current (Port)Input leak current (RESET, SS)Supply current from VooSupply current from Voo and VeeTest conditionsIOL = 2mAIOL = 1.8mAIOL = ImAIOL = 1.6mAIOH = -400t'AIOH = -100t'AIOH = -40t'AVss :;;; VIN :;;; VceVss + O. 45:;;; VIN :;;; VeeVss + O. 45:;;; VIN ;;;;; VeeVss + 0.45:;;; VIN :;;; VccLimitsMin Typ Max0.450.450.450.452.42.42.4-19 10-10 10-0.2 -0.5-0.055 1090UnitVVVVVV,VJ.lAJ.lAmAmAmAmA• MITSUBISHI"ELECTRIC4-41


MITSUBISHI MICROCOMPUTERSMSM80S0L.XXXP/MSM8040LPSINGLE-CHIP I-BIT MICROCOMPUTERTIMING REQUIREMENTS (Ta = 0:....70·C. Vee = Voo = 5V±10%, Vss = ov. unless otherwise noted)SymbolParameterRelationship to <strong>Al</strong>ternative Limitseycle time (t c ) symbol Min Typtc Cycle time 11 (fxTAL -+- 15) tCY 2.5th (PSEN-O) Data hold time after PSEN 1/10· tc - 30 tOR 0th (R-O) Data hold time after RD 1/10· tc - 30 tOR 0tsu (PSEN-O) Data setup time after PSEN 3/10· tc - 200 tR02tsu (R-O) Data setl,lp t!m,e after RD 2/5' tc - 200 tR01tSUl (A-D)Data setup time after address(external data memory read cycle)7/10· tc - 220 tAOltSU2 (A-D)Data setup time after address(external program memory read cycle)1/2·tc -200tsu (PROG-O) Data setup time after PROG 6/10· tc - 120 tpRth (PROG-O) Data hold time after PROG 1/10· tc tpF 0NoteThe input voltage level is V1L = O. 45V and V1H = 2.4V.fXTAL is the oscillator frequency entered at the crystal input terminals (Xl. X 2 ).tA02UnitMax15 J,lS220 ns220 ns550 ns800 ns1530 ns1050 ns1380 ns250 nsSWITCHING CHARACTERISTICS (Ta = 0-7ot. Vee = Voo = 5V±10%, Vss = ov. unless otherwise noted)SymbolParameterRelationship tocycle time (tel<strong>Al</strong>ternativetw (ALE) ALE pulse width 7/3Q • tc - 170 tLLtd (A-ALE) Address to ALE signal delay time 2115 • tc - 110 tALtv (ALE-A) Address vaUd time after ALE 1/15· tc - 40 tLAsymboltw (PSEN) PSEN pulse width 2/5, tc - 200 tcc2tw (R) RD pulse width 1/2·tc -200 tCCltw(W) WR pulse width 1/2·tc -200 tCCltd (O-W) Data to WR signal delay time 13/30, tc - 200 towtv (w-o) Data vaUd time after WR 1/15· tc - 50 twotd (A-W) Address to WR, signal delay time 1/3·tc -150 tAWtd (AZ-R) Address disable to RD signal delay time 2/15· tc - 40 tAFCltd (AZ-W) Address disable to WR signal delay time 2/15· tc - 40 tAFCltd (AZ-PSEN) Address disable to PSEN signal delay time 1/30· tc ~·40 tAFC2td (ALE-R) ALE to RD signal delay time 1/5·tc -75 tLAFCltd (ALE-W) ALE to WR signal delay time 1/5' tc -75 t LAFCltd (ALE-PSEN) ALE to PSEN Signal delay time 1/10·tc -75 tLAFC2td (R-ALE) RD to ALE signal delay time 1/15·tc -40 tC<strong>Al</strong>td (W-ALE) WR to ALE signal delay time 1/15· tc - 40 tC<strong>Al</strong>td (PROG-ALE) PROG to ALE Signal delay time 1/15·tc -40 tC<strong>Al</strong>td (PSEN-ALE) PSEN to ALE signal delay time 4/15· tc - 40 tCA2td (PC-PROG) Port control to PROG signal delay time 2/15· tc - 80 tcptv (PROG-PC) Port control valid time after PROG 4/15· tc - 200 tpctd (O-PROG) Data to PROG signal delay time 2/5· tc -150 toptv (PROG-O) Data vaUd time after PROG 1/10·tc -50 tpotw (PROGLl PROG low-level pulse width 7/10· tc - 250 tpptd (a-ALE) Data to ALE signal delay time 4/15· tc - 200 tpLtv (ALE-a) Data valid time after ALE 1/10· tc -100 t LPtd (ALE-a) Delay time after ALE 3/10· tc + 100 tpvtw ("0) To pulse spacing 3/15· tc toPRRNote 34Conditions of measurement: control output CL = 80pF data bus output. port output CL = 150pF.Reference levels for input/output voltages are low-level = 0.8V high-level = 2V .Min41022012080010501050880120680290290404204201701201201206202504608502001500460150500LimitsTypUnitMaxnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns850 nsns4-42 . •.. MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSMSM80S0L-XXXP/MSM8040LPSINGLE-CHIP I-BIT MICROCOMPUTERTIMING DIAGRAMExternal Data MemorY Re~(I"ALEExternal Data Memory WriteALERDWR -------""'""'1BUS----~~~-t~~~~-------External Program Memory Instruction Fetch Port 2ALEPSEN ------++----.1tcALEtd (PROG-ALE)P20-P23110-...;;..----- DURING -""\./---::::::--~ V-::::;-"':'-~r===-\r--=-:-:=-:!:f-..Jr---}----{ I OUTPUTIItd (A-ALE)BUS --~~AruDmD~RE~SS~-+...;....~::!ill:~r-------tsu (PSEN-O)P20-P23DURINGINPUTPROG•. MITSUBI$HI.... ELECTRIC4-43


MITSUBISHI MICROCOMPUTERS, /MSM80C49·XXXP/MSM80C39P-6SINGLE-CHIP I-BIT CMOS MICROCOMPUTERDESCRIPTIONThe M5M80C49-XXXP and M5M80C39P-6 are 8-bit parallelmicrocomputer fabricated on a single chip using silicongate CMOS technology.FEATURES• Single 5V power supply• Instruction cycle ..................... 2.5~s (min)• Basic machine instructions .................... 971-byte instructions ..... . . . . . . . . . . . . . . . . . .. 692-byte instructions . . . . . . . . . . . . . . . . . . . . . . .. 28• Direct addressing' ............... up to 4096 bytes• Internal ROM (except M5M80C39P-6) ..... 2048 bytes• Internal RAM ............... " ..... 128 bytes• Built-in timer/event counter ................. 8 bits• I/O ports ............ . . . . . . . . . . . . . . . . .. 27 lines• Easily expandable memory and I/O• Subroutine nesting ...................... 81evels• External and time/event counter interrupt,"1 level each• High noise margin• Low power dissipation modes (Vcc = 5V)Operating. . . . . . . . . . . . . . . . . . . . . . . . . .. 50mWHALT mode ......................... 15mWStand-by ............................ 50~WAPPLICATIONControl processor for a wide variety of applicationsPIN CONFIGURATION (TOP VIEW)RESET INPUTAESET-+ •SINGLE-STEP INPUTSS ... 5REQ0~~f~~~0::: INT -+ ~EXTERNAL ACCESS EA -+ 7READ AD +- 8PRO·GRAM --­STORE ENABLE PSEN +- 9WRITE WA +- '0ADDRESSE~~1I~ ALE +- 11DATA BUS( 0 V) VssVee (5V)39 +- Tl TEST PIN 138 *P237 * 7 }P2 6I/O PORT 236 *P2s35 *P24I/O PORT 127 * P1 0Z6 +- STBY STANDBYzs .... PAOG~/3TERNALZ' *-...,_____--11- 2 .. ' * P 2 0Outline 40P4P2 3} CONTROLOUTPUTZ3 * P2z I/O PORT 212 "P21FUNCTIONThe M5M80C49-XXXP and M5M80C39P-6 are integrated8-bit CPU, with memory (ROM, RAM) and timer/eventcounter interrupt all contained on a single chip.BLOCKDIAGRAM1--RO REGISTER 0Rl REGISTER 1R2 REGISTER 2 0R3 REGISTER 3 :>


MITSUBISHI MICROCOMPUTERSMSM80C49-XXXP/MSM80C39P-6SINGLE-CHIP a-BIT CMOS MICROCOMPUTERPIN DESCRIPTIONVssPinVee--STBYGroundNameMain power supplyStandbyTo Test pin 0Xl, X 2RESETCrystal inputsReset- SS Single stepĪNTEAInterruptExternal access- RO Read controlPSEN-WRALEProgram store enableWrite control0 0 -0 7 Data busP2o:""'P2 7 Port 2PROGPl o-P1 7TlAddress latch enableProgramPort ITest pin IInput or outputInputInputOutputInputInputInputInputInputOutputOutputOutputOutputInput/outputInput/outputOutputInput/outputOutputInput/outputInputNormally connected to ground (OV).Connected to 5V power supply.FunctionCDConnected t05V power supply during normal operation.~Used when entering the standby mode. Power dissipation is reduced by connecting this to OV.CDControl signal from an external source for conditional jumping in a program. Jumping is dependent onexternal conditions (JTO/JNTO).~Used for outputting the internal clock signal (ENTO CLK).External crystal oscillator or RC circuit input for generating internal clock signals.An external clock signal can be input through Xl or X2.Control used to initialize the CPU.Control signal used in conjunction with ALE to stop the CPU through each instruction, in the single-stepmode.CDControl signal from an external source for conditional jumping in a program. Jumping is dependent onexternal conditions (JNI).~Used for external interrupt to CPU.CDN ormally maintained at OV.~When the level is raised to 5V, external memory will be accessed even when the address is less than40016 (2048). The M5M80C39P is raised t05V.Read control signal used when the CPU requests data from external data memory or external device tobe transferred to the data bus.(MOVX A, @Rr, and INS A, BUS)Strobe signal to fetch external program memory.Write control signal used when the CPU sends data through the data bus to external data memory or externaldevice.(MOVX @Rr, A and OUTL BUS, A)A signal used for latching the address on the data bus. An ALE signal occurs once during each cycle.CDProvides true bidirectional bus transfer of instructions and data between the CPU and external memory.Synchronizing is done with signals RD/WR. The output data is latched.~When using external program memory, the output of the low-order 8 bits of the program counter aresynchronized with ALE. After that, the transfer of the instruction code or data from the external program--memory is synchronized with PSEN.@The output of addresses for data using the external data memory is synchronized with ALE. After that,the transfer of data with the external data: memory is synchronized with RD/WR.(MOVX A, @R r , and MOVX @R r , A)'CDQuasi-bidirectional port. When used as an input port, FF16 must first be output to this port. After reset,when not used as an output port, nothing needs to be output.~P20-P23 output high-order 4 bits of the program counter when using external program memory.@P20-P23 serve as a 4-bit I/O expander bus for the M5M82C43P.Strobe signal for M5M82C43P I/O expander.Quasi-bidirectional port. When used as an input port, FF16 must first be output to this port. After reset,when not used as an output port, nothing needs to be output.CDControl signal from an external source for conditional jumping in a program. Jumping is dependent onexternal conditions (JTI/JNTl).~When enabled, event signals are transferred to the timer/event counter (STRT CNT).II• MITSUBISHI"ELECTRIC4-45


MITSUBISHI MICROCOMPUTERSMSM80C49-XXXP IMSM80C39P-6SINGLE-CHIP 8-BIT CMOS MICROCOMPUTERABSOLUTE MAXIMUM RATINGSSymbol Parameter Condtions LimitsVee Supply voltage Vss-0.3- 7VI Input voltage V ss - O. 3-Vee + 0.3Vo Output voltage Vss-0.3- Vee+ 0 . 3Pd Power dissipation Ta~25·C 1.5Topr Operating free·air temperature range -40-85Tstg Storage temperature range -65-150UnitVVVW"C"CRECOMMENDED OPERATING CONDITIONS (Ta~-40-85·C, unless otherwise noted)LimitsSymbol Parameter UnitMin Typ MaxVee Supply voltage 4.5 5 5.5 VVss Supply voltage 0 VVIHl High·level input voltage, except EA. RE5ET. Xl. X2 0.7 X Vee Vee VVIH2 High·level input voltage, EA. RE5ET. Xl. X2 0.8xVce Vee VVIL Low·level input voltage, except EA. RE5E T. Xl. X2 VSS 0.3 X Vee VVIL Low·levelinputvoltage, EA, RESET. Xl. X2 VSS 0. 2XVee VELECTRICAL CHARACTERISTICS (Ta= -40-85·C. Vec=5V ± 10%. VSS =OV, unless otherwise noted)Symbol Parameter Test conditionsMinLimitsTypMaxUnitVOL Low·level output voltage IOL=2mA0.45VVOHl High·level output voltage, except PI 0- P17, P2 0- P2 7 I OH = -400pA O.75XVCCVVOH2 High·level output voltage, PI 0- P 1 7, P 20- P 2 7 IOH=-lpA O.75XVccVII Input current, Tl.INT. 55. EA. STBY VSS~VIN~Vee -1010pAIOZ Output current, BU 5. To , high impedance state VSS~VIN~Vee -1010pAIlL 1 Input current during low level, Port VIL=VSS- 50pAII L2 Input current during low level, R E 5 E T VIL=VSS- 50pAIcC Supply current at 6MHz10mAIcc Supply current during HAL T at 6MHz (Note I)3mAIcc Supply current during 5 TAN D BY (Note 1)10pAVee(STB) Stand by power supply voltage 2VNote 1.BUS, To. TI, EA, S5. STBY, RESET. TNT =Vee or VSSTIMING REQUIREMENT (Ta=-40-85·C. Vcc=5V±10%. VSS =OV, unless otherwise noted)SymbolParameter<strong>Al</strong>ternativesymbolMinLimitsTypMaxUnitteCycle timetey 2.515 psth (PSEN'D)th (R'D)tsu (PSEN' D)tsu (R'D)tsu (A'D)tsu (PROG' D)th (PROG'D)Data hold time after P 5 E NData hold time after RDData setup time after PSENData setup time after R DData setup time after ADDRESSData setu p ti me after PRO GData hold time after PROGtOR 0tOR 0t ROt ROtADt pRtpF 0200 ns200 ns500 ns500 ns950 ns810 ns150 ns4-46• MITSUBISHI..... ELECTRIC


MITSUBISHI MICROCOMPUTERSMSM80C49· XXXP/MSM80C39P·6SINGLE-CHIP 8-BIT CMOS MICROCOMPUTERSWITCHING CHARACTERISTICS (T a= -40-85"C, Vee= 5V ± 10%, VSS=OV, unless otherwise noted)<strong>Al</strong>ternativeLimitsSymbol Parameter Unitsymbol Min Typ MaxtW(ALE) ALE pulse width tLL 400 nstd (A-ALE) Delay time, address to A LE signal tAL 150 nstv (ALE-A) Address valid time after ALE tLA 80 nstw(PSEN) P SEN pulse width tee 700 nstw(R) RD pulse width tee 700 nstw(W) W R pulse width . tee 700 nstd (O-W) Delay time, data to W R signal tow 500 nstv (W-O) Data valid time after WR two 120 nstd (A-W) Delay time, address to WR signal tAW 230 nstd (AZ-R) Delay time address floating to R 0 signal tAFe 0 nstd(AZ-PSEN) Delay time, address floating to PSEN signal tAFe 0 nstd(PC-PROG) Delay time, port control to PROG signal tep 110 nstv(PROG-PC) Port control valid time after PROG tpe 140 nstd(O-PROG) Delay time, data to PROG signal top 220 nstv(PROG-O) Data valid time after PROG tpo 65 nstW(PROGL) PROG low pulse width tpp 1510 nstd (O-ALE) Data time data to ALE tpL 400 nstv (ALE-O) Data valid time after ALE tLP 100 nsNote: Conditions of measurement: control output CL : 80pFdata bus output, port output CL : 150pF tc : 2.5lls0. 7V ee ----.... ~----Xo.7vee0. 3Vee ____..J..0. 3V eeIITIMING DIAGRAMRead from External Data MemoryALEtW(R)Write to External Data MemoryALEWR ----------------,1td (AZ-R)th (R-O)BUSInstruction Fetch from External ProgramMemorytcPort 2ALEtw (PSEN)BUS-..u_--


MITSUBISHI MICROCOMPUTERSMSM80C49-XXXP/MSM80C39P-6SINGLE-CHIP a-BIT CMOS MICROCOMPUTERLow power dissipation mode(1 ) HALT modeIt will b.e. in HALT mode when HALT instruction is executedand program -execution is stopped. In HALTlmode, only the basic clock operates and the others areall in the halt state. MCU keeps the contents of the registersin the state before the execution of HALT instrucitons.The pin conditions are shown below.Table 1PinData busPorts1,2ALEPSEN.RDWR. PROGT¢lT1(counter input)(Timer)ConditionsOutput mode : Data outputInput mode: High inpedence(Input mode for M5M80C39P-6)Port data outputLHProvided clock is continuedThe first pulse input is effective.After the reset of Halt mode. the count continues.Halt(2) Standby modeIt will be in Stnadby mode when STBY input goes "L"after setting RESET ipput to "~". In standby mode, alloperations including clock stop, and only the contentsof the buit-in RAM are maintained. For the standbymode reset, let STBY pin "H", Keeping RESET inputlow, and then let RESET input input "H". After that theinternal state is inilialized and program excuition startsfrom address O.Control method of standby mode (Example)Place the capacitor to RESET pin, as shown in Fig 2, inorder to make th standby mode control easier, so thatthe standby mode can be controlled by only contollingSTBY pin.M5M80C49-XXXp·M5M80C39P-6HALT stateL-+------------------------~LL'------------1- 1 count up-----+- 1 count upL-+ ____ ..H-+-----------------------+_H-+----..H-+------........--------""'1- 1 count upFig. 2Control circuit example for standby modeFig. 1Counter operation in the HALT modeThe HALT mode can be cleared by the following 2methods(i) By RESET inputWhen RESET input goes "L", an internal state is initializedas same as the normal reset operation, andthe program starts from address O.(II) BylNT inputWhen INT input gose "L",and if it is in the interuptenable state, the interrupt sequence will start afterexecuting the 2en instruction following HALT instructions.If is the interrupt disable state, the program exeutionstarts from the next address to HALT instructions.4-48 • MITSUBISH. I"'ELECTRIC


MELPS 8-41 SLAVE MICROCOMPUTERS


MITSUBISHI MICROCOMPUTERSMELPS 8-41 SLAVE MICROCOMPUTERSFUNCTIONS OF MELPS 8-41 SLAVE MICROCOMPUTERSDESCRIPTIONThe MELPS 8-41 family is a general-purpose 8-bit CPUperipheral LSI microcomputer series configured internallywith a CPU, RAM, ROM, 1/0 ports, timer and other functions.These microcomputers function independently of externalconnections but since they operate based on the instructionsfrom the CPU (master CPU) that employs theseLSls as the peripheral LSls, they are known as slave microcomputers.Data is passed to and from the master CPU and slave microcomputersasynchronously through the buffer registersbuilt into the MELPS 8-41 and therefore, when seen fromthe master CPU side, the LSI can be treated in every waylike an ordinary peripheral LSI. Since the MELPS 8-41 has abuilt-in microcomputer, its functions can be changed easilysimply by altering the program of the internal ROM.MELPS 8-41SLAVE MICROCOMPUTER FAMILYInput clockType nameROM(MHz)(bytes)M5L8041 A-XXXP 6 1024M5L8042-XXXP 12 2048CapacityRAM(bytes)641281/0 Technology used(ports)18 ED NMOS18 ED NMOSBLOCK DIAGRAM OF MELPS 8-41DATA BUS INPUT/OUTPUT PORT 1AP1 s P1 7 'INPUT/OUTPUT PORT 2IIVce (5V)Voo (5V)Vss (OV)RESETSINGLE STEPTo TEST PINOT, TEST PIN 1R'------{ 7 EAEXTERNAL I/O CONTROLOUTPUTREADWRITECHIP SELECTADDRESSEXTERNAL ACCESSNote1: The M5L8042-XXXP has a 2048-word X 8-bit ROM.2 : The M5L8042-XXXP has a 128-word X 8-bit RAM.• MITSUBISHI..... ELECTRIC5-3


MITSUBISHI MICROCOMPUTERSMELPS'8·41 SLAVE MICROCOMPUTERSFUNCTIONS OF MELPS' 8 .. 41 SLAVE MICROCOMPUtERSBASIC FUNCTION BLOCKSProgram Memory (ROM)TheM5L8041A-XXXP contains a 1042-byte ROM while theM5L8042-XXXP has a built-in 2048-byte ROM. The programfor the user application is stored in this ROM. Addresses 0,3 and 7 of the ROM are reserved for special functions.Table 1 shows the meaning and functions of these specialaddresses.Table 1 Reserved, defined addressesand their meanings and functionsAddressMeaning and function0 The first instruction executed after a system reset.37The first instruction executed after an external Interrupt isaccepted,The first Instruction executed after a timer Interrupt,based on the timer/event counter,. is accepted.Data Memory (RAM)The M5L8041 A-XXXP has a built-in 64-byte (128 bytes forM5L8042-XXXP) RAM, The RAM is used for data storageand manipulation and it is divided into sections for moreefficient processing. Addresses 0 - 7 and 24 - 31 form twobanks of general-purpose registers that can be directlyaddressed, Addresses 0-7 compose bank 0 and are numberedRo- R 7 • Addresses 24-31 compose bank 1 and arealso numbered Ro- R 7 . Only one bank is active at a time.The instructions SEL RBO and SEL RB1 are used to selectthe working bank. Fig. 1 shows the division of the RAM andits mapping. The remaining sections, addresses 32 andabove, must be accessed indirectly using the generalpurposeregisters Ro or R 1 • Of course, all addresses can beindirectly accessed using the general-purpose registers Roand R 1 •A good practice to simplify programming is to reservegeneral-purpose register bank 0 for use of the main programand register bank 1 for interrupt programs. For example,.if register bank 0 (ad


MITSUBISHI MICROCOMPUTERSMELPS 8-41 SLAVE MICROCOMPUTERSFUNCTIONS OF MELPS 8-41 SLAVE MICROCOMPUTERSProgram Counter (PC) and Stack (SK)The M5L8041A-XXXP has a 10-bit (11 bits for the M5L8042-XXXP) program counter which is illustrated in Fig. 2.When an interrupt or a subroutine call has occurred, theprogram currently being executed is interrupted and theexecution flow transters to the interrupt program or subroutine.When such a condition has been encountered, thevalue currently stored in the program counter is saved foruse when restarting execution of the original program flow.The place where these program counter values are storedis the program counter stack. In addition to the programcounter, the high-order 4 bits of the PSW (program statusword) , which will be described later, are saved in thestack. Addresses 8 -- 23 of the RAM are used for this purpose.10 bits (or 11 bits for the M5L8042-XXXP) for the PCand 4 bits for the PSW are saved. Therefore, a RAM capacityof 2 bytes (16 bits) is used for each time. This means thatit is possible to use the program counter stack wiV! theRAM 8 --23 addresses to store both the PSW and programcounter on top of each other up to 8 levels. This situation isindicated in Fig. 3.The 3-bit stack pointer indicates at which level data isbeing stored in the stack. The stack pointer is also a part ofthe PSW but it is not stored in the program counter stack. Itis automatically incremented by 1 whenever the programcounter and PSW are stored in the program counter stackwhile, conversely, it is decremented by 1 every time storedvalues are taken out. The stack pOinter always shows thepositon of the program counter stack which is used as thenext storage place. Consequently, when a return is madefrom a subroutine (using the RET or RETRinstruction), thestack pointer is first decremented by 1 and then the contentsof the program counter stack indicated by the stackpointer are transferred to the program counter.(Note 5)Flg.2Program counterNote 5 : PC 10 for M5L8042-XXXPFig.3Stack pointer8 2 8 11o8 ao 0stack pointer1:I0I1:I0 I1III:I~1:0PC4-7, PCO-3MSB LSBRAM register number(Data memory address)R23R22R 21R20R19R lSR17RUlR 15R14R13R 12RllI RlOP8\A.(4)1 PCS-9Rg (Note 6)RsRelationship between program counter stack andNote 6 : PC S -PC 10 for M5L8042-XXXPII• MITSUBISHI.... ELECTRIC5-5


MITSUBISHI MICROCOMPUTERSMELPS 8-41 SLAVEM-ICROCOMPUTERSFUNCTIONS OF MELPS 8-41 SLAVE MICROCOMPUTERSProgram Status Word (PSW)The PSW (program status word) is stored in 8 bit~ in theregister storage. The configuration is shown in Fig. 4. Thehigh-order 4 bits of the PSW are stored in the stack, alongwith the PC, when an interrupt is accepted or a subroutin~call executed. When control is returned to the main programby RETR, both the PC and the high-order 4 bits of PSWare restored. When control is returned by RET, only the PCis restored, so care must be taken to ensure that the contentsof the PSW are not unintentionally changed.The order and meaning of the 8 PSW bits are given below.Bit O-Bit 2 : Stack pointer (So, S1, S2)Bit 3 : Not usedBit 4 : Working register bank indicator0= BankO1 = Bank 1Bit 5 Flag 0 (value is set by user and can betested with JFO conditional jump instruction.)Bit6 : Auxiliary carry bit (AC). It is set/reset by theADD and ADDC instructions and used by theDAA decimal compensation instruction.Bit7 : Carry bit (CY). This indicates an overflow afteran arithmetic or logic operation.1/0 PortsThe MELPS 8-41 has two 8-bit ports, called port 1 and port 2.'(1) Port 1 and port 2Ports 1 and 2 are both 8-bit ports with identical properties.The output data of these ports are retained anddo not change until another output is loaded into them.. When used as inputs, the input data is not retained. sothe input signals must be maintained until an input instructionis executed and completed ..Ports 1 and 2 are so-called quasi-bidirectional portswhich have a special circuit configuration to accomplishthis purpose. <strong>Al</strong>l the pins of the ports can be usedfor input or for output.CPU interna~""'--IbusReset -+---1Write pulse--+----+------l5VPortl~~~--t IPort 2pinsFlg.4High-order 4 bits are stored along with PC in stack.I Cy I AC I Fo I as 11 I S2 I S1 I So ICy : CarryA C : Auxiliary carry '( carry from low-order 4 bits of ALU)Fo : Flag 0as : Working register bank indicatorS2 }S 1 Stack pointerSoProgram status wordFlg.51/0 port 1 and 2 circuitThe special, circuit is shown in Fig. 5. Internal on-chippull-up resistors are provided for all the ports for pullupto 5V. The current required for setting the TTL signalhigh can be supplie(J through these pull-up resistors.In addition, the level can be pulled low by thestandard TTL output. This means that any pin can beused for both input and output.To shorten the switching time from a low level to highlevel, when l's are output, a device with a relatively lowimpedance is turned on for a short time (approx. 500nswhen a 6MHz crystal oscillator is used).To use a particular port pin as an input, a logic "1"must first be written to that pin. After resetting, a port isset to an input port and remains in this state.Therefore, it is not necessary to output all l's if it is tobe used for input. In short, a port being used for outputmust output l's before it can be used for input.5-6 • MITSUBISHI..... ELECTRIC


MITSUBISHI MICROCOMPUTERSMELPS 8-41 SLAVE MICROCOMPUTERSFUNCTIONS OF MELPS 8-41 SLAVE MICROCOMPUTERSThe individual terminals of the quasi-bidirectional portscan be used for input or output. Some terminals, therefore,can be in the input mode while the remaining terminalsof a port are in the output mode. This capabilityof ports 1 and 2 is convenient for inputting or outputting1-bit data with few bits. The logical instructions ANLand ORL can easily be used to manipulate the input oroutput of these ports.(2) Data busThe data bus (00 0 """ 00 7 ) handles the data, commandsand statuses between the master CPU and MELPS 8-41. It is controlled by the following 4 control signals.Table 2 shows the relationship between the control signalsand the data bus.Ao : Address input indicating data/command busbuffer registers and status registerR : Read inputW : Write inputS : Chip select inputDQo-DQ7 .:..SoAoAo,}SoWSoAoAjj8/I'StatusST7 MOV STS,AST6 4STsST4FlFaIBFOBFInternalbusOutput data OUT DBB, Abus buffer 8-/(OBB(O»~Table 2Control signals and data busS R W Ao Data bus mode Data on data bus0 0 1 0 Read Data0 0 1 1 Read Status0 1 0 0 Write Data0 1 0 1 Write Command (F, .... 1 )1 X X X High impedance -SoW8,'"InputIN A, OBBdata/command8bus buffer ~(08B(I»IIThe internal configuration of the data bus is shown in Fig. 7.The functions of the 3 registers indicated (status register,output data bus buffer register and input data/commandbus buffer register) are now described in detail.Flg.6Internal configuration of data bus controlFlg.7Internal configuration of data bus• Status registerThe status register is c9nfigured with 8 bits and the highorder4 bits (ST 4 -ST 7 1 can be set as required with a software(MOV STS, A) instructions. The low-order 4 bits (OBF,IBF, Fo, F 1 ) are set as follows:OBF (output buffer full)The OBF flag is automatically set to "1" when the output instruction(OUT DBB, A) is executed inside the MELPS 8-41and it is cleared when the contents of the output data busbuffer are read by the master CPU.IBF (input buffer full)The IBF flag is automatically set to "1" when the data orcommands are written into the input data/command busbuffer by the master CPU and it is cleared when the inputinstruction (IN A, DBB) is executed inside the MELPS 8-41.Fo (flag 0)The Fo flag is set by the flag setting instructions (CPL Fo,CLR Fo) and it is used to inform the master CPU of the internalstate of the MELPS 8-41.• MITSUBISHI"'ELECTRIC5-7


MITSUBISHI MICROCOMPUTERSMELPS8·41 SLAVE MICROCOMPUTERSFUNCTIONS OF MELPS 8·41 SLAVE MICROCOMPUTERSF1 (flag 1)When the data or command is input into the input datalcommand bus buffer by the master CPU, the F1 flag is setto the condition of the Ao input.The F1 flag is also set by the flag setting instructions (CPLF1, CLR F1).• Output Data Bus Buffer RegisterThe accumulator (A) contents are transferred to the DBB(0) output data bus buffer register by the OUT DBB, A instruction.Since the OBF flag is set at this time, the masterCPU can judge whether the data has been transferred tothe register by confirming the state of the OBF flag.• Input Data/Command Bus Buffer (DBB(l)) RegisterWhen the write request (W =0) is generated from the masterCPU, the data on the data bus is transferred to the DBB(1) input data/command bus buffer register. Since the IBFflag is set at this time, it is possible to judge whether thedata or command has been transferred inside the MELPS8-41 by confirming the state Qf this flag.Conditional Jumps Using Pins To, T1and Flags IBF, OBFThe conditional jump instructions are used to alter· programs,depending on the internal and external conditions(states) of the CPU. Details of the jump instructions can befound in the section on machine instructions.The input signal status of pins To and T1, and the states ofthe IBF and OBF flags can be checked by the conditionaljump instructions. These input pins, through conditionaljump instructions such as JTO and JNTO, can be used tocontrol a program. This means that programs and processingtime can be reduced by being able to test data i':l theinput pin rather than reading the data into a accumulatorand then testing it.Pin T1 has other functions and uses which are not related toconditional jump instructions. Details of these other functionsand uses can be f.ound on the section dealing with pinfunctions.The unconditional jump instructions for enabling a jump tobe made to the address where the ordinary interrupt pro­,cessing program is stored are contained in address 3 of theprogram memory.The interrupt level is one so that the next interrupt cannotbe accepted until the current interrupt processing has beencompleted. The RETR instruction terminates the interruptprocessing. That is to say, the next interrupt cannot beaccepted until the RETR instruction is executed. The nextinterrupt can be accepted at the start of the second cycleof the RETR instruction (2-cycle instruction). Timer/eventcounter overflow which causes an interrupt request will alsonot be accepted.Priority is given to the external interrupt when both an externalinterrupt and timer interrupt have been generated atthe same time.CDTIMER INTERRUPT ENABLE FF (TCNTF)®TlMER INTERRUPT REQUEST FF (TIRF)@EXTERNAL INTERRUPT LATCH@EXTERNAL INTERRUPT ENABLE FF (INTF)@INTERRUPT ENABLE FF (IEF)@INTERRUPT ACKNOWLEDGE FFQ)EXTERNAL INTERRUPT PENDING FF (EIPF)InterruptThe CPU reco~nizes ~n external interrupt by a low-levelsignal at the Sand W pins. When such an interrupt isaccepted, the external interrupt pending flip-flop and IBFflag are set.Interrupt requests are sampled between the SYNC signaloutputs of every machine cycle. When a request is recognized,then as soon as the instruction being executed isterminated, a subroutine call is made to address 3 of theprogram memory. As with ordinary subroutine calls, theprogram counter and program status word (PSW) are savedin the program counter stack.Flg.SInterrupt control section configuration5-8 •. MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSMELPS 8-41 SLAVE MICROCOMPUTERSFUNCTIONS OF MELPS 8-41 SLAVE MICROCOMPUTERSTable 3 Acceptance of InterruptsItem Conditions Execution detailsInternal Interrupt When TCNTEF No external interrupt Interrupt is executed and call is mode to address 7.(timer INT enable FF) = 1 I During external interrupt executionInterrupt is held.When TCNTFInterrupt is not executed or held.(timer INT enable FF ) = 0 TF (Timer flag)+- 1External interrupt When INo timer interrupt Interrupt is executed and call is made to address 3.(external INT enable FF) = 1 I During timer Interrupt execution IWhen (external INT enable FF) = 0Timer and external interruptsCombination is same as conditions abovegenerated simultaneouslyInterrupt is not executed but held.External interrupt takes priority and is executed.When a second level of external interrupt is' required, thetimer interrupt, if not being used, can provide this. This isdone by enabling the timer/event counter interrupt and settingthe timer/event counter to FF 16 • The CPU is placed inthe event counter mode. The interrupt is then generated inaddress 7 by setting the Tl input from the external sourcefrom the high to low level.The IBF flag can be tested using a conditional. jump instruction.For further details, check the section on the conditionaljump instructions, pins To and Tlo and the IBF andOBF flags.Timer I Event CounterThe timer/event counter for the MELPS 8-41 is an 8-bitcounter, that is used to measure time delays or count externalevents but not both. The same counter is used to measuretime delays or count external events simply by changingthe input to the counter.The counter can be initialized by executing an MOV T, Ainstruction. The value of the counter can be read for checkingby executing the MOV A, T instruction. Reset will stopthe counting but the counter is not cleared, thus enablingcounting to be resumed.The largest number the counter can contain is FF 16 . If it isincremented by 1 when it contains FF 16 , the counter will bereset to 00 16 , the overflow flag is set and a timer interruptrequest is issued. The timer flag can be checked using theJTF conditional branch instruction, and it is cleared by executingthe JTF instruction or by resetting the system.When the timer interrupt is accepted, a subroutine call i!rmade to address 7 of the program memory.When both a timer and external interrupt request aregenerated at the same time, the external interrupt is givenpriority and will be accepted first by automatically calling toaddress 3 of the program memory. The timer interrupt requestis kept and will be processed when the external interrupthas been completed and a RETR instruction is executed.A latched timer interrupt request is cancelled whena timer interrupt request is generated. The STRT CNT instructionis used to change the counter to an event counter.Then the pin Tl signal becomes the input to the eventcounter and events are counted up at the Tl fall. The maximumrate that can be counted is one time in 3 machine cycles(7.5J.Ls when using a 6MHz crystal). The high-level atTl must be maintained at least * of the cycle time (500nswith a 6MHi: crystal).The STRT T instruction is used to change the counter to atimer. The internal clock signal becomes the input to thetimer. The internal clock is 3~ of 400kHz (with a 6MHzcrystal) or 12.5kHz (see Fig. 9). The timer is thereforecounted up every 80J.Ls. The counter can be initialized byexecuting an MOV T, A instruction. Delay times varyingfrom 80J.Ls to 20ms (256 count) can be obtained by detectingthe counter overflows. Even times of more than 20ms canbe achieved by counting the number of overflows using theprogram.A resolution of less than 80J.Ls can be obtained in the eventcounter mode by supplying an external clock to pin T 1 . It isalso possible to supply every third (or more) prescaled ALEsignal to pin Tl instead of an external clock.II• MITSUBISHI.... ELECTRIC5;""9


MITSUBISHI MICROCOMPUTERSMELPS 8-41 SLAVE MICROCOMPUTERSFUNC.TIONS OF MELPS 8-41 SLAVE MICROCOMPUTERSTIMEROVERFLOW2.5tis·(when using a6MHz crystal)Instruciton cycleI 85 Sl 82 83 T S4 I 85 81 IInstructionInstruction programdecode,Instruction executionfetch counterrenewalTIMERFLAG (TF)S 0Flg.12Instruction execution timingFlg.9EOGE OE TECTORTimer/event counter configurationCycle TimingThe output of the state counter is + the input frequencyfrom the oscillator, and a ClK signal is produced which determinesthe times of each machine state (see Fig. 10) .During the cycle count the ClK signal is prescaled by +and a machine cycle containing 5 states is produced. TheMElPS 8-41 instructions are executed in one or twomachine cycles. Fig. 12 shows the internal operation with aninstruction for~ed from one machine cycle.ResetThe RESET pin is for resetting the CPU. A Schmitt triggercircuit along with a pull-up resistor are connected to it onthe chip. A sufficiently long pulse can be obtained for resettingby attaching 1 J..l F capacitor as shown in Fig. 13. Anexternal reset pulse applied at RESET must remain at thelow level for at least 10ms after the power has been turnedon and after it has reached its normal level.The reset function causes the following initialization withinthe CPU.(1) The program counter is reset to O.(2) The stack pointer is reset to O.(3) The register bank 0 is selected.(4) Ports 1 and 2 are reset to the input mode.(5) External and timer interrupts are reset to disable state.(6) Timer is stopped.(7) Timer flag is cleared.(8) Flags Fo and F1 are cleared.MELPS8-41Flg.l0 Clock generator circuit5VInternalclock~.~~l- "SYNC -4--+-__ ~Flg.13Example of reset circuitPROGt--r--1--rIL~_~-4_~Flg.llClock and generated cycle signals5-10 • MITSUBISHI"'ELECTRIC


MITSUBISHI MICROCOMPUTERSMELPS 8-41 SLAVE MICROCOMPUTERSFUNCTIONS OF MELPS 8·41 SLAVE MICROCOMPUTERSSingle·Step OperationThe MELPS 8-41 is provided with an SS pin for facilitatingsingle-step operation where the CPU stops after the executionof each instruction is completed. The user can usethis to trace the flow of the program, instruction by instruction,and find this to be an aid in program debugging.SS is used in synchronization with the timing of the SYNCsignal output from the CPU. Fig. 14 shows the circuit usedfor single-step operation and the timing involved.svSingle-step modesvThe CPU is made to rec~nize that it is to stopwhen SS is set to the low level.!The CPU stops when the next instruciton isfetched. (If a 2-cycle instruction is being executed,the CPU stops after the instruciton iscompleted.)The CPU advises the • external equipment thatit has entered the stop mode by setting theSYNC signal to high.+By setting SS high, the CPU is made to recognizethat it may exit from the stop mode.The CPU advises the external equipment thatit has exited from the stop mode by setting theSYNC level low, and it moves on to the executionof the instruction at hand.~(a) Example of single-step circuitBufferIf the CPU is to be stopped again upon completionof the next instruciton, SS is set low immediatelyafter the SYNC signal goes low.Unless the single-step mode is required fromthe next instruction, SS is kept high.SYNCFlg.15CPU operation in single-step modeFlg.14Instruction ---~o---- .execution(b) Single-step timingStopI Instruction-+-execution~Ingle-step operation circuit and timingA type D flip-flop with----.ereset and reset pins is used togenerate the signal for SS.Wh~n the preset pin is kept low, SS goes to the high level,which puts the CPU in the run mode.For single-step operation the preset pin is switched to thehigh level and SS to the low level. While SS is low, theCPU stops. To restart the CPU, a pulse is supplied to theclock pin on the type D flip-flop. This sets SS to the highlevel, and the CPU fetches the next instruction and beginsto execute it. Once the CPU starts the execution, the SYNCsignal connected to the reset pin of the type D flip-flop islow and so SS also goes low. As soon as the CPU finishesexecuting the instruction, it is again stopped by SS going tothe low level.Fig.15 shows the operation of the CPU in the single-stepmode.Central Processing Unit (CPU)The CPU is composed of an 8-bit parallel arithmetic unit,accumulator, flag flip-flop and instruction decoder. The 8-bitparallel arithmetic unit has circuit to perform the four basicarithmetic operations (addition, subtraction, multiplicationand division) as well as logical operations such as AND andOR. The carry, zero and other states generated by theseoperations are set in the flag flip-flop. The accumulatorsupplies the operands (HIENZANSUU) to the arithmeticcircuit, receives the results from the same circuit andkeeps them. The flag flip-flop keeps the carry, zero andother states when various kinds of arithmetic operation instructionsare executed.DMA ControlPorts P2 6 and P2 7 of the MELPS 8-41 can be used not onlyas ordinary input/output ports but also for the control signalemployed for DMA handshaking. Immediately after resetting,these two ports function as ordinary ports (seeFig. 16)..MITSUBISHI"'ELECTRIC5-11


MITSUBISHI MICROCOMPUTERSMELPS 8-41 SLAVE . MICROCOMPUTERSFUNCTIONS OF MELPS 8-41 SLAVE MICROCOMPUTERSM ELPS8-41P2 sOROORQnM5L.82 57POM AInterrupt Request to Master . CPUPorts P2 4 and P2 5 of MELPS 8-41 can be used not only asordinary input/output ports but also as the· outputs of theISF (input buffer full) flag and OSF (output buffer full) flag.Immediately after resetting, both ports function as inputports.P2 7OACKOACKnMELPS8-41Flg.16DMA controlWhen the EN DMA instruction is executed, P2 6 becomesthe DRO (DMA request) output. Subsequently, when P2 6 isset to "1 ", DRO becomes "1" and DMA-based data transferis requested. __ _ __ _ORO is cleared when the DACK • R, DACK • W or EN DMAinstruction is executed.Flg.18OBFOBFP2.P2 sIBFIBFInterrupt request to master CPUl'n~,ruPt to master ,a."m CPUEN DMAP26/DROWhen the EN FLAGS instruction is executed, P24 functionsas the OaF pin and P2 5 as the ISF pin. "1" must be outputto both pins so that the OSF and ISF flag states are outputto each pin, respectively. These states are not output while"0" is output to the pi!ls. The OSF flag output indicates thatdata ~s been output to the output data bus buffer register;the ISF flag output indicates that the input data/commandbus buffer register is in the data accept enable mode.RESETOUTLANLORLFlg.17Internal configuration of DMA controlWhen the EN DMA instruction is executed, P27 becomesthe DACK (DMA acknowledge) input. The DACK input isused as the chip select input for DMA transfer. There is,therefore, no connection with the state of S (chip select)during OMA transfer.Flg.19Internal configuration of IBF/OBF5-12 • MITSUBISHI..... ELECTRIC


I D3-~q~ol)MITSUBISHI MICROCOMPUTERS(. MELPS 8-41 SLAVE MICROCOMPUTERSFUNCTIONS OF MELPS 8-41 SLAVE MICROCOMPUTERSINSTRUCTION CODES~~:_~~ __ D4-r_00_0_0-r_00_0_l_-r_00_l_0~_00_11-;_0_1_00-+_0_1_01~_0_11_0-+_0_11_1-r_l_00_0-r_l0_0_l-r_l0_l_0~_10_11-;_1_1_00-+_1_1_01-+_1_1_10-+_1_1_11~6 ABC 0 E F0000 o000100100011NOPINC XCH XCHD ORl ANl ADD AD DC@ ROA, @ RO A, @ RO A, @ RO A, @ RO A, @ RO A, @ ROINC XCH XCHD ORl ANl ADD ADDCMOV MOV '~q,!STS, A @ RO, A '@RP,;#nNOV r.tOV@ R1 A, @ R1 A, @ R1 A, @ R1 A, @ R1 A, @ R1 A, @ R1@ R1, A @R1;#nOUT: ~B~ INJBl MOV:: J62: MOV ·.J~3: .,' ;;Jf,\4,;,'" ":. ,,~XRlA,@ROXRlA,@R1DBB, A, m A, DBB: "rp, A,Tm T,Am ,.f\"l :. mMOVP JMPP X:RL MOVP3JS$.m'MOVA,@ ROMOVA,@R1J~1:in'~0100 4010101100111100010011010 A1011 B1100 C1101 o1110 E1111 FEN DIS EN DIS STRT STRT STOP ClR CPl ClR CPl SEl SEl EN ENI TCNTI TCNTI CNT T TCNT FO FO F1 F1 RBO RB1 DMA FlAOSJtF ,~~to',; ~t9' :Jt":T1 :JT1 .JFOJZ· JNIBF'JN.'.".····.,., ..1 .• ·.. 0.'.·."':l",·: . '" .....,m, :,':~m', ,~G':: "ANL: MOV :M:O'V, DEC XRl llJ~?," MOVA, R1 P1, A A, R1 A, R1 A, R1 A, R1 1;1fn R1, A ::81; ~:rj; R1 A, R1 'Fii:;:m: A, R1XCH OUTl ORl ANl ADD ADDCJ .. i< MOV UPY;; DEC XRl :DJN~' MOVA, R2 P2, AXCH ORl ANl ADD AD DC MOV :'MO'l, DEC XRl :,PJNZ': MOVR3 A, R3 A, R3 A, R3 A, R3 A, R3 R3, AA3~'~ri R3 A, R3 "~$I.:m A, R3MOVD INC XCH MOVD ORl ANl ADD ADDC ORlD ANlD MOV:~OV, DEC XRl: O.JNZ MOVA, P4 R4MOVDINCA, PS RSMOVDINCA, P6 R6MOVDA,P7INCR7A, R4 P4, A A, R4 A, R4 A, R4 A, R4 P4, A P4, A R4, A R4; ~r1 R4XCH MOVD ORl ANl ADD AD DC .ORlD ANlD MOV ~QX DECA, RS PS, A A, RS A, RS A, RS A, RS PS, A PS, A RS, A:~ #,1\: RSXCH MOVD ORl ANl ADD ADDC ORlD ANlD MOV : MO~' DECA, R6 P6, A A, R6 A, R6 A. R6 A, R6 P6, A P6, A',."PR6, A :R6;.Jtn R6XCH MOVD ORl ANl ADD AD DC ORlD ANlD MOV :'~bv, DECA, R7 P7, A A, R7 A, R7 R7, A A, R7 P7, A P7, A R7, AR7j .,#n R7A, R4 R4jfTI A, R4XRl D"NZ MOVA, RS:135. 'inXRl ,O~~A, R6 I;~~;,~A,RSMOVA,R6MOVA, R7-2-byte 2-cycle instructionl-byte 2-cycle instruction• MITSUBISHI.... ELECTRIC5-13


MITSUBISHI MICROCOMPUTERSMEL'PS 8-41 SLAVE MICROCOMPUTERSFUNCTIONS OF MELPS 8-41 SLAVE MICROCOMPUTERSMACHINE INSTRUCTIONStMnemonicType 07 0 e 0 5 0 40 0 1 0MOV A, # n n 7 n 6 n 5 n 4Instruction codet/)03 0 2 D 1 0 0~Hexadecimal0 0 1 1 2 3n 3 n 2 n 1 n O n 2'" CDg, Function02 (A) - nMOV A, Rr1 1 1 11 r 2 r 1 r O F 8+ 1 r(A) - (Rr)1 r=O-7~u;c MOV Rr, A1 0 1 0~~1 0 1 1MOV Rr, #n n 7 n 6 n 5 n 4XCH A,Rr0 0 1 01 r 2 r 1 ro A 8+ 1 r1 r 2 r 1 r O B 8n 3 n 2 n 1 n O +r 2n1 r 2 r 1 r O 2 8+ 1 r(Rr) - (A)1 r=O-7(Rr) - n2 r=0-7(A)-(Rr)1 r=0-7MOV A, @Rr1 1 1 10 0 0 r 0 F 0+ 1 r(A) - (M (Rr) )1 r=O-lMOV @Rr, A1 0 1 00 0 0 r 0 A 0+ 1 r(M (Rr) ) - (A)1 r=O-l1 0 1 1~c MOV @Rr, #n n 7 n 6 n 5 n 4~CI)c":g1 0 1 0CD MOVP A, @A-0"C


MITSUBISHI MICROCOMPUTERSMELPS 8-41 SLAVE MICROCOMPUTERSFUNCTIONS OF MELPS 8-41 SLAVE MICROCOMPUTERSAffected carryC AC NoteDescriptionTransfers data n to register A.Transfers contents of register Rr to register A.Transfers contents of register A to register Rr.Transfers data n to register Rr.Exchanges contents of register Rr with contents of register A.Transfers contents of memory location of current page, whose address is in register Rr, to register A.Transfers contents of register A to memory location of current page whose address is in register Rr.Transfers data n to memory location of current page whose address Is in register Rr.IITransfers data of memory location of current page whose address is in register A to register A.Transfers data of memory location of page 3 whose address is in register A to regsiter A.Exchanges contents of memory location of current page whose address is in register Rr with contents of register A.Exchanges contents of low-order 4 bits of register with low-order 4 bits of memory location of current page whose address is in registerRr.Transfers contents of program status word to register A.0 0Transfers contents of register A to program status word.I2Transfers contents of register A to status register.0Clears carry flag and resets it to O.0Complements contents of carry flag.--Clears flag Fo and resets it to O.Complements contents of flag Fo.• - MITSUBISHI.... ELECTRIC5-15


MITSUBISHI MICROCOMPUTERSMELPS 8.-41 SLAVE MICROCOMPUTERSFUNCTIONS OF MELPS 8-41 SLAVE MICROCOMPUTERSSMnemonicTypee CLR F180Ul::I~CPL F1D7 D 6D 5 D 41 0 1 01 0 1 1Instruction codeD3 D 2D1 D O0 1 0 10 1 0 1HexadecimalUlQ)~A 5 1B 5 1UlQ)(j Function>.01 (F1)-O1 (F 1 )-(F 1 )ADD A. #n0 0 0 0"7"6"6"40 0 1 1 0 3"3"2"1"0"22 (A) - (A) +"ADD A. Rr0 1 1 01 r 2 r 1 r O 6 8+ 1 r(A) - (A) + (Rr)1 r=O-7ADD A. @Rr0 1 1 00 0 0 r 0 6 0+ 1 r(A) - (A) + (M (Rr) )1 r=O-1AD DC A. #"0 0 0 1"7"6"5"40 0 1 1 1 3"3"2"1"0"22 (A)-(A)+"+(C)AD DC A. Rr0 1 1 11 r 2r 1 r O 7 8+ 1 r(A) - (A) + (Rr) + (C)1 r=O-7ADDC A. @Rr0 1 1 10 0 0 r 0 7 0+ 1 r(A) - (A) + (M (Rr» + (C)1 r=O-1ANL A. #"0 1 0 1"7"6"5"40 0 1 1 5 3"3"2"1"0"22 (A) -(A) A"ANL A. Rr0 1 0 11 r 2 r 1 r O 5 8+ 1 r(A) - (A) A (Rr)1 r=O-7ANL A. @Rr0 1 0 10 0 0 r 0 5 0+ 1 r(A) +- (A) A (M (Rr) )1 r=O-1ORL A. #"0 1 0 0"7"6"5"40 0 1 1 4 3"3"2"1"0"22, (A) - (A) V"ORL A. Rr0 1 0 01 r 2 r 1 r O 4 8+ 1 r(A) - (A) V (Rr)1 r=O-7ORL A. @Rr0 1 0 00 0 0 r 0 4 0+ 1 r(A) - (A) V (M (Rr) )1 r=O-1XRL A. # "1 1 0 1"7"6"5"40 0 1 1 D 3"3"2"1"0 "22 (A) +- (A) V- nXRL A. Rr1 1 0 11 r 2 r 1 r O D 8+ 1 r(A) +- (A)V- (Rr)1 r= 1-7XRL A. @Rr1 1 0 10 0 0 r 0 D 0+ 1 r(A) - (A)V- (M (Rr) )1 r=O-1INC A0 0 0 10 1 1 11 7 11 (A) +- (A) + 1DEC A0 0 0 00 1 1 10 7 11 (A) - (A)-15-16.• MITSUBISHI;"ELECTRIC


MITSUBISHI MICROCOMPUTERSME'LPS 8-41 SLAVE,MICROCOMPUTERSFUNCTIONS OF MELPS 8-41 SLAVE MICROCOMPUTERSAffected carryC AC NoteDescriptionClears flag Fl and resets it to O.Complements contents of flag Fl.0 0 1Adds data n to contents of register A and sets carry flags to 1 if there is an overflow; otherwise resets carry flags to O. The result is stor~dIn register A.0 0 1Adds contents of register Rr to contents of register A and set carry flags to 1 if there is an overflow; otherwise resets carry flags to O. Theresult is stored in register Ii\.0 0 1Adds contents of register A and contents of memory location of current page whose address is in register Rr and sets carry flags to 1 ifthere is an overflow; otherwise resets carry flags to O. The result is stored in register A.0 0 10 0 10 0 1Adds carry and data n to contents of register A and sets carry flags to 1 if there is an overflow; otherwise resets carry flags to O. The resultis stored in register A.Adds carry and contents of register Rr to contents of register A and sets carry flags to 1 if there is an overflow; otherwise resets carryflags to O. The result is stored in register A.Adds carry and contents of memory location of current page whose address is in register Rr to contents of register A and sets carry flagsto 1 if there is an overflow; otherwise resets carry flags to O. The result is stored in register A.IILogical product of contents of register A and data n is stored in register A.Logical product of contents of register A and contents of register Rr is stored in register A.Logical product of contents of register A and contents of memory location of current page whose address is in register Rr is stored inregister A.Logical sum of contents of register A and data n is stored in register A.Logical sum of contents of register A and contents of register Rr is stored in register A.Logical sum of contents of register A and contents of memory location of current page whose address is in register Rr is stored in registerA.Exclusive OR of contents of register A and data n is stored in register A.Exclusive OR of contents of re,glster A and contents of register Rr is stored in register A.Exclusive OR of contents of register A and contents of memory location of current page whose address is in register Rr. is stored in reg-Ister A.Increments contents of register A by 1. The result is stored in register A.Decrements contents of register A by 1. The result is stored in register A.• MITSUBISHI.... ELECTRIC5-17


MITSUBISHI MICROCOMPUTERSMELPS 8-41 SLAVE MICROCOMPUTERSFUNCTIONS OF MELPS 8-41 SLAVE MICROCOMPUTERSSMnemonicTypeCLR A07060S 0 40 0 1 0Instruction code0 3 0 2 0 10 0 Hexadecimal0 1 1 1'" Q)>.ID2 7 1Q)'"0 Function>.()1 (A)-O(J~E:e


MITSUBISHI MICROCOMPUTERSMELPS 8-41 SLAVE MICROCOMPUTERSFUNCTIONS OF MELPS 8-41 SLAVE MICROCOMPUTERSAffected carryC AC NoteDescriptionClears contents of register A and resets to O.Forms I's complement of register A and stores it in register A.0 0 1Contents of register A are converted to binary coded decimal notation and stored in register A.Exchanges contents of bits 0-3 of register A with contents of bits 4-7 of register A.Shifts contents of register A left one bit. MSB A7 is rotated to LSB Arl.00Shifts contents of register A left one bit. MSB A7 is shifted to carry flag a~d carry flag is shifted to LSB 1.0.Shifts contents of register A right one bit. LSB Arl is rotated to MSB A7.Shifts contents of register A right one bit. LSB Arl is shifted to carry flag and carry flag is shifted to MSB A7.IIIncrements contents of register Rr by 1. The result is stored in register Rr.Increments contents of memory location of current page whose address is in register Rr by 1.Decrements contents of register Rr by 1. The result is stored in register Rr.Jumps unconditionally to address m.Jumps to memory location of current page whose address is in register A; but when instruction executed was in address 255, jumps tonext page.Jumps to address m of current page when bit b of register A is 1 . Executes next instruction when bit b of register A is O.Jumps to address m of current page when IBF is O.Jumps to address m of current page when OBF is 1.Jumps to address m of current page when timer/counter overflow flag is 1; flag is cleared after execution.Decrements contents of register Rr by 1 ; jumps to address m of current page when result is not O.jumps to address m of current page if carry flag is 1.• MITSUBISHI.... ELECTRIC.5-19


MiTSUBISHI MICROCOMPUTERSMELPS 8-41 SLAVE MICROCOMPUTERSFUNCTIONS OF MELPS 8-41 SLAVE MICROCOMPUTERSI,STypeJNC mMnemonic0 7 0 6 0 5 0 41 1 1 0m 7 m 6 m 5 m 4 ,Instruction code .,Q)0 3 0 2 0,0 0 Hexadeclma.1 ~0 1 1 0 E 6m3m 2m,mO m 2.,Q)~()FunctionWhen (C) = 0, (PCO-PC7) - m2 When (C) = 1, (PC) - (PC)+ 2JZ m1 1 0 0m 7 m 6 m 5 m 40 1 1 0 C 6m3m 2m,mO m 2When (A) = 0, (PC O -PC7) - m2 When (A) *' 0, (PC) - (PC)+ 2JNZ m1 0 0 1m 7 m 6 m 5 m 40 1 1 0 9 6m3m 2m,mO m 2When (A) *' 0, (PCO-PC7) - m2 When (A) = 0, (PC) - (PC)+ 2Q.~i\ig;:'5g()JTO mJNTO mJT1 m0 0 1 1m7m 6m e;m40 0 1 0m 7 m 6 m 5 m 40 1 0 1m7m 6m e;m40 1 1 0 3 6m3m 2m,mO m 20 1 1 0 2 6m3m 2m,mO m 20 1 1 0 5 6m3m 2m,mO m 2When (To) = 1, (PC O -PC7) - m2 When (To) = 0, (PC) - (PC)+ 2When (To) = 0, (PCO-PC7) - m2 When (To) = 1, (PC) - (PC)+ 2When (T,) = 1, (PC O -PC7) - m2 When (T,) = 0, (PC) - (PC)+ 2JNT1 m0 1 0 0m 7 m 6 m 5 m 40 1 1 0 4 6m3m 2m,mO m 2When (T,) = 0, (PCO-PC7)-m2 When (T,) = 1, (PC) - (PC) + 2JFO m1 0 1 1m7m 6m e;m40 1 1 0 B 6m3m 2m,mO m 2When (Fo) = 1, (PC O -PC7) - m2 When (Fo) = 0, (PC) - (PC) + 2JF1 m0 1 1 1m7m 6m e;m40 1 1 0 7 6m3m 2m,mO m 2When (F,) = 1, (PCO-PC7) - m2 When (F,) = 0, (PC) - (PC) + 2Q)c:CALL m~ RET.cIJJ'"RETRm,om g m a,1m7m em 'e;m41 0 0 01 0 0 10 1 0 0 1 4+ma-m,o 2m3m 2m,mO m0 0 1 18 3 10 0 1 19 3 1«SP» - (PC)(PSW4-PSW7)2 (SP) - (SP) + 1(PCo-PC,o) - m(SP) - (SP) - 12 (PC) - «SP»(SP) - (SP) - 12 (PC)(PSW4-PSW7) - «SP»IN A, Pp0 0 0 01 0 P, Po 0 8+ 1 p(A) -(Pp)2 p=1-2OUTL Pp, A0 0 1 11 0 P, Po 3 8+ 1P(Pp)-(A)2 P=1-2'S~0~Q.'".=ANL p p,#"ORL Pp, #"IN A, DBB1 0 0 1n 7 "6"5"41 0 0 0"7"6"5"40 0 1 01 0 P, Po 9 8+"3"2"'"0 p 2"1 0 P, Po 8 8+"3"2"'"0 P2"0 0 1 0 2 21(Pp)- (Pp)An2 p=1-2(Pp) - (Pp)V n2 p=1-21 (A) - (OBB)OUT DBB, A0 0 0 00 0 1 0 0 211 (OBB) - (A)I ,5-20'MITSUBISHI..... ELECTRIC


MITSUBISHI MICROCOMPUTERSMELPS 8-41 SLAVE MICROCOMPUTERSFUNCTIONS OF MELPS 8-41 SLAVE MICROCOMPUTERSAffected carryC AC NoteDescriptionJumps to address m of current page if carry flag is O.Jumps to address m of current page when contents of register A are O.Jumps to address m of current page when contents of register A are not O.Jumps to address m of current page when flag To is 1.Jumps to address m of current page when flag To is O.Jumps to address m of current page when flag T1 is l.Jumps to address m of current page when flag T1 is O.Jumps to address m of current page when flag Fo is 1.IIIJumps to address m of current page when flag F1 is 1.Calis subroutine from address m. The program counter and the high-order 4 bits of PSW are stored in address indicated by stack pOinter(SP). SP is incremented by 1 and m is transferred to PCo-PC 1O•SP is decremented by 1. Program counter is restored to saved setting in stack indicated by stack pOinter. PSW4-PSW7 are not changedand interrupt disable is maintained.SP is decremented by 1. Program counter and high-order 4 bits of PSW are restored with saved data in stack indicated by stack pOinter.Interrupt becomes enabled after execution is completed.Loads contents of Pp to register A.Output latches contents of register A to Pp.Logical product of contents of Pp and data n; outputs result to Pp.Logical sum of contents of Pp and data n; outputs result to Pp.Enters contents of data bus buffer (DBB) into register A and resets IBF.Outputs contents of register A to data bus buffer (DBB) and sets OBF.• MITSUBISHI.... ELECTRIC5-21


MITSUBISHI MICROCOMPUTERSMELPs ·8-41 SLAVE MICROCOMPUTERS[TypeFUNCTIONS OF MELPS 8·41 SLAVE MICROCOMPUTERSInstruction codeMnemonic >. g, FunctionIII0 7 0 6 0 5 0 4 0 30 2 0,0U0 HexadecimalMOVO A, Pp 0 0 0 0, , P, Po 0 C (A o-A3) +- (PpO-Pp3)+ 1 2 (A 4 -A 7 ) +- 0 p = 4-7P,PoEu"8MOVO Pp , A + , 2 P=4-7~"0as0 0, , , , P, Po 3 C (PpO -P p3 ) +- (Ao-A3)c: , 0 0 , , , P, Po 9 C (PpO -P p3 ) +- (P pO -p p3 ) 1\ (A o -A3)c.)(ANLO Pp, A + ,wP,Po 2 p=4-7~, 0 0 0, 1 P, Po 8 C . (P pO-Pp3) +- (Ppo-Pp3)V(Ao-A 3 )P,PoORLD Pp, A + , 2p,poQ)'"'"Q)p=4-70 , 0 0 0 0, 0 4 2 (A) +- (T)MOV A, T 1 1MOV T, A0 1 1 0 0 0 1 0 6 21 1(T) +- (A)E§uSTRT T~ STRT CNT::J0U';:::Q)Ei= STOP TCNTEN TCNTIDIS TCNTI0 1 0 1 0 1 0 1 5 51 10 1 0 0 0 1 0 1 4 51 10, , 0 0 1 0 , 6 51 10 0 , 0 0, 0 '.2 5 , ,0 0, , 0, 0 , 3 5 , ,(TCNTF) +- 1(TCNTF) +- 00 0 0 0 0, 0 , 0 5 (INTF) +- 1EN I 1 10 0 0 1 0 1 0 1 1 5 (INTF) +- 0DIS I1 1, , o , 0 0 1 0 1 C 5 (BS) +- 0SEL RBo 1 1, 1 0 1 0 1 0 ,0 5 (BS) +- 1SEL RB, 1 1, 1 1 0 0 1 0 1 E 5EN DMA 1 11 1 1 1 0 1 0 ,F 5 (P2 4 ) +- (OBF)EN FLAGS 1 1 (P2 5 ) +- (IBF)g 0 0 0 0 0 0 0 0 0 0NOP 1 1~Note 1 Executing an instruction may produce a carry (overflow or underflow). The carry may be lost or it may be transferred to C or AC, The (0)mark indicates a carry which affects C or AC. The detail affection of carries for instructions ADD, AD DC and DA is as follows:( C ) ...... 1 At overflow of accumulator( C ) ...... 0 At no overflow of accumulator( A C ) ...... 1 At overflow of bit 3 of accumulator(A C) ...... 0 At .no overflow2 : The contents of .ST 4 -ST 7 are read when host computer reads status of MELPS8-41.5-22• MITSUBISHI."ELECTRIC


"MITSUBISHI MICROCOMPUTERSMELPS 8-41 SLAVE MICROCOMPUTERSFUNCTIONS OF MELPS 8-41 SLAVE MICROCOMPUTERSAffected carryDescriptionC AC NoteInputs contents of Pp to low-order 4 bits of register A and inputs 0 to high-order 4 bits ofregister A.Pp's used for multiplying 8243 ports are P4-Outputs low-order 4 bits of register A to Pp. Correspondence to P2, P1 bits is shownP7.below.P4···P1P2 = 00Logical product of the low-order 4 bits of register A and contents of Pp; Pp contains result. PS···P1P2 = 01Logical sum of low-order 4 bits of register A and contents of Pp; Pp contains result.P6···P1P2 = 10P7···P1P2= 11Transfers contents of timer/event counter to register A.Transfers contents of register A to timer/event counter.Starts timer operation of timer/event counter. Count cycle is 480 times master oscillation.Starts operation as event counter of timer/event counter. Counts up when pin T1 changes from high to low input level.IIStops operation of timer or event counter.Enables interrupt of timer/event counter.Disables interrupt of timer/event counter. Resets interrupt flip-flop of CPU which is set during CPU stand-by. Timer flag is not affected.Enables external interrupt.Disables external interrupt.Selects working register bank O.Selects working register bank 1 .Enables DMA handshaking line.\Enables master interrupt.No operation. Execution time is 1 machine cycle.• MITSUBISHI.... ELECTRIC5-23


MITSUBISHI MICROCOMPUTERSMELPS 8-41 SLAVE MICROCOMPUTERSFUNCTIONS OF MELPS 8-41 SLAVE MICROCOMPUTERSItemDetails of executionTF (Timer Flag) +- 0TIRF (Timer INT Request FF) +- 0TCNTF (Timer INT Enable FF) +- 0RESET input low level INTF (External INT Enable FF) +- 0IEF (INT Enable FF) +- 1IBF +- 0EIPF (External Interrupt Pending FF) +- 0JTF execution TF (Timer Flag) +- 0Timer/event Counter TF (Timer Flag) +-,overflow TCNTE (Timer INT Enable FF) = , When TIRF (Timer INT Request FF) +-,EN TNCTI execution TCNTF (Timer INT Enable FF) +-,DIS TNCTI execution TCNTF (Timer INT Enable FF) +- 0EN I executionINTF (ExternallNT Enable FF) +-,DIS I executionINTF (External INT Enable FF) +- 0RETR executionIEF (lNT Enable FF) +-,SymbolAA o-A 3A 4 -A 7Ao-An , An+1bb 7 beb 5BSACCDBBFoF1INTFIBFmm7m6mSm4m3m2m1 mom10m 9ma(M(A»(M(Rr». (Mx(Rr»nn7n6nSn4n3n2n1 noOBFpPpP1POContentsSymbola-bit register (accumulator)PCLow-order 4 bits of register A PCO-PC 7High-order 4 bits of register APC S -PC 1OBits of register APSWValue of bits 5-7 of first byte machine codeRrBits 5-7 of first byte machine coderRegister bank selectroAuxiliary carry flagr2r1 roCarry flag 52515 0Data bus bufferSPFlag 0ST4ST7Flag 1STSExternal interrupt enable flip-flopTInput buffer full flagToDestination addressT1Second byte (low-order a bits) machine codeTCNTFcorresponding to destination addressTFBits 5-7 of first byte (high-order 3 bits) machine code :11=Content of memory location addressed by register A @Content of memory location addressed by register RrContent of external memory location addressed by +--register Rr-Value of immediate data ( )Immediate data of second byte machine codeAOutput buffer full flagVPort number ¥Port designator -Bits. of machine code corresponding to port number 0ContentsProgram counterLow-order a bits of program counterHigh-order 3 bits of program counterProgram status wordRegister designatorRegister numberValue of bit 0 of machine codeValue of bits 0-2 of machine codeValue of bits 0-2 of stack pOinterStack pOinterBits 4-7 of status registerSystem statusTimer/event counterTest pin 0Test pin 1Timer/event counter interrupt flip-flopTimer flagSymbol to indicate immediate dataSymbol to indicate content of memory locationaddressed by registerShows direction of data flowExchanges contents of dataContents of register, memory location or flagLogical ANDLogical ORExclusive ORNegationContent of flag is set or reset after execution5-24•. MITSUBISHI;"ELECTRIC


MITSUBISHI MICROCOMPUTERSMSL8041A-XXXPSLAVE MICROCOMPUTERDESCRIPTIONThe M5L8041 A-XXXP is a general-purpose, programmableinterface device deisgned for use with a variety of 8-bitmicrocomputer systems. This device is fabricated using N­channel sillicon-gate ED-MOS technology.FEATURES• Mask ROM·· .. ································· 1024-word by 8-bit• Static RAM········································ 64-word by 8-bit• 18 programmable 1/0 pins• Asynchronous data register for interface to master processor• 8-bit CPU, ROM, RAM, 110, timer, clock and low power,stand-by mode• Single 5V supply• <strong>Al</strong>ternative to custom LSI• Interchangeable with i 8041 AAPPLICATION<strong>Al</strong>ternative to custom LSI for peripheral interfacePIN CONFIGURATION (TOP VIEW)TEST PIN 0CLOCK 1 X1 -+ 2CLOCK 2 X 2 -+ 3RESET RESET -+ 4SINGLE STEP S8 -+ 5CHIP SELECT CS -+ 6EXTERNALACCESS (NOTE 1) E~ -+ 7READ R -+ 8ADDRESS Ao -+ 9WRITE W-+ 10SYNCHRS?~~ZAE~ SYNC -+ 11DATA BUSNote 1DOo" 12Outline 40P4Vee (5V)TEST PIN 1INPUT/OUTPUTPORT 127 .. P1 026 Voo (5V) EXTERNAL25 -+ PROG I/OCONTROL!Connect to Vss in the operating condition.INPUT/OUTPUTPORT 2IIBLOCK DIAGRAMINPUT/OUTPUT PORT 2AoRESETSINGLE STEPTEST PIN 0TEST PIN 1READWRITECHIP SELECTADDRESS'-------{7 EA EXTERNAL ACCESS(NOTE1)~ ~ PROG'--v---"'EXTERNAL 1/ o CONTROLCLOCK SYNCHRONIZEDSIGNAL• . MITSUBISHI"ELECTRIC5-25


MITSUBISHI MICROCOMPUTERSMSL8041A-XXXPSLAVE MICROCOMPUTERFUNCTIONThe M5L8041A-XXXP is designed as an ordinary 8-bit CPUperipheral LSI chip and it contains a small stand-alone microcomputer.<strong>Al</strong>though this microcomputer functions independently,when it is used as a peripheral controller, it iscalled the slave microcomputer in contrast to the mastercomputer. These two devices can transfer the data altern a-tively through the buffer register between them. TheM5L8041 A-XXXP contains the buffer register to use this LSIas a slave microcomputer and it can. be accessed in thesame way as other standard peripheral devices. Since theM5L8041 A-XXXP is a complete microcomputer, it is easy todevelop a user-oriented mask-programmed peripheral LSIonly by changing the control software.PIN DESCRIPTIONPinNameVss GroundVee Main power supplyVoo Power supplyToTest pinOX" X2 Crystal inputsRESET Reset- SS Single stepCS Chip select inputEAExternal access- R Read enable signalAoAddress input,-W Write enable signalSYNC Sync signal outputDOo-D0 7 Data busP2o-P2 7 Port 2PROG ProgramPl o -P1 7 Port 1T, Test pin 1Input or output---InputInputInputInputInputInputInputInputInputOutputInput/outputInput/outputOutputInput/outputInputFunctionConnected to a OV supply (ground).Connected to a 5V supply.Connected to a 5V supply.Used as a memory hold when Vcc is cut off.Provides external control of conditional program jumps (JTO/JNTO instructions).An internal clock circuit is provided so that by connecting an RC circuit or crystal to these input pins theclock frequency can be determined. Pins X, and X 2 can also be used to input an external clock signal.CPU initialization input.Used to halt the execution of a command by the CPU, When used in combination with the SYNC signal,the command execution of the CPU can be halted every instruction to enable single step operation.Chip select input data bus control.Normally maintained at OV.Serves as the read signal when the master CPU is accepting data on the data bus from the M5L8041A-XXXP.An address input used to indicate whether the signal on the data bus is data or a command.Serves as the write signal when the master CPU is outputting data from the bus to the M5L8041A-XXXP.Output 1 time for each machine cycle.Three-state, bidirectional data bus. Data bus is used to interface the M5L8041A-XXXP to a master systemdata bus.Ouaisi-bidirectional port. When used as an input port, FF,6 must first be output to this port.After resetting, however, when not used afterwards as an output port, this is not necessary.P2o-P2 3 are used when the M5L8243P I/O port expander is used.Serves as the strobe signal when the M5L8243P I/O expander is used.Ouaisi-bidirectional port. When used as an input port, FF,6 must first be output to this port.After resetting, however, when not used afterwards as an output port, this is not necessary.Provides external control of conditional program jumps (JTl /JNTl instructions).Can serve as the input pin for the event counter (STRT CNT instructions) .5-26• ,MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSMSL8041A-XXXPSLAVE MICROCOMPUTERABSOLUTE MAXIMUM RATINGSSymbol Parameter Conditions Limits UnitVee Supply voltage -0.5-7 VVoo Supply voltage -0.5-7 Vwith respect to VssVIInput voltage-0.5-7 VVo Output voltage -0.5-7 VPd Power dissipation Ta = 25'C 1500 rnWToor Operating temperature rangE! -20-75 ·CTsta Storage temperature range -65-150 ·CRECOMMENDED OPERATING CONDITIONSLimitsSymbol ParameterMin Nom MaxUnitVee Supply voltage 4.5 5 5.5 VVoo Supply voltage 4.5 5 5.5 VVss Supply voltage 0 VV IH High-level input voltage 2 VV IL Low-level input voltage 0.8 Vf(


MITSUBISHI MICROCOMPUTERSMSL8041A-XXXP•TIMING REQUIREMENTS (Ta = -20-75·C, Vee = 5V±10%, unless otherwise noted)DBB Read<strong>Al</strong>ternativeSymbol Parameter Test conditionssymboltc (


MITSUBISHI MICROCOMPUTERSMSL8041A-XXXPSLAVE MICROCOMPUTERTIMING DIAGRAMSReadCS, Ao)tsu (CS-R)tSU(Ao-R),ItW(R)th (R-CS)j~~KtPZX(R-DQ)/htpZX(Ao-DQ) tpzx (CS-DQ)"'~tPXZ(R-DQ)~WriteCS, AoSU(AO-W)tsu (CS-W)tW(W)wtSU(D-W)th(W-D)IIPort 2SYNC___, r----\\'----_-----1/EXPANDERPORT OUT PUTEXPANDERPORTINPU TPROGDMADACKwP2 o -P2 3 DATAP2 o -P2 3 DATA,,tSU(DACK-R)tw(R)Itsu(PC-PR)I th (R- DACK))~tsu (Q PRJPORT CONTROL K. OUTPUT DA~AKI tSU(D-PR)~ ~ th(PR-D)P~RT CONTROL)Ith(PR-PC)tW(PR), I-J~I- INPUT DATA"-,~ (,tsu (DACK- W)I.,th(W-DACK)DRO.--1XtpZX( DACK-DQ)tPHL(R-DRQ)tw(W)t~U(D-W)th(W-~)u~~·tPHL(W-DRQ)• MITSUBISHI"'ELECTRIC5-29


MITSUBISHI MICROCOMPUTE.RSMSL8041A·XXXPSLAVE MICROCOMPUTERTYPICAL CHARACTERISTICSw~~o>I­ ::>a..I­ ::>o...JW~...J±~J:DATA BUS HIGH-LEVELOUTPUT VOLTAGE VS. HIGH-LEVEL.OUTPUT CURRENT3.83.63.43.23.0Vee = 5VTa = 25'C""- ........'-......~ .........-0.2 -0.4 -0.6 -0.8 -1.0~oI >w(!)I­::Jg:::Jo-' wGj-'~9DATA BUS LOW-LEVELOUTPUT VOLTAGEVS. LOW-LEVELOUTPUT CURRENT0.5Vee =5VTa = 25'C0.40.30.2o.1/V//~/-10HIGH-LEVEL OUTPUT CURRENTIOH(mA)LOW-LEVEL OUTPUT CURRENTIOL(mA)w~~o>I­ ::>a..~...JW>W...J~o...J10P 1 • P2 LOW-LEVEL INPUTVOLTAGE VS. LOW-LEVELINPUT CURRENT'"Vee = 5VTa = 25'C"'\~\ \\- 0 . 05 - 0 . 1 - 0 . 15 ~ 0.2 - 0 . 25w(!)~o>I­::Ja..~-' w>w-'~o-'RESET LOW-LEVEL INPUTVOLTAGE VS. LOW-LEVELINPUT CURRENT"Vee =5VTa = 25'C\ ,~\\-0.02 -0.04 -0.06 -0.08 -0.1LOW-LEVEL INPUT CURRENTII(mA)LOW-LEVEL INPUT CURRENTII(mA)NORMARIZED SUPPLY CURRENT (IcC>Q 1.6.2I- Z 1.4wa:a:::>() 1.2~a..a..~ 1.0'"oWN~ 0.8::Ea:VS. AMBIENT TEMPERATUREVee = 5VVoo = 5V~"'- "-.....-oZ 0.6-2525 50 75100"0..EI-ZwII:II:::J()>--'a..a..::J(J)0WNa:


MITSUBISHI MICROCOMPUTERSMSL8041A-XXXPSLAVE MICROCOMPUTERAPPLICATION EXAMPLES(1) Interface with M5L8085APr---r--r--000- DO?8M5L8041A~-xxXP~M5L8085APControlAo- A? 8\t---I----~ r--\~~~"0;;(t---t---(f)m t--- ~g~ aJ~c00 0 '"V8CSAoRW\ 000- DO?Pl~P2~PERIPHERALDEVICESa.--............... I--(2) Interface with MELPS 8-48 Microcomputer and M5L8243P11WPortRWPort.000- DO? 8MELPS8-48MicrocomputerRWCSAo\ 000- DO?PROGP2 o -P2 3M5L8041A-XXXPP2.-P2 744.PROGP4~P2 o -P2 3P5~P6~M5L8243P~P 7-"PERIPHERALDEVICESPl o -P1 78-"ToT,. • MITSUBISHI..... ELECTRIC5-31


MITSUBISHI MICROCOMPUTERSMSL8042-XXXPSLAVE MICROCOMPUTERDESCRIPTION'The M5L8042-XXXP is a general-purpose programmable interfacedevice designed for use with a variety of 8-bit microcomputersystems. The device is fabricated using n­channel silicon-gate EO-MOS technology.FEATURES• Mask ROM .................................... · 2048-word by 8-bit• Static RAM ............................ · ........ "128-word by 8-bit• 18 programmable 1/0 pins• Asynchronous data register for interface to master processor• 8-bit CPU, ROM, RAM, 1/0, tilner, clock and low-powerstand-by mode• Single 5V power supply• <strong>Al</strong>ternative to custom LSI• Interchangeable '!Vith i 8042APPLICATION<strong>Al</strong>ternative to custom LSI for peripheral interfacesPIN CONFIGURATION (TOP VIEW)TEST PIN 0 To~ 1CLOCK 1 X1 ~ 2CLOCK 2 X2~ 3RESET RESET ~ 4SINGLE STEP Ss~ 5CHIP SELECT CS ~ 6EXTERNALACCESS(NOTE 1) E~ ~ 7READ R~ 8ADDRESS Ao ~ 9WRITE W~ 10SYNCHR~I~~~r SYNC +- 11DATA BUSDOo- 1239 +- T1Vee (5V)38 - P2 7 /DACK \37 - P26/DRO ci~~WJ~36 - P2s/lBF PORT 235 - P24/0BFINPUTIOUTPUTPORT 127 - P1 026 Voo (5V)25 ~ PROG ~>gERNALCONTROLINPUTIOUTPUTPORT 2\Outline 40P4Note 1Connect to Vss in the operating condition.BLOCK DIAGRAM/INPUTIOUTPUT PORT 1INPUT/OUTPUT PORT 2P2 4 /0BFP2s/lBFP2 6 /DORC!V""",-,;:c",..k-.;~-;...,r P2 7 /DACK-~voc {5VIRESETAoRESETSINGLE STEPTEST PIN 0TEST 'PIN 1READWRITECHIP SELECTADDRESS'-----...( 7 EA EXTERNAL ACCESS5PR~~ SYNC EXTERNAL 1/0 CONTROLCLOCKSYNCHRONIZEDSIGNAL5-32• MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSMSL8042-XXXPSLAVE MICROCOMPUTERFUNCTIONThe M5L8042-XXXP is designed as an ordinary 8-bit CPUperipheral LSI chip and it contains a small stand-alone microcomputer.<strong>Al</strong>though this microcomputer functions independently,when it is used as a peripheral controller, it iscalled the slave microcomputer in contrast to the mastercomputer. These two devices can transfer the data alternativelythrough the buffer register between them. TheM5L8042-XXXP contains the buffer register to use this LSIas a slave microcomputer and it can be accessed in thesame way as other standard peripheral devices. Since theM5L8042-XXXP is a complete microcomputer, it is easy todevelop a user-oriented mask-programmed peripheral LSIonly by changing the control software.PIN DESCRIPTIONPinNameVss GroundVee Main power supplyVoo Power supplyToTest pin aX 1• X 2 Crystal inputsRESET Reset- SS Single stepCS Chip select inputEAExternal access- R Read enable signalAoAddress inputWWrite enable signalSYNC Sync signal outputDQo-DQ7 Data busP2 0 -P27 Port 2PROG ProgramPl o-P1 7 Port 1T1 Test pin 1Input or output---InputInputInputInputInputInputInputInputInputOutputInput/outputInput/outputOutputInput/outputInputConnected to a av supply (ground).Connected to a 5V supply.Connected to a 5V supply.Used as a memory hold when Vee is cut off.FunctionProvides external control of conditional program jumps (JTO/JNTO instructions).An internal clock circuit is provided so that by connecting an RC circuit or crystal to these input pins. theclock frequency can be determined. Xl and X2 can also be used to input an external clock signal.CPU initialization input.Used to halt the execution of a command by the CPU. When used in combination with the SYNC signal.the command execution of the CPU can be halted every instruction to enable single step operation.Chip select input for data bus control.Normally maintained at av.Serves as the read signal when the master CPU is accepting data on the data bus from the M5L8042-XXXP.An address input used to indicate whether the signal on the data bus is data or a command.Serves as the write signal when the master CPU is outputting data from the bus to the M5L8042-XXXP.Output 1 time for each machine cycle.Three-state. bidirectional data bus. Data bus is used to interface the M5L8042-XXXP to a master systemdata bus.Quasi-bidirectional port. When used as an input port. FF 16 must first be output to this port.After resetting. however. when not used afterwards as an output port. this is not necessary.P2o-P2 3 are used when the M5L8243P I/O expander is used.Serves as the strobe signal when the M5L8243P I/O expander is used.Quasi-bidirectional port. When used as an input port. FF 16 must first be output to this port.After resetting. however. when not used afterwards as an output port. this is n~t necessary.Provides external control of conditional program jumps (JTl /JNTl instructions).Can serve as the input pin for the event counter (STRT CNT instruction).II• MITSUBISHI;"ELECTRIC ..5-33


MITSUBISHI MICROCOMPUTERSMSL8042-XXXPSLAVE MICROCOMPUTERABSOLVTE MAXIMUM RATINGSSymbol Parameter Conditions Limits UnitVee Supply voltage -0.5-7 VVoo Supply voltage -0.5-7 VWith respect to vssVI Input voltage-0.5-7 VVo Output voltage -0.5-7 VPd Power dissipation Ta = 2S'C 1500 rnWToor Operating temperature range 0-70 ·cTsta Storage temperature range -65-150 'cRECOMMENDED OPERATING CONDITIONSLimitsSymbol ParameterMin Nom MaxUnitVee Supply voltage 4.5 5 5.5 VVoo Supply voltage 4.5 5 5.5 VVss Supply voltage 0 VV IH High-level input voltage 2.2 VV IL Low-level input voltage 0.8 Vf(9\) Operating frequency 1 12 MHzELECTRICAL CHARACTERISTICS (Ta =O":"'70'C, Vee =SV±10%, unless otherwise noted)SymbolParameterV IL Low-level input voltageV IH1 High-level input voltage (all except X" X2, RESET)V IH2 High-level input voltage (X" X2, RESET)V OLl Low-level output voltage (000~007)V OL2 Low-level output voltage (Plo~P17' P20~P27, SYNC)V OL3 Low-level output voltage (PROG)V OH1 High-level output voltage (000~007)V OH2 High-level output voltage (all other outputs)IIInput leakage current (To, T" R, W, CS, Ao, EA)lozL High-impedance state output leakage current (000-007)IILl Low-level input load current (Plo~P17' P20~P27)IIL2 Low-level input load current (RESET, SS)100 Supply current from Voolee+loD Total supply currentTest conditionsIOL = 2mAIOL = 1.6mAIOL = lmAIOH = -400J.lAIOH = -SOJ.lAVss ~ V, ~ VccVss+O.4S ~ Vo ~ VeeVIL = O.BVVIL = O.BVLimitsMin Typ MaxUnit-0.5 0.8 V2.2 Vee V3.8 Vee V0.45 V0.45 V0.45 V2;4 V2.4 V-10 10 /-lA-10 10 /-lA-0.5 rnA-0.2 rnA10 rnA145 rnA5-34• MITSUBISHI"'ELECTRIC


MITSUBISHI MICROCOMPUTERSMSL8042·XXXPSLAVE MICROCOMPUTERTIMING REQUIREMENTS (Ta = 0-70'C, Vcc = 5V±10%, unless otherwise noted)DBB Read<strong>Al</strong>ternativeSymbol ParametersymbolTest conditionstc (¢) Cycle time tCYtw (R) Read pulse width tRR Ie (¢) = 1. 25 /-LStsu (CS-R) Chip select setup time before read tARth (R-CS) Chip select hold time after read tRALimitsUnitMin Typ Max1.25 15 f-LS160 nsaansnsDBB Write<strong>Al</strong>ternativeSymbol ParametersymbolTest conditionstw(w) Write pulse width twwtsu (cs-w) -CS, Ao, setup time before writetsu (AO-W)th (W-CS) -CS, Ao, hold time after writeth (W-AO)tsu (OO-W) Data setup time before write towth (W-OO) Data hold time after write twoPort 2<strong>Al</strong>ternativeSymbol Parameter Test conditionssymboltw (PR) PROG pulse width tpptsu (PC-PR) Port control setup time before PROG tcp C L = BOpFth (PR-PC) Port control hold time after PROG tpc CL = 20pFtsu (O-PR) Output data setup time before PROG top C L = BOpFtsu (O-PR) Input data hold time before PROG tpR C L = BOpFth (PR-O) Input data hold time after PROG tpF CL = 20pFDMA<strong>Al</strong>ternativeSymbol ParametersymbolTest conditionstsu (OACK-R) OACK setup time before read tACCth (R-OACK) OACK hold time after read tCACtsu (OACK-W) OACK setup time before write tACCth (W-OACK) OACK hold time after write tCACNote1: Input voltage level V 1L = o. 45V, V 1H = 2, 4V.tAWtWALimitsUnitMin Typ Max160 ns0 ns0 ns130 ns0 nsLimitsUnitMin Typ Max700 ns80 ns60 ns200 ns650 ns0 150 nsLimitsUnitMin Typ Max0 ns0 nsans0 nsIISWITCHING CHARACTERISTICS (Ta = 0-70'C, Vcc = 5V±10%, unless otherwise noted)DBB Read<strong>Al</strong>ternativeSymbol ParametersymbolTest conditionst pzx (CS-OO) Data enable time after CS tAD CL = 100 pFtpzx (AO-OO) Data enable time after address tAD CL = 100 pFt pzx (R-OO) Data enable time after read tRO CL =100pFtpxz (R-OO) Data disable time after read tOFLimitsMin Typ MaxUnit130 ns130 ns130 ns85 nsDMA<strong>Al</strong>ternativeSymbol ParametersymbolTest conditions'tpzx (OACK-OQ) Data enable time after OACK tACO C L = 150 pFtpHL (R-ORO) ORO disable time after read tCROt pHL (W-ORO) ORO disable time after writetCRONote 2Output voltage discriminating levels, low and high, are O. 8V and 2. OV respectively.LimitsUnitMin Typ Max130 ns90 ns90 ns• MITSUBISHI;"ELECTRIC5-35


MITSUBISHI MICROCOMPUTERSMSL8042-XXXPSLAVE MICROCOMPUTERTIMING DIAGRAMSReadCS, Ao)~tsu (CS-R)tSU(Ao-R)tW(R)"tPZX(R-DQ)MtpZX(Ao-DQ) tpzx (CS-DQ)~th (R-CS)J~J(tPXZ(R-DQ)VALID DATA~WritePort 2SYNCEXPANDERPORT OUTP UTEXPANDERPORT INPUTPROGDMAwI----'P2o-P23 DATAP20-P23 DATA,,tsu (DACK-R)tw(R}Itsu(PC-PR),I th(R-DACK)tsu (Q PRJ) RPORT CONTROL OUTPUTlDATA.K'tSU(D-PR)--i ~ th(PR-D)) If '\ PORT CONTROL Jth(PR-PC)tW(PR),:jlf-INPUT DATA~'(, IF-,Itsu (DACK- W) .~th(W-DACK)OROXtpZX( DACK-DQ}JtPHL(R-DRQ}tw(W}IItSU(D-W) thew-D)u~~t PHL( W-DRQ)5-36• MITSUBISHI"ELECTRIC


MITSUBISHI MICROCOMPUTERSMSL8042-XXXPSLAVE MICROCOMPUTERTYPICAL CHARACTERISTICS'>Io>w(!)~...Jo>I­::::>Cl.I­::::>o...JW>W...J:i:(!)IDATA BUS HIGH-LEVELOUTPUT VOLTAGE VS. HIGH-LEVELOUTPUT CU RRENT3.83.63.4323. 0Vee = 5VTa = 25'C"~ ..........~r--- ~8 -2. 0 -0.8 1.0-0.2 -04 -0.6DATA BUS LOW-LEVELOUTPUT VOLTAGE VS. LOW-LEVELOUTPUT CU RRENT~ 0.5S Vee = 5Vo> Ta = 25'Cw 0.4(!)«~o 0.3>I-::::>Cl.~ 02o...JWGj O....J~o...J1 V.,VV/~/10HIGH-LEVEL OUTPUT CURRENTIOH(mA)LOW-LEVEL OUTPUT CURRENTIOL(mA)w(!)~...Jo>I­::::>Cl.~...JW>W...J~o...J3210P 1• P 2 LOW-LEVEL INPUTVOLTAGE VS. LOW-LEVELINPUT CURRENT..........~Vee = 5VTa=25'C'"~"\\.\\- 0 . 05 - 0 . 1 - O. 15 - O. 2 - O. 25~;>w(!)«I- ...J0>I- ::::>Cl.~...JW>W...J~0...J!iRESET 'LOW-LEVEL INPUTVOLTAGE VS. LOW-LEVELINPUT CURRENT"Vee = 5VTa = 25'C~\\~ \-002 -0.04 -0.06 -0.08 -0.1IILOW-LEVEL INPUT CURRENT1,(mA)LOW-LEVEL INPUT CURRENT1,(mA)NORMARIZED SUPPLY CURRENT (IcdVS. AMBIENT TEMPERATUREU 1.6.2 Vee = 5VVoo = 5VI­ZWII:II:::::>()>­...JCl.Cl.::::>enowNa:«~II:oZ1.4'"~0.6-251.21.00.8'" ~~25 50 7510000I-ZwII:II:::::>()>-...JCl.Cl.::::>en0wNa:«~II:0ZNORMARIZED SUPPLY CURRENT (1 00)1 :61.4VS. AMBIENT TEMPERATUREVee = 5VVoo = 5V1.2~ 1.0'" ~~0.8"- 25 25 50 75 100AMBIENT TEMPERATURETaCC)AMBIENT TEMPERATURE T a('C)• MITSUBISHI.... ELECTRIC5-37


MITSUBISHI MICROCOMPUTERSMSL8042-XXXPSLAVE MICROCOMPUTERAPPLICATION EXAMPLES(1) Interface with M5L8085AP .r--r- r--OQo- OQ7A8M5L8042-XXXp~~M5L8085APControlAo- A7 8


LSls FOR PERIPHERAL CIRCUITS


MITSUBISHI MICROCOMPUTERSMS0780SP/MS0781SPMS0782SP/MS0783SPINPUT/OUTPUT EXPANDERDESCRIPTIONThese devices, fabricated using the aluminum gate CMOSprocess and used for input/output port e~pansion, are idealLSls for connection to the single-chip 4-bit microcomputerseries.The M50780SP and M50782SP are housed in a 40-pinplastic mold D I L package wh ile the M50781 SP andM50783SP are housed in a 28-pin plastic mold DILpackage.FEATURES• Wide operating voltage range. . . . . . . . . . .. 3 ~ 14V• Low power dissipation• Interchangeable with TI's TMS1025C and TMS1024C interms of pin connections and electrical characteristics(M50780SP and M50781SP)APPLICATIONI/O expansion for the single-chip microcomputer seriesFUNCTIONM50780SP, M50781 SP, M50782SP and M50783SP areconfigured with 4 or 7 groups of input/output ports, 1group of input/output ports, a port selector circuit andmode control circuit, and operation is possible. in the latchor multiplexer mode.Table 1 ConfigurationsExpander Outline CE pin Requirements for resetCompatibleexpandersMS0780SP 40-pinSO-S2 = low TMS102SCCEMS0781SP 28-pin STD = (t) ,TMS1024CMS0782SP 40-pinSO-S2= lowCEMS0783SP 28-pin STD = highPIN CONFIGURATIONS (TOP VIEW)VooINPUT/OUTPUT { Rz ....PORT R R3_(Note 1)CHIP ENABLE INPUT CE - + 4MODE SELECT INPUT M5 -+STROBE 1~~0~ 5TD-+INPUT/{ :;~: :OUTPUTPORT 1 P 1z .... 9P13 .... 10INPUT/{::~: :~~~~~U~ P4Z _ 13. P43 .... 14INPUT/{ ::~: ::~~~TU~ P 2 .-. 17P53·+ 18INPUT/{PZO.-+ 190p~T:~i P Z1 _ 20 --,, _____ ....r-Note 1: M50782SP has a CE pin.VooINPUT/{ROUTPUT 2_ 2PORT R R 3_ 3(Note 2)CHIP ENABLE INPUTCE-+ 4MODE SELECT INPUTM5-+ 5STRO~~~;;~{S:;::~ ~P43 .... 10INPUT/{::~.: :~Outline 40P4B28 _R1}INPUTI27 _ R 0 ~~~~U~Vss25 +-- 5Z} INPUT20 +-- 51 SELECT23 +-- 50 PORT:: : :::} INPUT/20 .... P71 ~~~~UJ19 .... P70:: ::::}INPUTI~~~~U~ P5Z- 13 16 -P61 ~~~~U~P53 - .... 14-L.._---,. __ ~--"'5 -P60Outline 28P4BIINote 2: M50783SP has a CE pin.• MITSUBISHI.... ELECTRIC·6-3


MITSUBISHI MICROCOMPUTERSMS0780SP/MS0781SPMS0782SP/MS0783SPINPUT/OUTPUT EXPANDERTable 2 Pin DescriptionM5SymbolSTDNameMode select inputStrobe inputLatch mode at high; multiplexer mode at low.FunctionThis input is valid in latch mode and data latched by the fall (t) are output to output port.Input data are read into latch at high level. At low level latch data are output.CE (CE)Ao-A3Chip enable inputInput/output portThis input is valid in multiplexer mode.4-bit bidirectional input/output ports. Input in latch mode; output in multiplexer mode.Pl0- P 13 Input/output ports 1-7P20- P 23P30- P 33P40- P 43PSO-PS3P60- P 63P10- P 734-bit bidirectional input/output ports. Output in latch mode; input in multiplexer mode.M50780SP.. M50781 SPTable 3 Latch ModesInputM5 CE 5TD SO-52 Ao-A3H X ! nH X ! nH X L O,nH X H O,nH X !°L L X O,nHLXXXXLatchTable 4 Multiplexer ModesOutput Input Outputo (PnO, P n1. P n2, P n3) MS CE 5TD SO-52 P nO-Pn3 o (Ao, AI, A2, A3)H H (PnO-Pn3) L L X O,n X ZL L (PnO-Pn3) L H X n H H00 00 (<strong>Al</strong>l ports) L H X n L L00 OO(AII ports) L X X°X ZL L (<strong>Al</strong>l ports)00 Z (<strong>Al</strong>l ports)M50782SP.. M50783SPTable 5 Latch ModesTable6 Multiplexer ModesInputM5 CE STD SO-52 Ao-A3H X H n HH X H n LH X ! n HH X ! n LH X L O,n XH X HX°L H L n XLatchOutput Input Outputo (PnO, P n 1, P n2, P n3) M5 CE 5TD SO-52 P nO-Pn3 o (Ao, AI, A2, A3)-* H (PnO-Pn3) L H X O,n X Z-* L (PnO-Pn3) L L X n H HH H (PnO-Pn3) L L X n L LL L (PnO- P n3) L X XXZ°00 00 (<strong>Al</strong>l ports)-* L (<strong>Al</strong>l ports)00 Z (<strong>Al</strong>l ports)X : High or low* Not latchedZ : High-impedance state6-4•. MITSUBISHI..... ELECTRIC


MITSUBISHI MICROCOMPUTERSMS0780SP/MS0781SPMS0782SP/MS0783SPINPUT/OUTPUT EXPANDERBLOCK DIAGRAMSM50780SP(Note 11CEMSSTDPORT R~R3 R2 Rl ROVDD VSS>--------~LATCHLATCHLATCHLATCHLATCHLATCHLATCHPORTBUFFERPORTBUFFERPORTBUFFERPORTBUFFERPORTBUFFERPORTBUFFERPORTBUFFERP13 Pn Pl1 Pl0 PS3 PS2 PSI Pro PI3 PI2 PII PIO P43 P42 P41 P40 P33 Pn P31 P30 P23 P22 P21 P20 P13 PI2 PII PIO~ '--y-------' '---------y----'-----y-----"'----y------''--y-----' ~PORT 7 PORT 6 PORT 5 PORT 4 PORT 3 PORT 2 PORT 1M50781SPNote 1: M50782SP has a IT pin.(Note 21CE MS STDVoo VSS~-01IILATCHLATCHLATCHLATCH---------------- --------------PORTBUFFERPORTBUFFERPORTBUFFERPORTBUFFERJIP13 Pn Pl1 Pl0~PORT 7PS3 PS2 PSI Pro PI3 PI2 PII PIO'---y-----'PORT 6 PORT 5'-----v----'P43 P42 P41 P40'-y---"PORT 4Note 2: M50783SP has a IT pin.• MITSUBISHI;"ELECTRIC6-5


MITSUBISHI MICROCOMPUTERSMS0780SP/MS0781SPMS0782SP IMS0783SP-i',INPUT/OUTPUT EXPANDERTable 7 Function Table--------------MS07805P, MS07825PMS07815P, MS07835Pn 52 51 50 P10-P13 P20- P 23 P30-P33 P40- P 43 PSO-PS3 PSO-P631 L L H 02 L H L 03 L H H 04 H L L 05 H L H a6 H H L 07 H H' HP70- P 730ABSOLUTE MAXIMUM RATINGSSymbol Parameter ConditionsVOO Supply voltage With respect to V ssVIInput voltageVo Output voltagePd Maximum power dissipation Ta =2S·CTopr Operating free-air temperature rangeTstg Storage temperature rangeLimitsUnit-0,3-15 VVss-0.3 -Voo+0.3 VVSS-0.3- Voo+0.3 V600 mW-10-70 ·C-40-125 ·CRECOMMENDED OPERATING CONDITIONSLimitsSymbol ParameterMin Nom MaxUnitVoo Supply voltage 3 14 VVI Input voltage 0 Voo VVIH High-level input voltage Voo XO.7 Voo VVIL Low·level input voltage 0 VooxO.3 VELECTRICAL CHARACTERISTICS (Ta=2S·C, Voo=9V, unlessotherwisenoted)SymbolParameterPort 1 - port 7VOH High·level output voltagePort RPort 1 - port 7VOLl Low-level output voltagePort RVOL2 Low-level output voltage Port 1 - port 7Port 1 - port 7III nput currentPort RIDoSupply currentTest conditionsVoo= 5 V, IOH= -2mA,Voo= 9 V, IOH=-4mAVoo=12V, IOH= .,.-S.SmAVoo= 5 V, IOH=-200,uAVoo= 9 V, IOH=-350,uAVoo=12V, IOH=-4S0,uAVoo= 5 V, IOL = 1mAVoo= 9 V, IOL = 1.4mAVoo=12V, IOL"'" 1.7mAVoo= 5 V. IOL=250,uAVoo= 9 V, IOL=450,uAVoo=12V, IOL=SSO,uAVoo=SV, IOL=4mAVoo=9V, IOL =12mAVoo=12V, IOL=17mAVI=O-VOOVI=O-VOOOutput pins openLimitsUnitMin Typ Max2.5 V6.5 V9.5 V4,6 V8_6 V11.6 V0.4 V0.4 V0.4 V0.4 V0.4 V0.4 V1.8 V2,5 V3.9 V10 I-lA1 I-lA50 ,uA6-6• MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSMS0780SP/MS0781SPMS0782SP IMS0783SPINPUT/OUTPUT EXPANDERTIMING REQUIREMENTSLimitsSymbol Parameter Test conditions UnitMin Typ MaxVoo= 5 V0.2tsu (R-STO) Data set-up time for STD input, port R input VOO= 9 V0.15 /-isVoo=12V0.1 l'VOO= 5 V1tsu (S-STO) Data set·up time for STD input, So - S2 inputs VOO= 9 VVoo=12VVoo= 5 V0.50.20.5/-istw STD input pulse width VOO= 9 VVoo=12VVoo= 5 V0.40.30.4/-isth (R-STO) Data hold time for STD input, port R input VOO= 9 VVoo=12VVoo= 5 V0.30.21/-isth (S-STD) Data hold time for STD input, SO-S2 inputs VOO= 9 VVoo=12V0.70.5/-isSWITCHING CHARACTERISTICSSymbolParameterTest conditionsLimitsMin Typ MaxUnitVOO= 5 V0.6t PZX(CE-P)tpZX(MS-P)Valid output delay time for CE input, R outputValid output de~ay time for MS input, PIO-P73outputsRL = 10kQVoo= 9 VVoo=12VVoo= 5 VVoo= 9 VVoO=12V0.5 /-is0.40.80.6 /-is0.5IICL=50pFVoo= 5 V0.6t PXZ(CE-R)Output floating delay time for CE input, R outputVoo= 9 V0.5 /-isVOO=12V0.4Voo= 5 V0.8t PXZ(MS-P)Output floating delay time for MS input, PIO -P 73outputsVoo= 9 V0.6 /-isVoo=12V0.5Voo= 5 V3t PHL(S-R)Data output high-to-Iow delay time; S input. R outputVoo= 9 V1 /-isVoo=12V0.7t PHL(P-R)Data output high-to-Iow delay time; PIO -1'73 inputs.R outputVoo= 5 VVOO= 9 VVoo=12V1.80.7 /-is0.5tPHL(SFO-P)Data output high-ta-Iow delay time; STD input,P outputRL =200kQVoo= 5 VVOO= 9 VVOO=12V1.20.5 /-is0.4CL=50pFVoo= 5 V3tPLH(S-R)Data output low-ta-high delay time; S input, R outputVoo= 9 V1 /-isVoo=12V0.7tpLH(P:R)Data output low-to-high delay time; PIO-P73 inputs,R outputVoo= 5 VVOO= 9 VVoo=12V1.80.7 /-is0.5)tPL~(STD-P)Data output low-to-high delay time; STD input,PIO "-P 73 outputsVoo= 5 VVOO= 9 VVOO=12V1.20.5 /-is0.4.•. MITSUBISHI.... ELECTRIC6-7


MITSUBISHI MICROCOMPUTERSMS0780SP/MS0781SPMS0782SP IMS0783SPINPUT/OUTPUT EXPANDERTIMING DIAGRAMMultiplex ModeMSOE(Note 1)INPUT(P)OUTPUT(R)tPZX(CE-A)tPHL(S-A)tPLH(S-A)tPHL(P-A)tPLH(P-A)tPXZ(CE-A)Latch ModeMS.,.1('~~os------------------------------------~~ :x:INPUT(R)~~tsu (A-STD)~tsu (S-STD)th (A-STO)th(S-STO)"KSTDOUTPUT(P)tPZX(MS-P) ~t PHL(STO-P)(Note 3)-t PLH( STOop)"""7 1 ~~~ /1~(MS~P)Note 1: M50782SP and M50783SP have a IT pin.2: For M50780SP and M50781SP3: For M50782SP and M50783SP6-8 . 'MITSUBISHI.... ELECTRIC


•MITSUBISHI MICROCOMPUTERSMS0784SPINPUT EXPANDERDESCRIPTIONThis device, fabricated using the aluminum gate CMOSprocess and used for input port expansion, is an ideal LSIfor connection to the single-chip 4-bit microcomputerseries.It is housed in a 28-pin plastic mold 01 L package.FEATURES• Wide operating voltage range . ............ (4'" 14V)• Low power d[ssipationAPPLICATIONInput port expansion in the single-chip microcomputerseriesFUNCTIONM50784SP comprises 4 groups of input ports, 1 group ofoutput ports and a port selector circuit.It is particularly attractive for implementing a multiplexer.PIN CONFIGURATION (TOP VIEW)VDD •R2_ 2OUTPUT PORT R { R _ 33CHIP ENABLE CE _ 4NC- SINPUT PORT 5{::~: ::PS2-' 3PS3 _+_14"'--____ ~Outline 28P4B28 ..... Ril27 _+ R 0 f OUTPUT PORT RVss:: ::2} PORT23 -soSE LECT1 INPUT:: := :::} INPUT PORT 7'9 -P70'8 -P6317 -P62INPUT PORT 6IIBLOCK DIAGRAMCHIP ENABLECECHIP SELECTINPUT~S2 S, SoPORT R~R3 R2R, Ro VDD Vss.-------L-----,-~IP 13 P71 P71 P70'------y------'PORT 7P63 P62 P61 P60~PORT 6PS3 P 52 PS1 Pso~PORT 5P43 P42 P 41 P 40~PORT 4• MITSUBISHI.... ELECTRIC·6-9


MITSUBISHI MICROCOMPUTERSMS0784SPINPUT EXPANDERPIN DESCRIPTIONSymbolNameFunctionCEP40- P43PSO-PS3PSO-PS3P70- P73Chip enable inputOutput portInput ports 4 - 7When low, output transistors will be "off" state:4-bit output ports. P-channel open drain outputs.4-bit input portsFunction table (1), Function table (2)InputOutputn 52 5,SoP40- P 43 PSO-PS3 PSO-PS3 P70-P73CE So-52 P nO-Pn3 Q (AO, AI> R2, A3)L 0, n X(L)H n HHH n L(L)4 H LS H L6 H H7 H HLH'LH0000X 0 X(L)(L) : Transistor "off" stateX: High or lowABSOLUTE MAXIMUM RATINGSSymbolParameterConditionsLimitsUnitVOOSupply voltageWith respect to VSS-0_3-1SVVIInput voltageVsS-0.3- V OO+0.3VVoOutput voltageVsS-0.3- V oO+0.3VPdMaximum power dissipationTa =2S·C600 mWToprOperating free-air temperature range-10-70 ·CTstgStorage temperature range-40-12S ·CRECOMMENDED OPERATING CONDITIONSSymbolParameterLimitsMin Nom MaxUnitVOO Supply voltage 4 14VI Input voltage 0 VooVIH High-level input voltage VooXO.7 VOOVIL Low-level input voltage 0 VooXO.3VVVVELECTRICAL CHARACTERISTICS (Ta=2S·C, Voo=9V, unless otherwise noted)SymbolParameterTest conditionLimitsMin Typ MaxUnitIOHHigh-level output currentPort RVOO=SV, VOH=3_SVVoo=9V, VOH=7 _SV1.S rnA2.S rnAVoo=12V, Vow=10.SV3_SrnAIIInput currentPort 4 - Port 7VI=O-VOO1 I1AJOOSupply currentOutput pins openSOI1A6"':"'10• ..MITSUBISHI.... ELECTRI,C


MITSUBISHI MICROCOMPUTERSMS0786SPINPUT/OUTPUT EXPANDERDESCRIPTIONThe M50786SP is an input/output expander fabricated usingaluminum-gate CMOS technology. It is designed especiallyfor connection with the single-chip 4-bit microcomputer series,and it comes in a 40-pin plastic molded DI L package.FEATURES• Wide operating voltage range .................. ·; .... · .. 4-14V• Low power dissipationAPPLICATIONI/O expansion for the single-chip 4-bit microcomputer seriesFUNCTIONThe M50786S~ is composed of seven groups of I/O ports,one I/O port group, a port selector circuit and a mode controlcircuit. It can be used in the latch or multiplexer mode.P-channel open-drain output buffers are featured.PIN CONFIGURATION (TOP VIEW)(4-14V) Vee 140 - R1 } INPUT/OUTPUTP1 3 - 10 31 - P3 0INPUT/OUTPUT { R2 - 239 _ Ro PORT RPORT R R _ 3CHIP ENABLE CE 3 Vss (OV)4INPUT -+MODE Sl~Ep~\ MS -+ 5STROBE DATA STD -+ 6INPUT {P1 0- 734_P3 3 }INPUT/OUTPUT P1 1 - 833 - P32 INPUT/OUTPUTPORT 1 P1 2 - 932 _ P3 1PORT 3P40 - 11 30 - P7 3 }INPUT/OUTPUT P41 - 12 29 - P72 INPUT/OUTPUTPORT 4 P4 _{ 213 28 _ P7 1PORT 7P4 3 - 14 27 - P70P50- 15 26 - P6 3 }INPUT/OUTPUT P51 - 16 25 - P62 ~Ncf~i~OUTPUTPORT 5 P5{ 2_ 17 24 - P6 1P53 - 18 23 - P60INPUT/OUTPUT {P20 - 19 22 - P2 3 } INPUT/OUTPUTPORT 2 P2 1 - _20 _____ ---1-21 - P2 2 PORT 2Outline 40P4BBLOCK DIAGRAMCHIP MODE STROBE PORTENABLE SELECT DATA SELECTINPUT INPUT INPUT ~-I(4-14V)(OViCE MS STD S2 8 1 SoVee VssIILATCHLATCHLATCHLATCHLATCHLATCHLATCHPORTBUFFERPORTBUFFERPORTBUFFERPORTBUFFERPORTBUFFERPORTBUFFERPORTBUFFER• MITSUBISHI.... ELECTRIC6-11


MITSUBISHI MICROCOMPUTERSMS0786SPINPUT /OUTPUT EXPANDERPIN DESCRIPTIONSymbol Name FunctionM5 Mode select Input Latch mode when high; multiplexer mode when low.5TDStrobe inputCE Chip enable Input Input Is valid in multiplexer mode.Valid in latch mode; data latched by fall (t) are supplied to output port.When high, input data are read into latch; when low, latch data are output.Ro-R3 Input/output port 4-bit bidirectional Input/output port. Functions as input in latch mode and output in multiplexer mode.Pl o-P1 3P20-P23P30-P33P40-P43 Input/output port 1-7 4-bit bidirectional input/output ports that function as output In latch mode and input in multiplexer mode.P50-P53P60-P63P70-P73LATCH MODEMULTIPLEXER MODEInputlatchOutput Input OutputM5 CE 5TD So-52 Ro-R3 o (Pno, Pn1, Pn2, Pn3) M5 CE 5TD So-52 PnO-Pn3 o (Ro, R1, R2, R3)H X H nH X H nH X + nH X + nH X L 0, nH X H 0L H L nH -* H (PnO-Pn3) L H XL -* (L) (PnO-Pn3) L L XH H H (PnO-Pn3) L L XL L (L) (PnO-Pn3) L X XX 0 0 0 0 (all ports)X-*(L) (all ports)X 0 0 (L) (all ports)* Not latched0, n X Zn H Hn L L°XX : IrrelevantZ : High impedance(L): Output transistor off-stateZFUNCTION TABLEn 52 51 501 L L H2 L H L3 L H H4 H L L5 H L H6 H H L7 H H HP1 0 -P130P20-P23 P30-P33 P4 0 -P43000P5 0 -P53 P6 0 -P63 P7 0 -P730006-12.MITSUBISHI..... ELECTRIC


MITSUBISHI MICROCOMPUTERSMS0786SPINPUT/OUTPUT EXPANDERABSOLUTE MAXIMUM RATINGSSymbol Parameter Conditions Limits UnitVoo Supply voltage With respect to Vss -0.3-15 VVI Input voltage Vss -0. 3-Voo +0.3 VVo Output voltage Vss -0. 3-Voo +0.3 VPd Power dissipation Ta = 25"C 600 mWTopr Operating temperature -10-70 'cTsm Storage temperature -40-125 'cRECOMMENDED OPERATING CONDITIONSLimitsSymbol ParameterMin Nom MaxUnitVoo Supply voltage 4 14 VVI Input voltage 0 Voo VV IH High-level input voltage VooXO.7 Voo VV IL Low-level input voltage 0 VooXO.3 VELECTRICAL CHARACTERISTICS (Voo = 9V, Ta = 25'C, unless otherwise noted)SymbolParameterTest conditionsLimitsMin Typ MaxUnitVOHHigh-level output voltagePorts 1-7Port RVoo = 5V, IOH = -lmAVoo = 9V, IOH = -3mAVoo = 12V, IOH = -5. 5mAVoo = 5V, IOH = -100,uAVoo = 9V, IOH = -250,uA2.5 V6.5 V9.5 V4.6 V8.6 VIIVoo = 12V, IOH = -450,uA11.6 VVoo = 5V, IOL = 130,uA0.4 VVOL Low-level output voltage Port RVoo = 9V, IOL = 350,uA0.4 VVoo = 12V, IOL = 550,uA0.4 VIIInput currentPorts 1-7Except ports 1-7VI = O-VooVI = O-Voo10 /-LA1 /-LA100 Supply currentOutput pins open50 /-LA• MITSUBISHI.... ELECTRIC6-13


MITSUBISHI MICROCOMPUTERSMS0786SPINPUT /OUTPUT EXPANDERTIMING REQUIREMENTSSymbolt8U (R-STO)t8U (S-STO)twth (R-STO)th (S-STO)ParameterData setup time for STD input,port R inputData setup time for STD Input,inputs So-S2STD input pulse widthData hold time for STD input,port R inputData hold time for STD input,port S inputTest conditionsVoo= 5VVoo = 9VVoo = 12VVoo = 5VVoo = 9VVoo= 12VVoo= 5VVoo= 9VVoo = 12VVoo = 5VVoo = 9VVoo= 12VVoo= 5VVoo= 9VVoo = 12VMin0.40.40.410.70.51.50.5 .0.30.50.50.510.70.5LimitsTypMaxUnit/.1.8/.1.8/.1.8/.1.8/.1.8SWITCHING CHARACTERISTICSSymboltpzx (CE-R)t pzx (MS-P)t pxz (CE-R)t pxz (MS-P).I'tpHL (S-R)t pHL (P-R)t pHL (STO-P)t pLH (S-R)t pLH (P-R)t pLH (STO-P)ParameterValid output delay time for CE input,R outputValid output delay time ~or MS input,P1o-P73 outputOutput floating delay time for CE input,R outputOutput floating delay time for MS input,P1o-P73 outputData output high-to-Iow delay time,S input, R outputData output high-to-Iow delay time,P1o-P73 input, R outputData output low-to-high delay time,STD input, R outputData output low-to-high delay time,S input, R outputData output low-to-high delay time,P1o-P73 input, R outputData output low-to-high delay time,STD input, P1o-P73 outputTest conditionsVoo = 5VRL = 10kOVoo= 9VCL = 50pFVoo = 12VVoo = 5VRL = 2kOVoo = 9VCL = 50pFVoo = 12VVoo = 5VRL = 10kOVoo = 9VCL = 50pFVoo= 12VVoo = 5VRL = 2kOVoo = 9VCL = 50pFVoo = 12VVoo= 5VVoo = 9VRL = 200kOVoo = 12VVoo = 5VCL = 50pFVoo = 9VVoo = 12VVoo= 5VRL = 2kOVoo = 9VCL = 50pFVoo = 12VVoo = 5VVoo= 9VRL = 200kOVoo = 12VVoo = 5VCL = 50pFVoo = 9VVoo = 12VVoo = 5VRL = 2kOVoo= 9VCL = 50pFVoo = 12VMinLimitsTypUnitMax1.51 /.1.50.82.41.8 /.1.81.21.51 /.1.$0.82.41.8 /.1.$1.21.22.5 /.1.$23.51.8 /.1.$1.22.41.8 /.1.$1.24.22.5 /.1.$23.51.8 /.1.81.22.81.8 /.1.$1.2\6-14• MITSUBISH. I.... ELECTRIC


MITSUBISHI MICROCOMPUTERSMS0786SPINPUT/OUTPUT EXPANDERTIMING DIAGRAMMultiplexer ModeMSCES2- S 0Input (p)Output (R)tPZX(CE-R)tpHL(S-Fl)tPLH(S-R)tPHL(P-R)tPLH(P-R)tPXZ(CE-R)Latch ModeMSCE~{"\ Ir----------------------- ~--------.IIS2-S0~~~IKInput (R)~~ -~tsu (R-STD)I-tsu (S-STD)th (R-STD)th (S-STD)STD., ;- _r~twOutput (p)tPZX(MS-P)I--.31 __tPLH(STD-P)JIXI~(M'P)/1•. MITSUBISHI.... ELECTRIC6-15


MITSUBISHI MICROCOMPUTERSMS0790SPINPUT /OUTPUT EXPANDEftDESCRIPTIONThe M50790SP is an input/output expander LSI fabricatedusing aluminum-gate CMOS technology. It is designedespecially for connection with the single-chip 8-bit microcomputerseries, and it comes in a 52-pin shrink plasticmolded OIL package.FEATURES• Wide operating voltage range .......................... · 4-14V• Voltage levelconvertable thanks to n-channel opendrainconfiguration at 1/0 port (port R)• Input/output ports (ports P45-P49) ............... 4 bits X 5• .Output ports {ports P40-P44) ....................... 4 bits X 5• Hig'h current output• Output latch data can be read• Input/output setting possible for each bit individuallywith 20bits 1/0 portsPIN CONFIGURATION (TOP' VIEW)(4-14V) VooIP47o- 5INPUT/OUTPUT P47 1 -PORT P47 P472-P473-RESET INPUTCHIP ENABLEINPUTREAD/WRITE R/W -+ 11CONTROL INPUTCLOCK INPUTINP~T/OUTPUT IPORT RNC INPUT/51 .. P46 0 OUTPUT50 .. P453 I PORT P4649 - P452 INPUT/OUTPUT48 - P451 PORT P4547 - P450APPLICATION1/0 expansion for single-chip 8-bit microcomputer M50740-XXXSPOUTPUTPORT P44Outline 52P4B34 -+ P40 3 133 -+ P402 OUTPUT32 -+ P40 1PORT P4031 -+ P40 030 - P49 ! 3 INPUT/29 - P49 2 OUTPUT28 _ P49 PORT P491( Vss (OV)CHIPR/WBLOCK DIAGRAM ENABLE CONTROLINPUT INPUT .RESET INPUT RES CE R/W t/> CL9~~UTIIPOf!T R(4-14V) (OV)Ro R1 R2 R3 Voo Vss-------0--€r----,I24 23 22 21 - 8 7 6 5 - 4 3 2 51P483 P481 P473 P471 P463 P461\ P48~ P480, \ P47~ P470 , ~PORT P48 PORT P47 PORT P466-16 .• MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSMS0790SPINPUT/OUTPUT EXPANDERFUNCTIONThe M50790SP enables expansion from one 4-bit I/O port(port R) group to five 4-bit output port groups and five 4-bitI/O port (port p) groups. The ports are selected as follows:when the clock input ,p is high, the address is input fromport R and when it is low, the data are input (or output) bythe same port (port R).Each I/O port (ports P45 - P49) has a direction register(045-049) and the input or output can be set for each bitindividually.The contents of all output latches can be read from port R.PIN DESCRIPTIONSymbol Name Input or output Function¢ Clock input In-CEChip enable inputInWhen the input is high, the address of the port to be accessed from port R is designated. The addressis latched at the rf> fall. Conversely, when the input is low, the R port data are input or output.If this input is high when rf> is high, the internal mode is prevented from being changed by externalequipment.R/W Read/write control input In The port R input/output is controlled by the high/low level of this input when rf> is falling.<strong>Al</strong>i the outputs are put into the high-impedance state when this input is low. This means that the open---RES Reset input In drain output port latches and direction registers are reset. The CMOS input/output port data latches remainunchanged (see table below).Data is sent and received at this 4-bit bidirectional port by the microcomputer's transfer instrucitons.R Port R In/out When rf> is high, the address is read through this port; when low, the data are sent or received throughthis port.P40 Output ports 40P41 Output ports 41These 4-bit output ports have output latches for each individual bit. The output configuration is n-channelP42 Output ports 42 Outopen-drains for P40i-P43i and p-channel open-drains for P44i.P43 Output ports 43P44 Output ports 44P45 Input/output ports 45P46 Input/output ports 46 These 4-bit bidirectional input/output ports have an output latch and direction register for each individualP47 Input/output ports 47 In/out bit and input or output can be designated for each bit. The output configuration is a 3-state CMOS struc-P48 Input/output ports 48 ture.P49 Input/output ports 49IIPORT MODES AFTER RESET INPUTPort Direction registerP40-P43 -P44 -P45-P49ALL low(input)Data latchALL "H"ALL "L"No changeOutput transistorN-channel open-drainOFFP-channel open-drainOFFHigh-impedance• MITSUBISHI"ELECTRIC6-17


MITSUBISHI MICROCOMPUTERSMS0790SPINPUT/OUTPUT EXPANDEROPERATIONAddress DesignationThe address is designated by port R while the clock if>signal is high and the address data are latched to theaddress latch by the if> fall (t). The relationship betweeneach port or address register and the addresses is shownbelow.Output OperationOutput Ports (P40-P44)In order for 1he data to be output to the P40 - P44 outputports, the' address must be designated from port R when if>is high. When if> .is low, the output data must be designatedin the, same way from port R. In this case, the R/Winput isset low with the if> fall ( t ).Input/Output Ports (P45-P49)Address and data signsIn the case of the 1/0 ports the direction register correspondingAddress (¢> = high)Data(¢>=low)to the bits must be set high beforehand. As long asR3 R2 R, Ro R3 R2 R, Ro the level is high, the output operation can be conducted inL L L L blankexactly the same way as for the P40-P44 ports.L L L H P40 3 P40 2 P40, P40 0L L H L P41 3 P41 2 P41, P41 0Input OperationL L H H P42 3 P42 2 P42, P42 0For input the direciton register corresponding to the bitsL H L L P43 3 P43 2 P43, P43 0must be set low beforehand. The actual operation consistsL H L H P44 3 P44 2 P44, P44 0in designating the input port address from port R when theL H H L P45 3 P45 2 P45, P45 0if> input is high and reading the R port data when if> is low. InL H H H 045 3 045 2 045, 045 0H L L L P46 3 P46 2 P46, P46this case, the R/W input is set high with the if> fall (t ).0H L L H 046 3 046 2 046, 046 0H L H L P47 3 P47 2 P47, P47 0 Latch Read OperationH L H H 047 3 047 2 047, 047 0H H L L P48 3 P48 2 P48, P48 0 Output Ports (P40...,:·P44)H H L H 048 3 048 2 048, 048 0 In order to read the P40-P44 output port latches, the P40-H H H L P49 3 P49 2 P49, P49 0 P44 port address is deSignated wh,en the if> input is highH H H H 049 3 049 2 049, 049 0and, as soon as R/W is high during the if> fall, the data canNote: 045-049 are the direction registers of ports P45-49. When 0 islow, the output is set to the high-impedance state and whenbe read from port R when if> is low.high, the CMOS output ON state is established. Designation foreach bit in this way is possible: The contents of the directionregisters, however, cannot be read out.1/0 Ports (P45-P49)In order to read the 1/0 port latches, the direction registercorresponding to the bits must be set high beforehand.Direction Register Setting(This sets the CMOS outputs ON,.) If the direction registerFor each bit the input/output ports have correspondingis high, then the latch reading operation can be conducteddirection registers (see table below). When a register isin exactly the same way as with the P40-P44 ports.low, the output is set to the high-impedance state andwhen high, the CMOS output ON mode is established.Direction Registers (045-049)The contents of the direction registers cannot be read out.Correspondence between1/0 ports and direction registersOutput port/input portDirection registerP40 0 P40, P40 2 P40 3P41 0 P41, P41 2 P41 3NoneP42 0 P42, P42 2 P42 3(Outputs only)P43 0 P43, P43 2 P43 3P44 0 P44, P44 2 P44 3P45 0 P45, P45 2 P45 3 045 0 045, 045 2 045 3P46 0 P46, P46 2 P46 3 046 0 046, 046 2 046 3P47 0 P47, P47 2 P47 3 047 0 047, 047 2 0473P48 0 P48, P48 2 P48 3 048 0 048, 048 2 048 36-18 ., ' MITSUBISHI""ELECTRIC


MITSUBISHI MICROCOMPUTERSMS0790SPINPUT !OUTPUT EXPANDERABSOLUTE MAXIMUM RATINGSSymbol Parameter Conditions Limits UnitVoo Supply voltage -0.3-15 VVI Input voltage With respect to Vss Vss-O. 3-Voo+0. 3 VVo Output voltage Vss-O. 3-Voo+0. 3 VPd Power dissipation Ta = 25'C 600 rnWTopr Operating temperature -10-70' 'cTstg Storage temperature -40-125 'cRECOMMENDED OPERATING CONDITIONS (Voo = 9V±10%, Ta = -10-70'C, unless otherwise noted)Symbol Parameter Test conditionsVoo Supply voltage 4VI Input voltage aV IHP High-level input voltage, P45, P46, P47, P48, P49 Voo = 7-l4V VooXO.7V ILP Low-level input voltage, P45, P46, P47, P48, P49 Voo = 7-l4V aV IHR High-level input voltage, R, t/>, R/W, CE, RES Voo = 7-l4V VooXO.4V ILR Low-level input voltage, R, t/>, R/W, CE, RES Voo= 7-l4V aIOL


MITSUBISHI MICROCOMPUTERSMS0790SPINPUT/OUTPUT EXPANDERTIMINGREQUIREMENTS (Ta = -lO-70·C, Voo±lO%, unless otherwise noted)SymboltSU(A-~)tsu(o-~)th(-A)th(-o)tsU(CE-~)th(-CE)tSU(R/W-~)th(-R/W)tSU(p-~)th(-p)tW(RES)ParameterAddress input set-up timeData input set-up timeAddress hold time after'" fallData hold time after '" riseChip enable set-up time before'" fallChip enable hold time after'" fallRead/write set-up time before '" fallRead/write hold time after'" fallP input set-up time before'" fallP input data hold time after'" riseReset pulse widthTest conditionsVee = 9VVoo = 12VVoo = 9VVoo = 12VVoo= 9VVoo = 12VVoo = 9VVoo = 12VVoo = 9VVoo = 12VVoo = 9VVoo = 12VVoo = 9VVoo = 12VVoo= 9VVoo = 12VVoo= 9Vvoo= 12VVoo = 9VVoo= 12VVoo= 9VVoo = 12VLimitsUnitMin Typ Max750 ns600 ns700 ns550 ns0 ns'0 nsans0 ns550 ns400 ns400 ns300 ns650 ns500 ns400 ns300 ns750 ns600 ns300 ns200 ns400 ns300 ns6-20• MITSUBISHI"ELECTRIC·


MITSUBISHI MICROCOMPUTERSMS0790SPINPUT/OUTPUT EXPANDERSWITCHING CHARACTERISTICS (Ta = -1O-70·C, Voo±10%, unless otherwise noted)NoteSymbol Parameter Test conditions(During output)t p (oI-P)(During input)tPXL


MITSUBISHI MICROCOMPUTERSMS0790SPINPUT/OUTPUT EXPANDERTIMING DIAGRAM (With reference voltage of 0.9 X Voo for high level and 0.1 X Voo for low level)For R/W, CE, t/> and RES, Ro-R 3 , high level is 0.9 X Vee and low level is 0.1 X Vee.During outputAddressCE-----_tsU(R!W-~)th(~-R!W)R/W-----_P (output) __________...;...___________ ~ ___________During inputRo-R 3-----


MITSUBISHI MICROCOMPUTERSMS0790SPINPUT/OUTPUT EXPANDERDuring direction register changingRO-3----------~~ ______ ....... JrAddressCER/W-----_.p(output)'-...... --21~t+-----Hi9h impedance state ------P ---High impedance state --~


MITSUBISHI MICROCOMPUTERSMS0790SPINPUT/OUTPUT EXPANDER.APPLICATION EXAMPLESConnection with M50740SPFig. 1 shows the connections between the M?0790SP I/Oexpander and the M50740-XXXSP. The addresses listed inTable 1 are reserved for the M50790SP, and data read andwrit~ operations are possible in the same way as for the 'internalports of the M50740-XXXSP. (Only the low-order 4bits of the data are valid.) The timing and control signalsare generated automatically at the M50740-XXXSP end.The operation is now described. The output ports are setOFF state and the input/output ports are placed in thehigh-impedance state by the RESET OUT signal from theM50740-XXXSP.. Port inputting or outputting is conducted by the same instructionsas those to the M50740-XXXSP's other zero pagememory. With output port P40 - 1'44 read operations thecontents of the respective output latches. can be read out.With input/output ports P45- P49 the contents of the directionregister can determine whether the read data comefrom the output latches or input ports. "1 's" for each directionregister bit signifies output and "O's" signifies input.The contents of the direction registers cannot be read out.They must be set using the store instruction. Table 2 showsthe codes written into the direction registers and the statesof the input/output bits of the ports.Fig. 2 shows the construction of each of the output ports.When an address shown in Table 1 is accessed, double thenormal instruction execution time is required and so caremust be taken when calculating the processing time.This precaution must be taken since a margin is providedfor interfacing with the I/O expander.5V7 ....... 14VINTCNTRP3Vee1>31R/W32CE 33121>11R/W10 CEV DDP49P48P478X4P2PlPORESETouTR3R2RlRoVss272829301 K,QX416151413RESR3R2RlRoVssP46P45P44P43P42P41P404Xl0M50740-XXXSPM50790SPFlg.lExample of connections between 1/0 expander (M50790SP) and microcomputer (M50740':'XXXSP)6-24 • MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSMS0790SPINPUT/OUTPUT EXPANDERTable 1 Addresses reserved for I/O expanderAddress (hexadecimal)Data bitin zero page D7* I D6* I Ds* I D4* I D3 I D2, 1 D1 1 DoDF P49 Direction RegisterDEDD P48 Direction RegisterDCDB P47 Direction RegisterDAD9 P46 Direction RegisterD8D7 P45 Direction RegisterD6D5D4D3D2D1P49P48P47P46P45P44P43P42P41P40DO* Bits D4-D7 are ignored when the M50790SP is accessed.*Remarks0: Input, 1: OutputCMOS 3state 1/00: Input, 1: OutputCMOS 3state 1/00: Input, 1: OutputCMOS 3state 1/00: Input; 1: OutputCMOS 3state 1/00: Input, 1: OutputCMOS 3state 1/0Pch Open Drain OutputNch OPen Drain OutputqqqTable 2 Port setting examplesDirection register (low-order 4 bits)Port P4i bitD3 D2 D1 Do P4 i3 P4 i2 P4 i1 P4 io0 0 0 0 Input Input Input Input0 0 0 1 Input Input Input Output0 0 1 0 Input Input Output Input0 0 1 1 Input Input Output Output0 1 0 0 Input Output Input Input0 1 0 1 Input Output Input Output0 1 1 0 Input Output Output Input0 1 1 1 Input Output Output Output1 0 0 0 Output Input Input Input1 0 0 1 Output Input Input Output1 0 1 0 Output Input Output Input1 0 1 1 Output Input Output Output1 1 0 0 Output Output Input Input1 1 0 1 Output Output Input Output1 1 1 0 Output Output Output Input1 1 1 1 Output Output Output OutputIIIGOutputregisterj "0" = ONlVDDo",P""09''''''-1 ~'""=ONVss(a) P40-P43 (n-channel open drain)(b) P44 (p-channel open drain)(c) P45-P49 (C-MOS)3stateFig.2Output port format• MITSUBISHI,;"ELECTRIC6-25


MITSUBISHI MICROCOMPUTERSMSL8243PINPUT/OUTPUT EXPANDERDESCRIPTIONThe M5L8243P is an input/output expander fabricated usingN-channel silicon-gate, EO-MOS technology. This device isdesigned specifically to provide' a low-cost means of I/Oexpansion for the MELPS 8-48 single-chip microcomputersand MELPS 8-41 slave microcomputers.FEATURES• 16 Input/output pins (l oL = 5.0mA( max.))• Simple interface to MELPS 8-48, MELPS 8-41• Single 5V -power supply• Low power dissipation .............................. 50mW(typ.)• Interchangeable with i8243 in pin configuration and electricalcharacteristicsAPPLICATIONI/O expansion for the MELPS 8-48 single-chip microcomputersand MELPS 8-41 slave microcomputers.PIN CONFIGURATION (TOP VIEW)INPUTI0pUJ~~X P50 - 1INPUTI I P4 o - 2OUTPUT P4, - 3PORT4 P4 2- 4P43 - 5CHIP SELECT CS -+ 6PROGRAM PROG -+ 7INPUrl I3 - 8OUTPUT P22 - 9PORT 2 P2, _ 10P2o - 11(OV) GNDOutline 24P4Vee (5V)FUNCTIONThe M5L8243P is designed to provide a low-cost means ofI/O expansion for the MELPS 8-41 and the MELPS 8-48.The M5L8243P consists of four 4-bit bidirectional static I/Oports and one 4-bit port which serves as an interface to theMELPS 8-41 and MELPS 8-48. Thus multiple M5L8243Ps canbe added to a single master. Using the original instructionset of the master, the M5L8243P serves as the in resident 1/o facility. Its I/O ports are accessed by instructions MOVO,ANLO and ORLO.BLOCK DIAGRAMPORT 2CHIP SELECT PROGRAM~CS PROG1-------6 7--.--~I ,I ,4BUS44ANDIORLOGICANDIORLOGICLATCH. LATCHLATCHLATCH1,l_P7 0 P7, P7 2 P7 3'----v-----'PORT?P6 0 P6, P6 2 P6 3 P5 0 P5, P5 2 P5 3~ '----.------'PORTS PORT 5P4 0 P4, P4 2 P4 3'-v----'PORT 46-26•. MITSUBISHI"ELECTRIC


MITSUBISHI MICROCOMPUTERSMSL8243PINPUT/OUTPUT EXPANDERPIN DESCRIPTIONSymbol Name Input or output Function-Chip select input. A high on CS causes PROG input to be regarded high inside the M5L8243P, then thisCS Chip selectIninhibits any change of output or internal status.A high-to-Iow transition on PROG signifies that address (PORT 4-7) and control are. available on PORT 2,PROG Program In and a low-to-high transition signifies that the designated data is available on the disignated port throughPORT 2. The designation is shown in Table 1.P2 0 ........ P2 3 Input/output port 2 In/outThe 4-bit bidirectional port contains the address and control bits shown in Table 1 on a high-to-Iow transitionof PROG. During a low-to-high transition it contains the input (output) data on this port.P4o""""P4 3 Input/output port 4 The 4-bit bidirectional I/O port. May be programmed to be input, low-impedance latched output or aP5 0 ........ P5 3 Input/output port 5three-state. This port is automatically set output mode when it is written. AN Led or ORLed then con-In/outP66 ........ P63 Input/output port 6 tinues its mode until next read operation. After reset on a read operation, .this port is in high-impedanceP7o""""P7 3 Input/output port 7 and input mode.OPERATIONThe M5L8243P is an input/output expander designed specificallyfor the MELPS 8-41 and MELPS 8-48. The MELPS8-41 and MELPS 8-48 already have instructions and PROGpin to communicate with the M5L8243P.An example of the M5L8243P and the MELPS 8-41 orMELPS 8-48 is shown in Fig. 1. The following description ofthe M5L8243P basic operation is made according to Fig. 1.Upon initial application of power supply to the device, andthen about 500,us after, resident bias circuits become stableand each. device is ready to operate. And each port of theM5L8243P is set input mode (high-impedance) by means ofa resident power-on initialization circuit.When the microcomputer begins to execute a transfer instruction. MQVO A,Pi i = 4,5,6,7which means the value on the port Pi is transferred to theaccumulator, then the signals are sent out on the pinsPROG and P2o ........ P2 3 as shown in Timing Diagram.On the high-to-Iow transition of the pin PROG, theM5L8243P latches the instructions (ex. 0000) into itself frompins P2o ........ P2 3 and transfers them to the instruction register(CD in Timing Diagram). During the lOW-level of PROG, theM5L8243P continuously outputs the contents of the specifiedinput (output) port (in this case port P 4 ) to pins P2o""""P2 3 (~ in Timing Diagram). The microcomputer, at anappropriate time, latches the level of pins P2o"""" P2 3 and resumeshigh-level of PROG.The next example is the case in which the microcomputerexecutesMOVO Pi, A i = 4, 5, 6, 7the transfer (output) instruction.In this case, as in the previous case, on the high-to-Iowtransition of the pin PROG, the M5L8243P latches the instructions(ex. 0110) into itself from pins P2o"""" P2 3 and transfersthem to the instruction register (CD in Timing Diagram).After this, the microcomputer sends out high to the pinPROG, transferring the data to pin P2o """" P2 3 which is anoutput data to input/output port. Then the. M5L8243P transfersthe data of pins P2o ........ P2 3 to the port latch of the designatedinput/output port (in this case ps). In a few secondsafter a low-to-high transition on the PROG, the designatedport (ps) becomes in an output mode and the data of theport latch are transferred to the port pins (@ in TimingDiagram).When instructionsANlO Pi,AORlO Pi,A i = 4, 5, 6, 7are executed, the microcomputer generally operates assame function as MOVD Pi, A.It only differs in that the data of port latch after @ in theTiming Diagram is ANDed or ORed with the data of portlatch before @ and the data of pins P2o""""P2 3 .When instructionsMOVOANlOORlOPi,APi, APi ,A i = 4, 5, 6, 7are executed toward the port in an output mode, the outputsare generated on the port as soon as low-to-high transitionon the PROG occurs.When the mode of the output port is going to be changedduring the execution and the instructionMOVO A , Pi i = 4, 5, 6, 7is executed, it is preferable to execute one dummy instruction.Because it takes a little time to turn the designatedport into a high-impedance state after high-to-Iow transitionon the PROG, the result may be that the first instruction isnot read correctly.• MITSUBISHI.... ELECTRIC6-27


MITSUBISHI MICROCOMPUTERSMSL8243PINPUT /OUTPUT EXPANDERABSOLUTE MAXIMUM RATINGSSymbol Parameter Conditions Limits UnitVee Supply voltage -0.5-7 VV, Input voltage With respect to vss -0.5-7 VVo Output voltage -0.5-7 VPd Maximum power dissipation Ta = 25"C 600 mWTopr Operating free-air temperature range -20-75 ·CTsta Storage temperature range -65-150 ·CRECOMMENDED OPERATING CONDITIONS (Ta = -20-75·C, Vee = 5V±10%, unless otherwise noted)LimitsSymbol ParameterMin Nom MaxUnitVee Supply voltage 4.5 5 5.5 VVss Supply voltage 0 VV ,H High-level input voltage 2 Vee+O.5 VV ,L Low-level input voltage -0.5 0.8 VELECTRICAL CHARACTERISTICS (Ta = -20-75·C, Vee = 5 V±10%, unless otherwise noted)SymbolParameterV OL1 Low-level output voltage, ports 4-7V OL2 Low-level output voltage, port 7V OL3 Low-level output voltage, port 2V OH1 High-level output voltage, ports4-7V OH2 High-level output voltage, port 21'1 Input leakage current, ports 4-71'2 Input leakage current, port 2, CS, PROGIcc Supply current from VccIOL Sum of all IOL from 16 outputsTest conditionsMin10L = 5mA10L = 20mA10L = O.SmAIOH = -240J.lA 2.4IOH = -100J.lA 2.4OV ~ Vin ~ Vee -1,0OV ~ Vin ~ Vce -10IOL = 5mA (VOL = O. 45V) Each pinLimitsUnitTyp Max0.45 V1 V0.45 VVV2bf./.A10 f./.A10 20 mA80 mATable 1Instruction and address codesInstruction code P23 P2 2 Address codeRead 0 0 port 4Write 0 1 port 5ORLO 1 0 port 6ANLO 1 1 port 7. P210011P2 00101MELPS 8-48 orMELPS8-41PROG~---~MP2ot-----_.!P2,t------.!P2 2i+-----.j1P23i+-----.j,)Input/outputdevicesFig.lBasic connection6-28.• MITSUBISHI"ELECTRIC


MITSUBISHI MICROCOMPUTERSMSL8243PINPUT /OUTPUT EXPANDERTIMING REQUIREMENTS (Ta = -20-75'C, Vee = 5V±10%, unless otherwise noted)<strong>Al</strong>ternativeSymbol ParametersymbolTest conditionstSU(INST-PR) Instruction code setup time before PROG tA 80pF Load lOath(PR-INST) Instruction code hold time after PROG ts 20pF Load 60tSU(OQ-PR) Data setup time before PROG tc 80pF Load 200th(PR-OQ) Data hold time after PROG to 20pF Load 20tW(PR) PROG pulse width tK 700tSU(CS-PR) Chip-select setup time before PROG tcs 50th(PR-CS) Chip-select hold time after PROG tcs 50tSU(PORT-PR) Port setup time before PROG tiP lOath(PR-PORT) Port hold time after PROG tiP 100MinlimitsTypMaxUnitnsnsnsnsnsnsnsnsnsSWITCHING CHARACTERISTICS (T a = -20-75'C, Vee = 5V±10%, unless otherwise noted)SymbolParameter<strong>Al</strong>ternativesymbolTest conditionsMinlimitsTypMaxUnitta(PR)tdV(PR)Data access time after PROGData valid time after PROGtACCtH80pF Load20pF Load0a650 ns150 nstpHL(PR)tpLH(PR)Output valid time after PROGtpo100pF Load700 nstpZX(PR)tpXZ(PR)Input/output switching time-800 nsII• MITSUBISHI..... ELECTRIC6-29


~MITSUBISHI MICROCOMPUTERSM5L8243PTIMING DIAGRAMtSU(CS PRJINPUT/OUTPUT EXPANDERth(PR CS)CSTW(PR)PROG~~~~PORT 2PORT 2tSU(INST PRJCD):th(PR-INST) tSU(DQPR) th(PR DQ).1 Ita(PR)tdV(PR)~I®'\~ JtpZX(PR)PORTS 4-7PORTS 4-7tpXZ( PRJtPHL(PR)I ;rLH(:!,R)~@.~K@,.~~PORTS 4-71ft,i\.IF-PORTS 4-7tSU( PORT PRJth(PR PORT):KNote 1AC test conditionsInput pulse level",·"······""····"",,,,,,·· 0.45-2.4VInput pulse rise time tr (10%-90%) ............ 20nsInput pulse fal\ time tf (10%-90%)·············· 20nsReference voltage for switching characteristic measurement.Output VOH ·······················································,,········2VVOL ............................................................. 0.8VCurrent Sinking Capability"


MITSUBISHI MICROCOMPUTERSMSL8243PINPUT/OUTPUT EXPANDERExampleTo use 20mA sinking capability at port 7, find the effects onthe sinking capabilities of the other liD lines.Assume the M5L8243P is driving loads as shown below.3 lines: -20mA (VOL = 1.0V max, port 7 only)4 lines: -4mA (VOL = O.45V max)9l!nes: -1.6mA (VOL = O.45V max)Is this within the allowable limit?k IOL = (20mA X 3) + (4mA X 4) + (1.6mA X 9) =90.4mAFrom the curve we see that with respect to IOL = 4mA, IOLis 93mA (Point B) and that the above load of 90.4mA is withinthe limit of 93mA.Note: The sinking current of ports 4 -- 7 must not exceed30mA regardless of the value of VOL.Flg.2Expansion interface exampleII• MITSUBISHI.... ELECTRIC6-31


MITSUBISHI MICROCOMPUTERSMSM82C43PINPUT /OUTPUT EXPANDERDESCRIPTIONTheM5M82C43P is an input/output expander fabricated usingCMOS silicon-gate technology. This device is designedspecifically to provide a low-cost means of I/O expansionfor the MELPSS-48 single-chip S-bit microcomputers andthe MELPSS-41 slave microcomputers.FEATURES• 16 input/output pins (l oL = 5.0mA (max.))• Simple interface to MELPSS-4S, MELPSS-41• Single 5V power supply• Interchangeable with iS243 in pin configurationAPPLICATIONI/O expansion for the MELPS8-4S single-chip microcomputersand the MELPSS-41 slave microcomputers.PIN CONFIGURATION. (TOP VIEW)~~~J~OUTPUT P5 0 " 1IP4o" 2INPUT/OUTPUT P41 " 3PORT 4 P4 2 " 4P43 " 5CHIP SELECT CS -+ 6PROGRAM PROG -+ 7IP23 " 824 Vee (5V)23 .. P51 }22 .. P5 2 ~rg'R~T ~OUTPUT21 .. P5 320 .. P6 0 \19 .. P61 INPUT/OUTPUT18 .. P6 2PORT 617 .. P6 3INPUT/.OUTPUT P22" 916 "P7 3 \PORT 2 - P2 1" 1015 .. P72 INPUT/OUTPUTP2o" 1114 .. P7 1 PORT 7______ 1-3 .. P7(oV) GND0Outline 24P4FUNCTIONThe M5MS2C43P is designed to provide a low-cost meansof I/O expansion for the MELPSS-41 slave microcomputersand the MELPSS-4S single-chip microcomputers. TheM5MS2C43P consists of four 4-bit bidirectional _ static I/Oports and one 4-bit port which serves as an interface to theMELPSB-41 and MELPSS-4S. Thus multiple M5M82C43Pscan be added to a single master.Using the original instruction set of the master, theM?MS2C43P serves as the in-resident I/O facility. Its I/Oports are accessed by instructions MOVO, ANLO andORLO.BLOCK DIAGRAMPORT 2CHIP SELECT PROGRAM~CS PROG P2op2t22P23,----------- -6 7 1110 9 8IVed5V)IIIIIIL_6-32 • MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSMSM82C43PINPUT/OUTPUT EXPANDERPIN DESCRIPTIONSymbol Name Input or output Function-C$ Chip selectInChip select input. A high on CS causes PROG input to be regarded high inside the M5M82C43P. Thisthen inhibits any change of output or internal status.A high-to-Iow transition on PROG signifies that address (ports 4-7) and' control are available on port 2,PROG Program In and a low-to-high transition signifies that the designated data is available on the designated port throughport 2. The designation is shown in Table 1.P2 0 ...... P2 3 Input/output port 2 In/outThis 4-bldlrectional port contains the address and control bits shown in Table 1 on a high-to-Iow transitionof PROG. During a low-to-high tranSitiOn, it contains the input (output) data on this port.P4 o ...... P4 3 Input/output port 4 4-bit bidirectional I/O ports. May be programmed to be input, low-Impedance latched or 3-state. TheseP5 0 ...... P5 3 Input/output port 5ports are automatically set to the output mode when written, ANLed or ORLed and this mode continuesIn/outP6 0 ...... P6 3 Input/output port 6 until the next read operation. After reset on a read operation, this port Is placed in the high ImpedanceP7 o ...... P7 3 Input/output port 7 and input mode.OPERATIONThe M5MB2C43P is an input/output expander designedspecifically for the MELPSB-41 and MELPSB-4B. TheMELPS8-41 and MELPS8-4B already have instructions andPROG pin to communicate with the M5M82C43P.An example of the M5M82C43P and the M5MBOC49-XXXP isshown in Fig. 1. The following description of theM5M82C43Pbasic operation is made according to Fig. 1.Upon initial application of the power supply to the device,each port of the M5MB2C43P is set to the input mode (highimpedance)by means of the resident power-on initializationcircuit.When the microcomputer begins to execute a transfer instructionMOVO A, Pi i = 4,5,6.7which means the value on the port Pi is transfer~d to theaccumulator. then the signals are sent out on the pinsPROG and P2o ...... P2 3 • as shown in the timing diagram.On the high-to-Iow transition of pin PROG. the M5M82C43Platches the instructions (e.g. 0000) into itself from pins P2o ......P2 3 and transfers them to the instruction register (CD in thetiming diagram). During the low-level of PROG, theM5M82C43P continuously outputs the contents of the specifiedinput (output) port (in this case, port P4) to pins P2o ......P2 3 (~ in the timing diagram). The microcomputer. at theappropriate time. latches the level of pins P2o ...... P2 3 and resumesthe, high level of PROG.The next example is the case in which the microcomputerexecutesMOVO PI, A i = 4. 5. 6. 7the transfer (output) instruction.In this case. as in the previous case, on the high-to-Iowtransition of pin PROG. the M5MB2C43P latches the instructions(e.g.Oll0) into itself from pins P2o ...... P2 3 and transfersthem to the instruction register (CD in the timing diagram).After this the microcomputer sends out high to pin PROG.transferring the data to pins P2o ...... P2 3 which is an outputdata to the input/output port. Then the M5MB2C43P transfersthe data of pins P2o ...... P2 3 to the port latch of the designatedinput/output port (in this case P6). In a few secondsafter a low-to-high transition on the PROG. the designatedport (P6) is set to the output mode and the data of the portlatch is transferred to the port pins (@ in the timingdiagram).When instructionsANlOORlOPi,APi,A i = 4.5.6.7are executed. the microcomputer generally operates as thesame function as MOVD Pi.A.It only differs in that the data of the port latch after ® in thetiming diagram is ANDed or ORed with the data of the portlatch before ® and the data of pins P2o ...... P2 3 .When instructionsMOVO Pi, AANlO Pi,AORlO Pi,A i = 4. 5, 6. 7are executed toward the· port in an output mode, the outputsare generated on the port as soon as low-to-high transitionon the PROG occurs.When the mode of the output port is going to be changedduring the execution and the instructionMOVO A,Pi i=4.5.6.7is executed. it is preferable to execute one dummy instruction'.Because it takes a little time to turn the designatedport into a high-impedance state after the high-to-Iow transitionon the PROG, the result may be that the first instructionis not read correctly .II•• . MITSUBISHI.... ELECTRIC6-33


MITSUBISHI MICROCOMPUTERSMSM82C43PINPUT /OUTPUT EXPANDERABSOLUTE MAXIMUM RATINGSSymbol Parameter Conditions Limits UnitVcc Supply voltage Vss-0.3-7 VVI Input voltage Vss-O. 3-Vcc+0. 3 VVo Output voltage Vss-O. 3-Vcc+0. 3 VPd Maximum power dissipation Ta = 25'C 1000 mWT oDr Operating free-air temperature range -40-85 'cTsta Storage temperature range -65-150 'cRECOMMENDED OPERATING CONDITIONS (T a = ~40-85'C,Vee = 5V±1 0%, unless otherwise noted)LimitsSymbol ParameterMin Nom MaxUnitVcc Supply voltage 4.5 5 5.5 VVss Supply voltage 0 VV IH High-level input voltage O. 7XVee Vcc VV IL Low-level input voltage Vss O. 3XVee VELECTRICAL CHARACTERISTICS (Ta = -40-85'C, Vee = 5V±10%, unless otherwise noted)SymbolParameterV OLl Low-level output voltage, ports 4-7V OL2 Low-level output voltage, port 7V OL3 Low-level output voltage, port 2VOH1 High-level output voltage, ports4-7V OH2 High-level output voltage, port2111 Input leakage current, ports 4-7112 Input leakage current port 2, CS, PROGIccl Supply current (1)Icc2 Supply current(2)IOL Sum of all 10L from 16 OutputsTest conditions10L = 5mA10L'= 20mA10L = O.6mA10H = -240,uA10H = -1OO,uAVss ;:;; Yin ;:;; VeeVss ;:;; Vln ;:;; VeeVee = 5.5V, VIN = Vee or VssPROG input pulse period = 5,usVee = 5. 5V, VIN = Vee or VssPROG = Vee10L = 5mA (VOL = O. 45V) each pinMinO. 75XVeeO. 75XVec-10-10LimitsTypUnitMax0.45 V1 V0.45 VVV20 J1.A10 J1.A2 mA10 J1.A80 mATable 1Instruction' and address codesInstruction code P2 3 P2 2 Address codeRead 0 0 Port 4Write 0 1 Port 5ORLO 1 0 Port 6ANLO 1 1 Port 7P2,0011P200101MELPSS-4S or MELPSS-41P2ol-----etP2,1-----etP221+-------tP231+-------t'--~~l:::IFlg.1Basic connection6-34•. MITSUBISHI..... ELECTRIC


MITSUBISHI MICROCOMPUTERSMSM82C43PINPUT/OUTPUT EXPANDERTIMING REQUIREMENTS (Ta = -40-85"C, Vee = 5V±1O%, Vss = ov, unless otherwise noted)<strong>Al</strong>ternativeLimitsSymbol Parameter Test conditionssymbol Min TyptSU(INST-PR) Instruction code setup time befor PROG tA CL = 80pF 100th(PR-INST) Instruction code hold time after PROG ts CL = 20pF 60tSU(OQ-PR) Data setup time before PROG tc CL = 80pF 200th(PR-OQ) Data hold time after PROG to CL = 20pF 20tW(PR) PROG pulse with tK 700tSU


~ ________MITSUBISHI MICROCOMPUTERSMSM82C43PINPUT/OUTPUT EXPANDERTIMING DIAGRAMcstsu(CS PRJth(PR CS)tW(PR)~,.PROGi\[ItSU(INST PRJ th(PR INST) tSU(DQ PRJ th(PR DQ)IPort 2CD):ta(PR)~R),Port 2IPort 4-7Port 4-7~ell'ItpZX(PR)-@J""tpHL(PR)\:I~LH(:R) -®'1,KtpXZ( PRJPort 4-7Port 4-7tSU( PORT PRJNote 1 : Input pulse level································ 0.3 X Vee-O.7 X VeeInput pulse rise time tr ............................................... 20nsInput pulse fall time tf .........................................x:: ...... 20nsReference voltage for switching characteristic measurementO. 7XVec ------"" -----O. 7XV ce0.3 XVec _____-J. _ O.3XVee'~'Ir.th(PR PORT):KCurrent Sinking Capability7For this case, each of the 7 lines could sink 8mA for a totalof 56mA. Since a 4mA reserve sinking capability exists, 9 ofthe I/O lines of the M5M82C43P can be divided arbitrarily. .6-36 .MITSUBISHI"ELECTRIC


MITSUBISHI MICROCOMPUTERSMSM82C43PINPUT/OUTPUT EXPANDERExample:To use the 20mAsinking capability at port7, find the effectson the sinking capabilities of the other I/O lines. Assumethe M5M82C43P is driving loads as shown below:3 lines: 20mA (VOL = 1.OV max, port 7 only)4 lines: 4mA (VOL = 0.45V max)9 lines: 1.6mA (VOL = 0.45V max)Is this within the allowable limit?I IOL = (20mA X 3) + (4mA X 4) + (1.6mA X 9) =90.4mAFrom the curve it is seen that with respect to IOL = 4mA, IOLis 93mA (point B) and that the above load of 90.4mA is withinthe limit of 93mA.Note: The sinking current of port 4 -- 7 must not exceed30mA regardless of the value of VOL.M5M80C49-XXXPFig.2PROGir-----------~------------~------------~----------~Expansion Interface exampleII• MITSUBISHI..... ELECTRIC6-37


MITSUBISHI MICROCOMPUTERSMSM82C43PINPUT/OUTPUT EXPANDER'>J:0>wC!l«~0>I-::Ja..I-::J0OUTPUT VOLTAGE VS.OUTPUT SINK CURRENT4.8 ~4.64.44.2(Port P4 ...... Port P7)~\\.\4.0'\3.8o\IVee =5VTa= 25'C-~0>w(!)«I- ....J0>I-::Ja..I-::J00.30.20.1OUTPUT VOLTAGE VS.OUTPUT SINK CURRENT(Port P4 ...... Port P7)IVee =5VT a = 20'CVV- /·7,V-oo 10 15 20 25 30OUTPUT SINK CURRENTIOL(mA)OUTPUT SINK CURRENTIOH(mA)~0>wC!l«~0>I-::Ja..I-::J0OUTPUT VOLTAGE VS.OUTPUT SINK CURRENT(Port P2)'"Vee = 5V4.8Ta=25'C-"-4.6......'"4.4"~."4.24.03.8o~~w(!)«~0>I-::Ja..I-::J0OUTPUT VOLTAGE VS.OUTPUT SINK CURRENT(Port P2)0.6IVee = 5V/0.5 -Ta = 25'C0.40.30.20.1ooV./1/1/1/OUTPUT SINK CURRENTIOH(mA)OUTPUT SINK CURRENTIOL(mA)NORMALIZED SUPPLY CURRENT {IcC> VS.I-ZWII:II:::J0~a..a..::Jen0wN::J«~II:0ZSUPPLY VOLTAGE1.4ITa = 25'C1.21.00.8/0.64t(MCU) = 6MHz/I/4.5 5.5SUPPLY VOLTAGE Vee(V)NORMALIZED SUPPLY CURRENT {IcC> VS.MCU OPERATING FREQUENCY1.5II- Vee = 5Vzw 1.25 -Ta = 25'CII:II:::J0 1.0~a..a..::>en0wN::J«~II:0Z0.750.50.25o o....... ~ ~~V./MCU OPERATING FREQUENCY (MHz)10126-38• MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSMSL81SSP2048-BIT STATIC RAM WITH I/O PORTS AND TIMERDESCRIPTIONThe M5L8155P is a 2K-bit RAM (256-word by 8-bit) fabri-_cated with the Nchannel silicon-gate ED-MOS technology.This IC has 3 I/O ports and a 14-bit counter/timer whichmake it a good choice to extend the functions of an 8-bitmicrocomputer. It is incased in a 40-pin plastic OIL packageand operates with a single 5V power supply.FEATURES• Compatible with MELPS 85 devices• Static RAM: 256 words by 8 bits• Programmable 8-bit I/O port: 2• Programmable 6-bit I/O port: 1• Programmable counter/timer: 14 bits• Multiplexed address/data bus• Single 5V power supply• Configuration and electrical characteristicsAPPLICATIONExtension of I/O ports and timer function for MELPS 85 andMELPS 8-48 devicesFUNCTIONThe M5L8155P is composed of RAM, I/O ports and counter/timer. The RAM is a 2K-bitstatic RAM organized as 256words by 8 bits. The I/O ports consist of 2 programmable 8-bit ports and 1 programmable 6-bit port. The terminals of the6-bit port can be programmed to function as control terminalsfor the 8-bit ports, so that the 8-bit ports can be operatedin a handshake mode. The counter/timer is composed of 14PIN CONFIGURATION (TOP VIEW)jPC3- 1I/O PORT C \ PC _4TIMER INPUT TIMER IN -+ 3RESET INPUT RESET -+ 4I/O PORT C PC5 - 5TIMER OUTPUT TIMER OUT +- 6SELEC~E~~nt 10 M -+ 7CHIP ENABLE INPUT CE -+ 8READ .INPUT RD -+ 9BIDIRECTIONALADDRESS/DATA BUSOutline 40P41/0PORT C1I/OPORT BI/OPORT Abits that can be used to count down (events or time) and itcan generate square wave pulses that .can be used forcounting and timing.11BLOCK DIAGRAM(5V)Vcc® --------------------­(ov)vss ~STATIC RAM(256 WORDS X 8 BITS)I/OPORT ABIDIRECTIONALADDRESS/DATA BUSDATA BUSBUFFER81-BIT INTERNALDATA BUSI/OPORT BRESET INPUT RESET 4MEMORY SELECT INPUT 10/MCHIP ENABLE INPUT CEREAD INPUTWRITE INPUTADDRESS LATCHENABLE INPUTREAD/WRITECONTROLCIRCUITI/OPORT C~---• MITSUBISHI..... ELECTRIC6-39


MITSUBISHI MICROCOMPUTERSMSL81SSP2048-BIT STATIC RAM WITH I/O PORTS AND TIMER; OPERATIONData Bus BufferThis 3-state bidirectional 8-bit buffer is used to transfer thedata while input or output instructions are being executed bythe CPU. Command and address information is also transferredthrough the data bus buffer.ReadlWrite Control LogicThe read/write control logic controls the transfer of data byinterpreting I/O' control bus output signals (RD, WR, 10iMand ALE) along with CPU signal (CE). RESET signal is alsoused to control the transfer of data and commands.Bidirectional Address/Data Bus (ADo-AD 7 )The bidirectional address/data bus is a 3-state 8-bit bus.The 8-bit address is latched in the internal latch by the failingedge of ALE. Then if 10iM input signal is at high-level,the address of I/O port, counter/timer, or command registeris selected. If it is at low-level, memory address is selected.The 8-bit address data is transferred by read input (RD)or write input (WR).Chip Enable Input (CE)When CE is at low-level, the address information onaddress/data bus is stored in the M5L8155PRe.d Input (RD)When RD is at low-level the data bus buffer is active. If 10/M input signal is at low-level, the contents of RAM are readthrough the address/data bus. If 10/M input is at high-level,the selected contents of I/O port or counter/timer are readthrough the address/data bus.Write Input (WR) ,When WR is at low-level, the data on the address/data busare written into RAM if 10/M is at low-level, or if 10/M is athigh-level they are written into I/O port, counter/timer orcommand register.Address Latch Enable Input (ALE)An address on the address/data bus along with the levels ofCE and IO/M are latched in the M5L8155P on the fallingedge of ALE.10lMemory Input (101M)When 10/M is at low-level, the RAM is selected, while athigh-level the I/O port, counter/timer or command registerare selected.1/0 Port A (PAo-PA t )Port A is an 8-bit general-purpose I/O port. Input/output set~ting is controlled by the syst~m software.1/0 Port B (PBo-PB 7 )Port B is an 8-bit general-purpose I/O port. Input/output settingis controlled by the system software.1/0 Port C (PC~-PC5)Port C is a 6-bit I/O port that can also be used to outputcontrol signals of port A (PA) or port B (PB). The functionsof port C are controlled by the system software: When port Cis used to output control signals of ports A or B the iissignmentof the siQnals to the pins is as shown in Table 1 .TablePin1 Pin assignment of control signals of, ,porteFunctionPCs B STB (port B strobe)PC4 B SF (port B buffer full)PC3 BINTR (port B interrupt)PC2 ASTB (port A strobe)PCl A BF (port A buffer full)PCa AINTR (port A interrupt) '-Timer Input (TIMER IN)The signal at this input terminal is used by the counter/timerfor counting events or time. (3MHz max.)Timer Output (TIMER OUT)A square wave signal or pulse from the counter/timer is outputthrough this pin when in the operation mode.Command Register (8 bits)The command register is an 8-bit latched register. Theloworder 4 bits (bits 0 ...... 3) are used for controlling and determinationof mode of the ports. Bits 4 and 5 are used as interruptenable flags for ports A and B when port C is usedas a control port. Bits 6 and 7 are used for controlling thecounter/timer. The contents of the command register are rewrittenby output instructions (address I/O XXXXXOOO).Details of the functions of the individual bits of the commandregister are shown in Table 2.Table2 Bit functions of the command registerBit Symbol Function0 PAIPB2 PCl3 PC24 lEA5 IEB6 TMI7 TM2PORT A I/O FLAGPORT B I/O FLAGPORT C FLAGPORT A ,INTERRUPTENABLE FLAGPORT B INTERRUPTENABLE FLAGCOUNTER/TIMER CONTROL1: OUTPUT PORT A0: INPUT PORT A1: OUTPUT PORT B0: INPUT PORT B00: ALTI11: ALT2'01: ALT310: ALT41: ENABLE INTERRUPT0: DISABLE INTERRUPT1: ENABLE INTERRUPT0: DISABLE INTERRUPT00: NO INFLUENCE ON COUNTER/TIMER OPERATION01: COUNTER/TIMER OPERATION DISCONTINUED (IFNOT ALREADY STOPPED)10: COUNTER/TIMER OPERATION DISCONTINUED AF-TER THE CURRENT COUNTER/TIMER 'OPERATIONIS COMPLETED11: COUNTER/TIMER OPERATION STARTED6-40 • ,MITSUBISHI'" ELECTRIC


THISMITSUBISHI MICROCOMPUTERSMSL81SSP2048-BIT STATIC RAM WITH I/O PORTS AND TIMERStatus Register (7 bits)The status register is a 7-bit latched register. The loworder 5bits (bits 0-4) are used as status flags for the I/O ports. Bit6 is as a status flag for the counter/timer. The contents ofthe status register are transferred into the CPU by reading(INPUT instruction, address I/O XXXXXOOO). Details of thefunctions of the individual bits of the status register areshown in Table 3.Table 3 Bit functions of the status registerBit Symbol Function0 INTR A PORT A INTERRUPT REQUEST1 A BF PORT A BUFFER FULL FLAG2 INTE A PORT A INTERRUPT ENABLE3 INTR B PORT B INTERRUPT REQUEST4 B BF PORT B BUFFER FULL FLAG5 INTE B PORT B INTERRUPT ENABLE6 TIMER COUNTER/TIMER INTERRUPT (SET TO 1 WHEN THE FINAL LIMITOF THE COUNTERITIMER IS REACHEDAND IS RESET TO 0 WHEN THESTATUS IS READ)7~BIT IS NOT USED1/0 PortsCommand/status registers (8 bitsn bits)These registers are assigned address XXXXXOOO. When executingan OUTPUT instruction, the contents of the commandregister are rewritten. When executing an INPUT instructionthe contents of the status register are read.Port A Register (8 bits)Port A Register is assigned address XXXXX001. This registercan be programmed as an input or output by setting theappropriate bits of the command register as shown in Table2.Port A can be operated in basic or strobe mode and isassigned I/O terminal PAo-PA7.Port B Register (8 bits)Port B register is assigned address XXXX)(01 O. As with PortA register, this register can be programmed as an input oroutput by setting the appropriate bits of the command registeras shown in Table 2. Port B can be operated in basic orstrobe mode and is assigned I/O terminals PBo-PB7.Port C Register (6 bits)Port C register is assigned address XXXXX011. This port isused for controlling input/output operations of ports A and Bby selectively setting bits 2 and 3 of the command registeras shown in Table 2. Details of the functions of the varioussetting of bits 2 and 3 are shown. in Table 4. Port C isassigned I/O terminals PCo - PC 5 and when used as portcontrol signals, the 3 low-order bits are assigned for port Awhile the 3 high-order bits are assigned for port B.IITable 4 Functions of port CStateTerminalALT 1 ALT 2 ALT 3PC 5 Input Output OutputPC4 Input Output OutputPC3 Input Output OutputPC2 Input Output A STB (port A strobe)PC, Input Output A BF (port A buffer full)PCa Input Output A INTR (port A interrupt)B STB (port B strobe)B BF (port buffer full)B INTR (port B interrupt)A STB (port A strobe)A BF (port A buffer full)A INTR (port A interrupt)ALT 4'. MITSUBISHI.... ELECTRIC6-41


MITSUBISHI MICROCOMPUTERSMSL81SSP,2048·BIT STATIC RAM WITH I/O PORTS AND TIMERConfiguration of portsA block diagram of 1 bit of ports A and B is shown in Fig. 1.While. port A or B is programmed as an output port, if theport is addressed by an input instruction, the contents of theselected port can be read. When a port is put in input mode,the output latch is cleared and writing into the output latch isdisabled. Therefore when a port is changed to output modefrom input mode, low-level signals are output through theport. When a reset signal is applied, all 3 ports (PA, PB, andPC) will be input ports and their output latches are cleared.Port C has the same configuration as ports A and B in modesAL T1 and AL T2.M5L8155PINTERNALDATA BUS,--:-1I 1*1I IEXTERNAL PINPORT A OR)( PORT BRD PORTWR PORTMD1. WR PORT=IO/M'WR'CE'(PORT ADDRESS SELECTED)2. RD PORT=IO/M'RD'CE'(PORT ADDRESS SELECTED)3. MULTIPLEX CONTROL1 STROBE INPUT MODE* 2 INPUT MODE* 3 OUTPUT MODE4. MD= 1 : OUTPUT MODEo : INPUT MODEFig. 1Configuration for 1 bit of port A or BTable 5 Basic functions of I/O portsAddress RD WR Function0 1 AD bus - status registerXXXXXOOO1 0 Command register - AD bus0 1 AD bus":' port AXXXXXOOl1 0 Port A - AD bus0 1 AD bus- port BXXXXX0101 0 Port B-AD bus0 1 AD bus - port CXXXXXOll1 0 Port C - AD busTable 6 Port control signal levels at AL T3 and AL T4Control Signal Output mode Input modeSTS Input InputSF "L" "L"INTR "H" "L"The basic functions of the I/O ports are shown in Table 5.The control signal levels to ports A and B, when port C isprogrammed as a control port, are shown in Table 6.Counter/TimerThe counter/timer is a 14-bit counting register plus 2 modeflags. The register has two sections: address I/O XXXXX100is assigned to the low-order 8 bits and address 1/0XXXXX101 is assigned to the high-order 8 bits. The loworderbits 0 ...... 13 are used for counting or timing. The counteris initialized by the program and then counted down to zero.The initial setting can range from 216 to 3FFFI6. Bits 14 and15 are used as mode flags.The mode flags select 1 of 4 modes with functions asfollow:Mode 0: Outputs high-level signal during the formerhalf of the counter operationOutputs low-level signal during the latter halfof the counter operation6-42 '.MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSM5L8155P2048-BIT STATIC RAM WITH I/O PORTS AND TIMERTable 7 Format of counter/timer Mode 1: Outputs square wave signals as in mode 0Mode 2: Outputs a low-level pulse during the finalAddressBit Numbercount downFunction7 6 5 4 3 2 1 0Mode 3: Outputs a low-level pulse during each finalTHE LOW-ORDER 8 BITScount downXXXXX100 T7 T6 T5 T4. T3 T2 Tl ToOF THE COUNTER REGISTER Starting and stopping the counter/timer is controlled byXXXXX101 M2 Ml T13 T12 Tll TlO T9 TaM1 ,M2: TIMER MODETHE HIGH-ORDER 6 BITSTa-T13: OF THE COUNTER REGISTERbits 6 and 7 of the command register (see Table 2 fordetails) . The format and timer modes of the counter/timerregister are shown in Table 7 and Table 8.Table 8 Timer modeThe counter/timer is not influenced by a reset, but countingis discontinued. To resume counting, a start command mustbe written into the command register as shown in Table 2.oMloTimer operationOutputs high-level signal during the former half of the counter operationOutputs low-level signal during the latter half of the counter operation(mode 0)Outputs square wave signals in mode 0 (mode 1)While operating 2n+ 1 count down in mode 0, a high-levelsignal is output during the n+ 1 counting and a low-level signalis output during the n counting.oOutputs a low-level pulse during the final count dowm(mode 2)Outputs a low-level pulse during each final count down(mode 3)ABSOLUTE MAXIMUM RATINGSSymbol Parameter ConditionsVcc Supply voltageVI Input voltage With respect to VssVo Output voltagePd Maximum power dissipation Ta=25°CTopr Operating free-air temperature rangeTstg Storage temperature rangeLimitsUnit-0.5-7 V-0.5-7 V-0.5-7 V1.5 W0-70 ·c-65-150 ·c11RECOMMENDED OPERATING CONDITIONS (Ta=O-70'C, unless otherwise noted)LimitsSymbol Parameter UnitMin Nom MaxVcc Supply voltage 4.75 5 5.25 VVss Power-supply voltage 0 VV IL Low-level input voltage -0.5 0.8 VV IH High-level input voltage 2 Vcc+O. 5 VELECTRICAL CHARACTERISTICS (T a=O-70°C , Vcc=5V±5%, unless otherwise noted)Symbol Parameter Test conditionsMinLimitsTypMaxUnitV OH High-level output voltage Vss=OV,loH=-400,uA2.4VVOL Low-level output voltage Vss=OV, 10L =2mAII Input leak current VsS=OV,VI=O-VCCII(CE) Input leak current. CE pin Vss=OV, VI=O-VCCloz Output floating leak current Vss=OV, VI=O. 45-Vcc-10-100-100.45 V10 /-LA100 /-LA10 /-LAGi Input capacitance VIL =OV, f=l MHz, 25mVrms, Ta=25°C10 pFGi/o Input/output terminal capacitance VI/0L =OV, f=l MHz, 25mVrms, T a=25°C20 pFIcc Supply current from Vcc Vss=OV180 rnANote 1Current flowing into an IC is positive, out is negative.• MITSUBISHI"ELECTRIC6-43


MITSUBISHI MICROCOMPUTERSMSL81SSP2048-BIT STATIC RAM WITH I/O PORTS AND TIMERTIMING REQUIREMENTS (Ta=O-70·C, Vcc=5V±5%, unless otherwise noted)<strong>Al</strong>ternativeSymbol Parameter Test conditionssymbolISU(A-L) Address setup time before latch IALIh(L"A) Address hold tilne after lalch ILAIh(L-RWH) Read/write hold time after latchIW(L) Latch pulse width ILLIh(RW-L) Latch hold time after read/write tCLIW(RWL) Read/write low-level pulse width tcctSU(D-W) Data setup time before write towth(W-D) Data hold time after write twotW(RWH) Read/write high-level pulse width tRvtSU(P-R) Port setup time before read t pRIh(R-P) Port hold time after read tRPtW(STB) Strobe pulse width tssISU(P-STB) Port setup time before strobeILCIpssIh(STB-P) Port hold time after strobe IpHSIW(f>H) Timer input high-level pulse width 12I w ( f> L) Timer input low-level pulse width 11t c ( f» Timer input cycle time tcvct r( f» Timer input rise time trtf( f> ) Timer input fafl time IfLimitsUnitMin Typ Max50 ns80 ns100 ns100 ns20 ns250 ns150 ns0 ns300 ns70 ns50 ns200 ns50 ns120 ns120 ns80 ns320 ns30 ns30 nsSWITCHING CHARACTERISTICS (Ta=O-70·C, Vcc=5V±5%, unless otherwise noted.)SymbolParametertPXV(R-DQ) Propagation time from read to data output tRDtPZX(A-OQ) Propagation time from address to data output tADtPVZ(R-OQ) Propagation time from read to data lIoating (Note 2) tRDFtpHL


MITSUBISHI MICROCOMPUTERSM5L8155P2048-BIT STATIC RAM WITH I/O PORTS AND TIMERTIMING DIAGRAM (reference level. high-level=2V. low-level=O.8V)Basic outputPORT~~f{ItWlRWUtPHUW-P)tPLHlW-P)17 ~'---tWl RWH )thlL-RWH)thlW-O)IO/M \\VV\\)ADDRESS J( ~[-DATA ~~ALEtSU(A-U thlL-A) tsulO-W)tWlUI"!! ....-.J1thlRW-U _IBasic inputPORT)~(IItSU(P-R)~tWlRWUt---- th(R-P)----Jl~ItWlRWH)-',--tClL-RW)-tpXVlR-OO)tpZXlR-OO)tClRW-UI---tpXZlR-OO)101M \r.~\\f\[-)(tpzxlA-O),(...ADDRESSn...~r~:\DATA~ K=ALEJTtsulA-UtWlU\~thlL-A)I(• MITSUBISHI"ELECTRIC'6-45


MITSUBISHI MICROCOMPUTERSMSL81SSP2048-BIT STATIC RAM WITH I/O PORTS AND TIMERStrobed outputStrobed inputPORTBFINTRTimer (Note 1)TIMER INTIMER OUTPULSE MODENoteTIMER OUT .,SQUARE WAVE MODE ------------' (Note 2)The wave form is shown counting down from 5 to 1.As long as the Ml mode flag of the timer register is athigh-level. pulses are continuously output.6-46•. MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSMSL8156P2048-BIT STATIC RAM WITH I/O PORTS AND TIMERDESCRIPTIONThe M5L8156P is a 2K-bit RAM (256-word by 8-bit) fabricatedwith the N-channel silicon~gate ED-MOS technology.This IC has 3 I/O ports and a 14-bit counter/timer whichmake it a good choice to extend the functions of an 8-bitmicrocomputer. It is incased in a 40-pin plastic OIL packageand operates with a single 5V power supply.FEATURES• Compatible with MELPS 85 devices• Static RAM: 256 words by 8 bits• Programmable 8-bit I/O port: 2• Programmable 6-bit I/O port: 1• Programmable counter/timer: 14 bits• Multiplexed address/data bus• Single 5V power supply• Configuration and electrical characteristicsAPPLICATIONExtension of I/O ports and timer function for MELPS 85 andMELPS 8-48 devicesFUNCTIONThe M5L8156P is composed of RAM, I/O ports and counter/timer. The RAM is a 2K-bit static RAM organized as 256words by 8 bits. The I/O ports consist of 2 programmable 8-bit ports and 1 programmable 6-bit port. The terminals of the6-bit port can be programmed to function as control terminalsfor the 8-bit ports, so that the 8-bit ports can be operatedin a handshake mode. The counter/timer is composed of 14PIN CONFIGURATION (TOP VIEW)PC3- 11/0 PORT C1 PC4-TIMER INPUT TIMER IN - 3RESET INPUT RESET - 41/0 PORT C PCs- 5TIMER OUTPUT TIMER OUT +- 6SELEC~E~~~t 10 M - 7CHIP ENABLE INPUT CE - 8READ INPUT RD - 9WRITE INPUl WR -10ADE~JAEBl~ 1~~t,~ ALE - 11ADo-12BIDIRECTIONALADDRESS/DATA BUS(OV)V ssOutline 40P41/0PORT C1110PORT B1/0PORT Abits that can be used to count down (events or time) and itcan generate square wave pulses that can be used forcounting and timing.IIBLOCK DIAGRAM(5V) vee;o - ---- --- - --- - ---­(OV) Vss 20STATIC RAM(256 WORDS X 8 BITS)1/0PORT ABIDIRECTIONALADDRESSIDATA BUSDATA BUSBUFFER1/0PORT BRESET INPUT RESET 4MEMORY SELECT INPUT 101MCHIP ENABLE INPUT CEREAD INPUTWRITE INPUTADDRESS LATCHENABLE INPUTREADIWRITECONTROLCIRCUIT1/0PORT C• MITSUBISHI.... ELECTRIC6-47


MITSUBISHI MICROCOMPUTERSMSL81S6P2048-BIT STATIC RAM WITH I/O PORTS AND TIMEROPERATIONData Bus BufferThis 3-state bidirectional 8-bit buffer is used to transfer thedata while input or output instructions are being executed bythe CPU. Command and address information is also transferredthrough the data bus buffer.Read/Wrlte Control LogicThe read/write control logic controls the transfer of data byinterpreting I/O control bus output sign~ls (RD, WR, 10/Mand ALE) along with CPU signal (CE). RESET signal is alsoused to control the transfer of data and commands.Bidirectional Address/Data Bus (ADo-AD 7 )The bidirectional address/data bus is a 3-state 8-bit bus.The 8-bit address is latched in the internal latch by the failingedge of ALE. Then if 10/M input signal. is at high-level,the address of I/O port, counter/timer, or command registeris selected. If it is at low-level, memory address is selected.The 8-bit address data is transferred by read input (RD)or write input (WR).Chip Enable Input (CE)When CE is at high-level, the address information onaddress/data bus is stored in the M5L8156PRead Input (RD)When RD is at low-level the data bus buffer is active. If 10/M input signal is at low-level, the contents of RAM are read .through the address/data bus. If 10iM input is at high-level,the selected contents of I/O port or counter/timer are readthrough the


MITSUBISHI MICROCOMPUTERSMSL81S6P2048-BIT STATIC RAM WITH I/O PORTS AND TIMERStatus Register (7 bits)The status register is a 7-bit latched register. The loworder 5bits (bits O~4) are used as status flags for the I/O ports. Bit6 is as a status flag for the counter/timer. The contents ofthe status register are transferred into the CPU by reading(INPUT instruction, address I/O XXXXXOOO). Details of thefunctions of the individual bits of the status register areshown in Table 3.Table3 Bit functions of the status registerBit Symbol Function0 INTR A PORT A INTERRUPT REQUEST1 A BF PORT A BUFFER FULL FLAG2 INTE A PORT A INTERRUPT ENABLE '3 INTR B PORT B INTERRUPT REQUEST4 B BF PORT B BUFFER FULL FLAG5 INTE B PORT B INTERRUPT ENABLE6 TIMER COUNTER/TIMER INTERRUPT7 - THIS BIT IS NOT USED.(SET TO 1 WHEN THE FINAL LIMITOF THE COUNTER/TIMER IS REACHEDAND IS RESET TO 0 WHI:N THESTATUS IS READ)1/0 PortsCommand/status registers (8 bitsl7 bits)These registers are assigned address XXXXXOOO. When executingan OUTPUT instruction, the contents of the commandregister are rewritten. When executing an INPUT instructionthe contents of the status register are read.Port A Register (8 bits)Port A Register is assigned address XXXXX001. This registercan be programmed as an input or output by setting theappropriate bits of the command register as shown in Table2.Port A can be operated in basic or strobe made and isassigned I/O terminal PAo~PA7.Port B Register (8 bits)Port B register is assigned address XXXXX010. As with PortA register, this register can be programmed as an input oroutput by setting the appropriate bits of the command registeras shown in Table 2. Port B can be operated in basic orstrobe mode and is assigned I/O terminals PBo~PB7.Port C Register (6 bits)Port C register is assigned address XXXXXOll. This port isused for controlling input/output operations of ports A and Bby selectively setting bits 2 and 3 of the command registeras shown in Table 2. Details of the functions of the varioussetting of bits 2 and 3 are shown in Table 4. Port C isassigned I/O terminals PCa ~ PCs and when used as portcontrol signals, the 3 low-order bits are assigned for port Awhile the 3 high-order bits are assigned for port B.IITable 4 Functions of port CState~~IALT 1 ALT 2 ALT 3PC 5 Input Output OutputPC4 Input Output OutputPC3 Input Output OutputPC2 Input Output A STB (port A strobe)PC, Input Output A BF (port A buffer full)PCa Input Output A INTR (port A interrupt)B STB (port B strobe)B BF (port buffer full)B I NTR (port B interrupt)A STB (port A strobe)A BF (port A buffer full)A INTR (port A interrupt)ALT 4.• MITSUBISHI"ELECTRIC6-49


MITSUBISHI MICROCOMPUTERSMSL81S6P2048-BIT STATIC RAM WITH I/O PORTS "ND TIMERConfiguration of portsA block diagram of 1 bit of ports A and B is shown in Fig. 1.While port A or B is programmed as an output port, if theport is addressed by an input instruction, the contents of theselected port can be read. When a port is put in input mode,the output latch is cleared and writing into the output latch isdisabled. Therefore when a port is changed to output modefrom input mode, low-level signals are output through theport. When a reset signal is applied, all 3 ports (PA, PB, andPC) will be input ports and their output latches are cleared.Port C has the same configuration as ports A and B in modesAL T1 and AL T2.M5L8156PINTERNALDATA BUSr--lI 1*1. IQDEXTERNAL PINPORT A OR)( PORT BRD PORTWR PORTMD1. WR PORT=IOiM'WR'CE'(PORT ADDRESS SELECTED)2. RD PORT=IOiM'RD'CE'(PORT ADDRESS SELECTED)3. MULTIPLEX CONTROL* 1 STROBE INPUT MODE*2 INPUT MODE* 3 OUTPUT MODE4. MD= 1 : OUTPUT MODEo : INPUT MODEFig. 1Configuration for 1 bit of port A or BTable 5 Basic functions of I/O portsAddress RD WR Function0 1 AD bus +- status registerXXXXXOOO1 0 Command register +- AD bus0 1 AD bus +- port AXXXXXOO11 0 Port A +- AD bus0 1 AD bus +- port BXXXXX0101 0 Port B +- AD bus0 1 AD bus +- port CXXXXX0111 0 Port C +- AD busTable 6 Port control signal levels at AL T3 and AL T4Control Signal Output mode Input modeSTB Input InputSF "L" "L"INTR "H" "L"The basic functions of the I/O ports are shown in Table 5.The control signal levels to ports A and B, when port C isprogrammed as a control port, are shown in Table 6.Cou nter/Ti merThe counter/timer is a 14-bit counting register plus 2 modeflags. The register has two sections: address I/O XXXXX100is assigned to the low-order 8 bits and address I/OXXXXX101 is assigned to the high-order 8 bits. The loworderbits 0 ........ 13 are used for counting or timing. The counteris initialized by the program and then counted down to zero.The initial setting can range from 2 16 to 3FF 16. Bits 14 and 15are used as mode flags.The mode flags select 1 of 4 modes with functions asfollow:Mode 0: Outputs high-level signal during the formerhalf of the counter operationOutputs lOW-level signal during the latter halfof the counter operation6-50 • _.MITSUBISHI..... ELECTRIC


-----------------~MITSU~ISHI MICROCOMPUTERSM5L8156P2048-BIT STATIC RAM WITH I/O PORTS AND TIMERTable 7 Format of counter/timer Mode 1: Outputs square wave signals as in mode 0Mode 2: Outputs a low-level pulse during the finalBit NumberAddressFunctioncount down~T-54 ,l"01--Mode 3: Outputs a low-level pulse during each final+,;:THE LOW-ORDER 8 BITSXXXXX100count down;~, ;':~r T'~ OF THE COUNTER REGISTER------Starting and stopping the counter/timer is controlled byM1,M2 TIMER MODEbits 6 and 7 of the command register (see Table 2 forXXXXX101~~ T"i:" T~ T,THE HIGH-ORDER 6 BITSdetails) . The format and timer modes of the counter/timerTs-T13 OF THE COUNTER REGISTERregister are shown -in Table 7 and Table 8.Table 8 Timer modeThe counter/timer is not influenced by a reset, but countingis discontinued. To resume counting, a start command mustTimer operationbe written into the command register as shown in Table 2.o oWhile operating 2n + 1 count down in mode 0, a high-levelOutputs high-level Signal during the former half of the counter operationOutputs low-level signal dUring the tatter halt of the counter operationsignal is output during the n+ 1 counting and a low-level signal(mode 0)is output during the n counting.Outputs square wave signals as in mode 0 (mode 1)oo-------------------Outputs a low-level pulse during the final count dowm(mode 2)------------------Outputs a low-level pulse during each final count downABSOLUTE MAXIMUM RATINGS(mode 3)Symbol Parameter ConditionsVee Supply voltageVI Input voltage With respect to vssVa Output voltagePd Maximum power dissipation Ta=25°CTopr Operating fre~-air temperature range ,Tstg Storage temperature rangeLimitsUnit-0.5-7 V-0.5-7 V-0.5-7 V1.5 W0-70 'c-65-150 'cRECOMMENDED OPERATING CONDITIONS (Ta=0-70'C, unless otherwise noted)LimitsSymbol Parameter UnitMin Nom MaxVee Supply voltage 4.75 5 5.25 VVss Power-supply voltage 0 Vt----V IL Low-level input voltage -0.5 0.8 VV IH High-level input voltage 2 Vcc+O.5 VELECTRICAL CHARACTERISTICS (Ta=0-70'C, Vcc=5V+5%, unless otherwise noted)SymbolParameterTest conditionsMinLimitsTypMaxUnitV OHHigh-level output voltageVss=OV, IOH=-400~A2.4VVOLLow-level output voltageVss=OV, 10L =2mA0.45 VIIInput leak currentVsS=OV,VI=O-VCC-1010 /-LAII(eE)Input leak current, CE pinVss=OV, VI=O-VCC-100100 /-LA102Output floating leak currentVss=OV, VI=O. 45-Vcc-1010 /-LACiInput capacitanceVIL =OV, f=l MHz, 25mVrms, T a=25°C10 pFCi/oInput/output terminal capacitanceVI/OL =OV, f=l MHz, 25mVrms, T a=25°C20 pFleeSupply current from VccVss=OV180 rnANote 1Current flowing into an IC is positive, out is negative.• MITSUBISHI.... ELECTRIC6-51


MITSUBISHI MICROCOMPUTERSMSL81S6P204'8-BIT STATIC RAM WITH I/O PORTS AND TIMERTIMING REQUIREMENTS (Ta=O~70'C, Vcc=SV±S%, unless otherwise noted)<strong>Al</strong>ternativeSymbol Parameter Test conditionssymboltSU(A-L) Add,ress setup time before latch tALth(L-A) Address hold time after latch tLAth(L-RWH) Read/write hold time after latchtw(L) Latch pulse width tLLth(RW-L) Latch hold time after read/write tCLtW(RWL) Read/write low-level pulse width tcctsu(o-W) Data setup time before write ~towth(w-o) Data hold time after write twotW(RWH) Read/write high-level pulse width tRYtSU(P-R) Port setup time before read t pRth(R-P) Port hold time after read tRPtW(STB) Strobe pulse width tsstSU(P-STB) Port setup time before strobet LCtpssth(STB-P) Port hold time after strobe tpHStw ( ~H) Timer input high-level pulse width t2tw ( ~ L) Timer input low-level pulse width t,t c ( ~) Timer input cycle time tCYCt r( ~ ) Timer input rise time trtf( ~) Timer input fall time tfLimitsUnitMin Typ Max50 ns80 ns100 ns100 ns20 ns250 ns150 ns0 ns300 ns70 ns50 ns200 ns50 ns120 ns120 ns80 ns320 ns30 ns30 nsSWITCHING CHARACTERISTICS (T~=O~70'C, Vcc=SV±S%, unless otherwise noted.)NoteSymbolParametertPXV(R-OQ) Propagation time from read to data output tROtPZX(A-OQ) Propagation time from address to data output tADtPVZ(R-OQ) Propagation time from read to data floating (Note 7) t ROF'tPHL(W-P)tPLH(W_P)tPLH(STB-BF)tPHL(R-BF)IpLH(sTB,INTR)tpHL( R,INTR)tPHL(STB-BF)tPLH(W-BF)tPHL(W-INTR)tpHL( ~-OUT)tpLH( ~ -OUT)tPZX(R-OQ)Propagation time from write to data outputPropagation time from strobe to SF flagPropagation time from read to SF flagPropagation time from strobe to interruptPropagation time from read to interruptPropagation time from strobe to SF flagPropagation time from write to SF flagPropagation time from write to interruptPropagation time from timer input to timer outputpropagation time from read to data enableMeasurement conditions c= 150pFMeasurement conditions of note 6 are not applied.<strong>Al</strong>ternativetwptwptSBFtRBEtSItROItSBEtWBFtWIhLtTHtRDEsymbolTest conditionsLimitsUnitMin Typ Max170 ns400 ns100 ns400 ns400 ns400 ns400 ns400 ns400 ns400 ns400 ns400 ns10 ns6-52• ,MITSUBISHI.... ELECTRIC '


MITSUBISHI MICROCOMPUTERSM5L8156P2048-BIT STATIC RAM WITH I/O PORTS AND TIMERTIMING DIAGRAM (reference level, high-level=2V, low-level=O.8V)Basic outputPORT~filtwCRwLlXtPHUW-p)tplHCW-P)~f- ~LtWCRWH)thCl-RWH)thcw-o)101M \CE J~ALE)ADDRESSV.lK.K jrtsuCA-Ll thCl-A) tsuco-w)~k-twCLl\JDATAV-thCRW-LlIIBasic inputPORT)tSUCP-R)~'trtwCRwLlK---r- thCR-P)Jl'- ~~JtWCRWH)IItCCl-RW)tpxvCR-OO)tCCRw-Ll101M'\I(tpZXCR-OO)~I---tpXZCR-OO)\CEI)(ADDRESStpZXCA-O)~tr n~ ~tr ):I'DATA~ K=ALEItsuCA-LltwCLlI\~thCL-A)k'• MITSUBISHI.... ELECTRIC6-53


MITSUBISHI, MICROCOMPUTERSMSL81S6P2048-BIT STATIC RAM WITH I/O PORTS AND TIMERStrobed outputPORT ____________________ ~~ __________________________________INTRBFStrobed inputPORTBFINTRTimer (Note 1)TIMER INTIMER OUTPULSE MODENoteTIMER OUT ,SQUARE WAVE MODE -------____ J (Note 2)1 : The wave form is shown counting down from 5 to 1 .2 : As long as the Ml mode flag of the timer register is athigh-level, pulses are continuously output.6-54• MITSUBISHI.... ELECTRIC


MIC-ROCOMPUTER SUPPORT SYSTEMS


MITSUBISHI MICROCOMPUTERSPC4000DEBUGGING MACHINEDESCRIPTIONThe PC4000 is a debugging machine for use with single-chipmicrocomputers. It is intended for use as a general purposedebuggingmachine for support of single-chip microcomputerhardware and software.FEATURES• Usable for RAM-based program debugging• Connectable to the user system via a 0 I L socket orconnector• Built-in EPROM (2716,2732) writer function• Uses serial data transfer for two-way data transfer withthe host machine (e.g. PC9000 cross assembler machine)• Usable with a variety of single-chip microcomputers bysimply replacing a single board• Print out of internal memory contents is possible bymeans of an external printer• Easy-to-carry-about in its compact case, provided withan angle standCONFIGURATIONThe PC4000, as shown in the block diagram, consists of thefollowing hardware elements.(1) M5L8085AP monitor CPU(2) Serial data input/output interface circuit(3) EPROM writer circuit(4) Program RAM (10 bits x 4K)(5) Keyboard and LED display circuits(6) Power supplyThe PC4000 is used in conjunction with a dedicatedboard which allows interface of the PC4000 with the objectmicrocomputer under development. The dedicated boardinsertion access window is located on the right side of thePC4000. In addition, each dedicated board stores thecontrol program for the monitor CPU. Therefore, when themicrocomputer type ischanged, the PC4000 can bemodified to suit the new type by merely changing the singlededicated board.APPLICATIONSHardware and software development and program debuggingfor single-chip microcomputer systems.II• MITSUBISHI"'ELECTRIC7-3


MITSUBISHI MICROCOMPUTERSPC4000DEBUGGING MACHINEFUNCTIONAL DESCRIPTIONObject programs developed on such devices as the PC9000cross assembler machine are sent to the PC4000 via theserial input/output interface. The serial data transmissionrate can be selected from 1200bps to 9600bps and theinterface is a 20mA ,current loop type. The transmissionformat is Intel-compatible hexadecimal.The data in the program memory is executed by theevaluation CPU on the dedicated board. In addition, thismemory contents can be written into 2716 or 2732EPROM devices or data can be read out of such devices viaa 24-pin D I L socket.The keyboard consists of 12 function keys and 16numerical' keys as well as a single entry key. The LEDdisplay is an 8-digit display of 7-segment LED elementsused to display data for reference while processing isperformed.BLOCK DIAGRAMEPROM27162732PROM WRITERINTERFACEM5L8041A-006PKEYBOARDDISPLAYM5L8279p·sKEYBOARDPROGRAMMEMORYM5T4044PX 10SERIAL I/OINTERFACEM5L8251 Ap·5r----- ------- ----------IIIIDEDICATED BOARDIIIIL------------ i------------I -IUSER SYSTEM7-4• MITSUBISHI"ELECTRIC


MITSUBISHI MICROCOMPUTERSPC4000DEBUGGING MACHINEKEY FUNCTIONS (BASIC FUNCTIONS ONLY)SPECIFICATIONSSymbolNameFunctionItemSpecificationSENDData transmit keyConverts program memory data to serialdata and transmits to an external deviceMethodThe system is used with a dedicated board whichincludes the evaluation chip to perform in-circuitemulationRCVPROGData receive key(EPROM)Program keyReceives serial data and writes this datainto program memoryWrites program memory data into theEPROM inserted in the socketApplicablemicrocomputersM58840- XXXPM58494- X X X PM58496-XXXPM5L8048-XXXPM5L8049-XXXPand all other, Mitsubishi single-chip microcomputersLOAD(EPROM)Load keySends data from the EPROM insertedin the socket to program memoryProgram RAMBuilt-in. 4K x 10 bits (250ns access time)PRTEXMPEXMRPrint keyExamine programmemory keyExamine register keyData transmit to the optional printerVerification/correction of programmemory contentsVerification/correction of registercontentsControl CPUBuilt-in EPROMwriter circuitDisplayInputM5L8085APUsable with 2716 or 2732 devices7-segment LED. 8 digitsKey switches: Commands: 12 keysNumerical: 16 keysEntry: 1 keyEXMMRESRUNBRKSTEPO-FENTExamine memory keyReset keyR un (execute) keyBrea k po i nt set keySingle step keyNumerical keysEntry keyVerification/correction of RAM contentsReset of program counterRe-start of program execution at thespecified address (real time)Sets the break pOint addressExcutes the program one step at a timeUsed for input of address and dataEffectively enters input numerical dataInterfaceMonitor functionUser systemconnectionDimensionsQ) 20mA current loop serial input/output interface4800bps. full deplex. one line(Selectable from 1200 to 9600bps)® Centronix-compatible panillel interface. one lineMonitor programs for the appropriate objectmicrocomputers are written into the two M5L2732Kdevices mounted on the dedicated board.· Basic FunctionsTransfer of RAM data with an external systemRead and write of EPROM data· Verification/correction of the built-in programmemory (RAM) contentsExecution and halt at any arbitrary program addressSingle-step execution of programsVerification/correction of internal registers. memory.flagsInput/output connections to the dedicated board bymeans of a cable364 X 257 X 85 mm (excluding handle and key switch topsIIPower supply-Operatingt(lmperatureStoragetemperatureAC 100V5-40·C-20-60·C100VA• MITSUBISHI"'ELECTRIC7-5


MITSUBISHI MICROCOMPUTERSPC4000DEBUGGING MACHINEPC4000 CONFIGURATIONTO EXTERNAL PRINTERDEDICATED BOARD(4-BIT SINGLE-CHIP)20mACURRENTLOOPTO PC9000 48do bpsCROSS .;.-----,ASSEMBLERUSERSYSTEMPOWER SUPPLYDEDICATED BOARD(FOR USE WITH MELPS8-48)PCA 8400,PC 40007-6• MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSPC9000CROSS ASSEMBLER MACHINEDESCRIPTIONThe PC9000 is a cross assembler mach ine. It is capable ofconverting programs for the Mitsubishisingle-chip microcomputerswritten in assembler language to machine language.In addition, it can perform such debugging functionsas disassembly and act as an EPROM writer.FEATURES• Input of the source program from the keyboard• An efficient screen· editor allows editing of sourceprograms• Program dump and load to the mini-floppy disk• Object data write/read for 2708, 2716 and 2732EPROM devices• Listing using a Centronix-compatible printer is possible• Data transmission is possible to the PC4000 debuggingmachine• Usable with all types of Mitsubishi single-chip microcomputers• Compact, desk-top designAPPLICATIONSoftware development support for Mitsubishi single-chipmicrocomputers.FUNCTIONThe PC9000 as shown in the configuration diagram consistsof the following hardware(1) Control CPU and bootstrap ROM(2) 48K byte RAM(3) 2K byte display screen RAM(4) 9-inch CRT display circuit(5) EPROM writer ci'rcuit(6) ASCII keyboard(7) Hardcopy output by means of an internal mini-printercircuit or an external printer interface circuit(8) Floppy disk controller (two mini floppy disk drives)(9) Parallel input/output interface circuit (two lines)(10) Power supplyAn M5L8085AP is used as the control CPU. The'keyboard, CRT, mini-floppy disk drives, and printer interfacesare connected by means of a bus line. The keyboard isused for input of commands to the monitor and sourceprogram data verification. The 9-inch green CRT displayscreen is capable of displaying 24 rines of 80 characters. Asa printer a 20 column mini-printer is built-in to the PC9000in addition to the ability to use an 80 column printerhaving Centronix compatibility via an interface which isavailable. The built-in mini-printer may be used to outputII• MITSUBISHI"ELECTRIC7-7


MITSUBISHI MICROCOMPUTERSPC9000CROSS ASSEMBL~ER MACHINEthe disassembly results while the external printer may beused to output the assembly listing as well as disassemblylisting.FUNCTIONAL DESCRIPTIONThe PC9000 contains the assembler, disassembler, sourceeditor, and EPROM writer functions required for softwaresupport of microcomputers. These functions are summarizedin the Table.FunctionEffectApplicable devicesAssembleDisassembleSource editorPROM writerSource input: keyboardoutput: printer, EPROM, data transfer (with debuggingunit)Disassembly of the specified fileOutput: 20 column printer, externa! printerDeletion, insertion, modification, character search, andscreen editingEPROM erase check, write, verification, read<strong>Al</strong>l 4-bit single-chip PMOS, and CMOS microcomputersM5L8048, M5L8049 and M5L8041A 8-bit single-chipmicrocomputersSame as aboveSame as aboveMSL2708K, MSL2716K, MSL2732KPC9000 CONFIGURATIONCRTCONTROLLERAC100VCENTRONIX-COMPATIBLE• MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSPC9000CROSS ASSEMBLER MACHINESPECI FICATIONSStructureCPUItemDesktop-type, single cabinetMitsubishi M5L8085AP (2.45 MHz clock)SpecificationIC memoryMemory deviceDisplayKeyboardDedicated printerPrinter interface2K byte ROM (bootstrap area), 48K-byte DRAM, 2K-byte VRAMMini floppy disk x 2 drives, double-sided, double-density9-inch green CRT display, 80 lines x 25 characters·Modified ASCII specifications, 2-key lockout5 x 7 dot Matrix thermal printer, 20 columns. 2 lines/s. Paper width: 60mm.Centronix, parallel interfaceInterface connector: 36-pin DDK AmphenolSerial input/output interface20mA current loop (2 lines)Data transfer format MELPS 85 Hexadecimal (equivalent to Intel Hexadecimal)Applicable microcomputersOuter dimensions and weightMELPS 8-48 (M5L8048-XXXP. M5 L8049- X X X P and others)MELPS 4 (M58840-XXXP and others)MELPS 41 (M58494- XX XP)MELPS 42 (M58496-XXXP and others)Desk top-type 470(W) x 290(H) x 490( D), 17 kgPower supply AC 100V±10% 50/60HzKEYBOARD ARRANGEMENTII,----------, POWERONtj(SPACE)• MITSUBISHI;"ELECTRIC7-9


MITSUBISHI MICROCOMPUTERSPC9100IS-BIT CPU SOFTWARE DEVELOPMENT SYSTEMDESCRIPTIONThe PC9100 is a software development support for theMELPS 86 and PCA8600 series. As this has floppy diskdrives and a built-in EPROM ,Programmer, a software developmentsupport for the MELPS ·86 is performed by onlyconnecting a CRT terminal on the market.The operation system (OS) adopts the propagated®CP/M-86 T . M . and CP/M-80®, therefore many softwaresprogrammed for CP/M are usable.. In addition, with a use of M5L8086S in-circuit emulatorPC9110, the operation from a source programming ofMELPS 86 to a hardware debugging is executed continuously.FEATURES• Compatible with PCA8601 monitor program• Adoption of CP/M-86, CP/M-80 for OS. Select any OSby a monitor program.• Capability of executing a developed software for 8080A/8085A and of developing an 8085A software when theCP/M-SO is selected.• Easy system expansion caused by system bus whichadopts IEEE-796 bus and 4 opened card cages.• Standard 2 drives for double-sided double-density floppydisk (Capacity of 1.2M bytes).• Applicable drive for double-sided double-density,double-sided single-density ,single-sided single-densitydisks by the switch on the rear panel.• Capability of programming 2 of 16-bit data at a time bya built-in EPROM programmer (corresponds toM5L2716K, M5L2732K, M5L2764K) .• Usable CRT device, which contains RS232C serialinterface, on the market• Capability of connecting a centronics printer• Capability of connecting the M5L8086S in-circuitemulator PC9110• One built-in RS232C serial interface for general purpose• RAM size ........................... 12K bytes• AC 100V• Compact, light weightAPPLICATION• Software development support for MELPS 86• Software development support for MELPS 85• Personal computer• Device for data analysis and management• Base machine for each dedicated systemNote 1. ® CP/M is a registered trade-mark of Degital Research Inc.2. lEE E-796 bus is a system bus for microcomputers wh ich are thestandardized Intel ® multi bus by IEEE.® multi bus is a registered trad;-mark of Intel.7-10• . MITSUBISHI..... ELECTRIC·


MITSUBISHI MICROCOMPUTERSPC9100IS-BIT CPU SOFTWARE DEVELOPMENT SYSTEMFUNCTIONThe PC9100 adopts multi bus as a system and mounts aPCAS601 CPU board, PCAS602 64K RAM board,PCAS603 floppy disk controller board (includingM5LSOS5A) of PCA S600 series and an I/O board forPC9100. 4 multi bus compatible boards are in the card cageslot for easy system's expansion and exclusive.2 built-in double-sided double-density floppy disks areprovided. The second drive (Drive B:) can select eitherdouble-sided single-density or single-sided single-density bythe switch on the rear panel. After selecting either singledensity, the CP/M lets the BIOS work automatically byaccessing each Drive as C:, D:.The EPROM programmer consists of 2 DI L sockets for2S-pin and 2 EPROMs are programmed in a 16-bitmicrocomputer object. Programmable EPROMs areM5L2716K, M5L2732K, M5L2732A type and M5L2764K.I/O functions are: (1) CRT interface (RS232C standard,Serial operation, 25-pin connector) (2) Printer interface(TTL level, Centronics 36-pin champ connector) (3)PC9110 interface (RS232C standard, Serial operation,25-pin connector) (4) General purpose serial interface (RS232C standard, Assignation to RDR: PUN: In CP/M, 25-pinconnector)After turning on the PC9100, the M5LSOS6S on thePCAS601 will be a bus master and executes a monitorprogram written in the ROM on the PCAS601. After this, ifthe G(GO) command is executed, the system will be inCP/M-S6 or CP/M-SO mode. When it is the CP/M-S6 mode,the system works considering the M5LSOS6S as master, andcommands consist of the CP/M-86, SOS6 assembler, SOS6debugger and application software for CP/M-S6 which is onthe market are able to execute.When it is the CP/M-SO mode, the commands consist ofthe CP/M-SO, SOSO assembler, SOSOdebugger and applicationsoftware for the CP/M-SO which is on the market areable to execute.The operation from the OS to the monitor is executedby the reset switch.BLOCK DIAGRAMI SERIALLTI BUS I CPU PORTM5L8086S M5L8251AP'r:TERRUPT'0'l11 PARALLELONTROLLER PORTM5L8259AP M5L8255AP-5PCA8601IINTERFACE FOR CRTCENTRONICSPRINTER INTERFACEaEX PANSIONCA RD CAGE(4)III REFRESH I 64KCONT-ROLLERPCA8602MEMORYBYTES (WITHPARITY BIT)M5K4116PM5W:7~~.02P I '--~I CPU IDENSITY NO.1M5L8085AP-jIDMA CONTROLLER MEMORY IM5L8257P-51 EPROM, SRAMSERIAL PORTM5L8251APx 21/0 BOARD FOR PC9100PCA8603PARALLEL IPORTM5L8255APXlc::::::::J c:=:J DC/DCCONVER-ROM H ROM L TERSOCKET SOCKET etcFDDPROM PROGRAMMER MODULE-------FDD DOUBLE-SIDED DOUBLE-DRIVEJDOUBLE- SIDED DOUBLE IDENSITY NO.2BIISELECTION SWITCHOF FLOPPY DISK TYPEPC9110 INTERFACEGENERAL PURPOSESERIAL INTERFACE• MITSUBISHI.... ELECTRIC7-11


MITSUBISHI MICROCOMPUTERSPC910018-81l' CPU SOFTWARE DEVELOPMENT SYSTEMFUNCTION EXPLANATION (According to CP/M, CP/M86, Mitsubishi original utility SIW)FunctionAssemblerDebuggerRPOM programmerData communicationEditorEffectsSource input: Sou rce fi Ie created by key board inputoutput: list, EPROM, Data communication with emulatorSoftware debugger:Software debugger:Supporter in CP/M-86For Application SIW in CP/M-86Supporter in CP/M-80Write, read, verification of EPROMFor Application SIW in CP/M-85(Capability of programming upper bytes and lower bytes at the same time for 8086)Bi-directional data communication with an external device in file baseSupporter in CP/MApplication devices• 8086• 8085A• 8086• 8085AM5L2716KM5L2732KM5L2764KRS232C standardApplicable for all usesExecution ofapplication SIWRich applicable SIW which on the marketego "CIS COBOL86", "PASCAL/M-86" etc. which are on the market as the high quality language for 8086 can beexecuted in the PC91 00. Likewise, the high quality editor (Word star etc.) on the market can be used beside thestandard editor.• 8086• 8085ASPEC I FICATIONHardware SpecificationItemSpecificationStructureDesk top. single cabinet (External CRT, Keyboard, printer)CPUMitsubishi M5L8086SMitsubishi M5L8085AP4.9152MHz2.4576MHzPCA8601 Program memory 16K bytesRAM16K bytesIC memory PCA8602 RAM 64K bytesPCA8603 Program fT''lmory 4K bytesRAM2K bytesMemory deviceCRT interface2 double-sided double-density floppy disks (Single-sided single density is also used by setting the switch on the rear panel)Serial interface (The electrical characteristics and connector are compatible with the RS232C standard)Transmit speed ..... 9600BPS standardPrinter interfaceCentronics parallel interface (The DDK unphenol 36-pin is used for a connector)Interface for PC9110 in-circuitemulator controllerSerial interface (The electrical characteristics and connector are compatible with the RS232C standard)Transmit speed .... ; 9600BPSGeneral purpose serial I/O interfacePROM programming" deviceApplicable microcomputerCapable expansion areaOuter dimensionsOperating temperatureOne port (The electrical characteristics and connector are compatible with the RS232C standard)Transmit speed ..... Selectable from 120012400/4800/9600BPS 9600 BPS standard2 multi devicesProgrammable into M5L2764K, M5L2732A type, M5L2732K, M5L2716KME LPS 86, ME LPS 854 of multi bus boardsDesk top type 420(W) x 450(D) x 260(H) mm5°C -40°C7-12• MITSUBISHI"ELECTRIC


MITSUBISHI MICROCOMPUTERSPC910016-BIT CPU SOFTWARE DEVELOPMENT SYSTEMSoftware SpecificationMonitor programItemSpecificationMonitor for 8086 which is compatible with the one on the PCA8081Operation systemCP/M-86CP/M-80General purpose O.S. for 8086 of Degital Research Inc.General purpo.se O.S. for 8080 of Degital Research Inc.Utility software(8086 base)Utility software(8080 base)ASM86. CMDDDT86. CMDSTAT. CMDSUBMIT. CMDPIP. CMDGENCMD. CMDED. CMDPROM. CMDDDFMTASM.COM'DDT. COMSTAT. COMSUBMIT. COMXSUB.COMPIP. COMLOAD. COMED. COMDUMP. COMMOVCPM.COM8086 AssemblerCP/M86 DebuggerFile status utilityBatch management utilityFile exchange utilityCMD file generating utilityEditor for p~ogram generatorPROM programmer controller programDisk initialization and disk copy8080 AssemblerCP/M80 DebuggerFile status utilityBatch management utilityExpansion of SUBMIT. COM utilityFile exchange utilityCOM file generating utilityEditor for program generatorHex dump utilityLibraryBIOS.A86, DEBLOCK. LIB, BIOS.ASM, DUMP.ASMMemory MapSystem map00000,6..------,FFFFF'6 .....___......8086 map8085 mapI IIIIIIIIL I_____.JII~ SYSTEM AREA r·:\\~IINHIBITED AREA _ LOCAL MEMORY AREA 0 BLANKNote 1. Broken line means that addresses are the same between each area.Solid line means that each area has the different address from others.2. The area marked with' will be changed by an installation of a control register..MITSUBISHI.... ELECTRIC7-13


MITSUBISHI MICROCOMPUTERSPC9001CPMCP/M SOFTWARE FOR PC.OOODESCRIPTIONThe PC9001 CPM is an option board to turn the crossassemble machine PC9000 to a CP/M® machine.This is capable of developing the 8085 software andexecutions of a software for a CP/M and a user programwith the PC9000. The CP/M of PC9001 is designed for 48Kbytes CP/M Version 2.2.This software must be used following the softwarecontract.Note: ® CP/M is a registered trade-mark of Digital Research Inc,FEATURES• Execution of a CP/M on the PC9000• Functions of a debugger and an assembler of 8080A• Application program which operates on a CP/M of whichmemory capacitor is below 48K• Developing and operating of a user program on thePC9000• Opened internal miniprinter ~s a user list device• Selectable letters (CAPITAL/small) by F3 key• Usable internal serial interface as RDR:, PUN:• Functions of a standard CP/M editor and' a PC9000original screen editor• Used for a high quality EPROM programmer by aninternal EPROM programmer and an option con'trolprogramAPPLICATIONS• Supporting develop machine for MELPS 85• Personal computer• Data communication terminalFUNCTIONSThe PC9001CPM contains the EPROM (M5L2716K orM5L2732K) that programs a boot strap program and abasic operation system (BIOS) for CP/M. A floppy disk .programmed of a CP/M and an application software, andmanuals are also packed in the PC9001 CP/M carton.Following the manual, exchange the EPROM on thePC9000 main board. The CP/M then initiates when asystem starts by the disk. The PC9000 original disk andprescribed disk ar~ compatible after changing a ROM.7-14 • MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSPC9001CPMCP/M SOFTWARE FOR PC9000SPECIFICATIONItemSpecificationCP/M Version Version 2.2RAM siLeConsole (CON)Paper tape reader (RDR:)Paper tape punch (PUN:)List device (LST:)48K bytesBuilt·in CRT device and keyboard of the PC9000Built·in ME LCOM 70 interface of the PC9000(Hand shaking operation using a data terminal ready. DTR)Built·in PC4000 interface of the PC9000(Hand shaking operation using a data set ready. DSR)Centronics external printer (LPT:) Built·in miniprinter of the PC9000 (U L1:) LPT = standard assignFloppy disk storage 2 x 320K bytes (A: and B)Key board• Capital/small letter selection by [E] keyPROM programmer • File load, file save, edit. PROM program, PROM read, verify, padding, block moving• 8K bytes work area• Target ROM (2708/2716/2732)Miscellaneous • Time-out detector for printer ready• Automatical warm boot operation by a key input when a programming is begun.in the write protected disk• Automatically effected DTR output of the ME LCOM 70 interface by a warm bootAPPLICATION SOFTWARE LIST IN THE PC9001CPMProgram Function SupplementEDIT Screen Edi tor PC9000 original editorED*Line EditorASM* Assembler for 8080LOAD*Modification of execution styleDDT* Debugger for 8080PROM Programming control The program to transfer an assemble result to a PROM by a built-in PROM programmer of PC9000. (Functionsfor 2708/16/32of padding and block transfer are progra~med.)DUMP* Hex Dump Source program is attachedIIPIP*STAT *SUBMIT*XSUB*File handlingSystem status indicatorSubmit fi18' managementOptional SUBMITCMNA 1 ME LCOM 70 communication The communication of object codes by the ME LCOM 70 in the Intel HE X formatCMNA 2 PC4000 communication The communication of object codes by the PC4000 in the Intel HEX formatGeneral purpose fi IeMSScommunicationThe communication of file data with another CP/M machineDISKCOPY Copy of disk contents Copy the disk contents from A to BDDBI Disk initialize Initialization of PC9000 formatting for a disk in the marketThe program marked with * is the utility progra~ for CP/M.• MITSUBISHI"ELECTRIC7-15


MITSUBISHI MICROCOMPUTERSPC9004INTERFACE. CABLE BETWEEN PC9000 AND PC4000DESCRIPTIONThe PC9004 is an interface cable to connect the crossassemble PC9000 and the debugging machine PC4000 byserial interface.FEATURES• High speed data communication for object codes ofassembled and debugged results by, connecting thePC9000 and the PC4000 with the serial interface.• File communication by a. serial interface between twoPC9000s (when CP/M@ option is used)Note: ® CP/M is a registered trade-mark of D'igital Research Inc.SPECIFICATIONItemConnectorLinePin connectionRS232C type connector7 linesSpeci ficat ionConnector A ----Connector 89 ................... 1010 ................... 911 ......... _ ......... 1212 .......•.. _ .. _ ..... 1113 ................... 1414 .......•........... 1322 ................... 22FUNCTIONSThe PC9004 makes it possible to execute a data communicationused with built-in current loop interface of thePC9000 and the PC4000. For example, to send a 4K bytesobject code in Intel HEX format (at 9600 baud), it takesapproximately 17 seconds.7-16 • MITSUBISHI"ELECTRIC


MITSUBISKI MICROCOMPUTERSPC900SPRINTER INTERFACE CABLEDESCRIPTIONThe PC9005 is an interface cable to connect the crossassemble machine PC9000 or the debugging machinePC4000 and a centronics printer.FEATURES• Capability of outputting an assembled list or a disassembledlist by connecting the PC9000 and a printer.• Capability of outputting a disassembled list or p tracedresult at the 8080 software debugging by DDT when aCP/M is converted to the PC9000.• Capability of outputting a disassembled list whichcorresponds to each microcomputer, an internal memorydump list etc. by connecting the PC4000 and a printer.SPECI FICATIONPin. No.12-9101112313219-29SignalContentSTB Strobe output signal of data00-0 7 Data output signal to a printer.ACK Input signai of data acknowledgementBUSY BUSY input signal from a printerP.EMP Input signal notifying a printer paper emptyRST Output signal to initiate a printerFAULT Input signal to notify printer errorsGNO GroundFUNCTIONSThe PC9005 is designed based on the centronics specificationand is used as an interface cable between the PC9000or the PC4000 and a centronics printer.II.•. MITSUBISHI..... ELECTRIC7-17


MI.TSUBISHI MICROCOMPUTERSPCA4040MELPS 740 DEDICATED BOARD (MS0740-XXXSP, M S0741-XXXSP)DESCRIPTIONThe PCA4040 MELPS 740 dedicated board is for use withthe PC4000 debugging machine for the M50740-XXXSP, andM50741-XXXSP single-chip 8-bit microcomputer, and it isused by inserting the board in the PC4000 cabinet. 'FEATURES• Connection to user's system by a flat cable• Single-step operation and breakpoint operation capabilityfrom the PC4000 debugging machil)e keyboard. Debuggingfunctions such as confirmation and modificationof internal register contents.APPLICATIONSDevelopment of hardware and software for systems usingthe MELPS 740 (M50740-XXXSP and M50741-XXXSP) single-chipmicrocomputer.CONFIGURATIONAs can be seen from the block diagram, the PCA4040 consistsof the following hardware.(1) Evaluation chip (M50740-000SP) and peripheral circuit(2) EPROM with the PC4000 monitor program(3) Single-step and breakpoint control circuit(4) Program memory interface circuit(5) Input/output buffer/latch circuitThe board and user system can be connected by means ofan accessory cable.FUNCTION. The debugging machine PC4000 operates as a debuggingmachine for MELPS 740 microcomputers using the monitorprogram contents of a ROM mounted on the dedicatedboard. The evaluation chip (M50740-000SP) loaded on theboard executes the program stored in the program memory.The internal status of the evaluation chip is read out undermonitor CPU control when halted by single-step operationand breakpoint operation.SPECIFICATIONSItemApplicable microcomputerClock frequency iCFApplicable debuggingmachinePower supplyConnection to user'ssystemDebugging functions(contents of monitor EPROM)SpeCificationM50740-XXXSP, M50741-XXXSP4MHzPC4000(connected by a card edge connector J3)Supplied by PC4000Accessory cablee Program execution from any address,stop and single-step operatione Confirmation and change of programRAM contentse Confirmation and modification of RAM datain evaluation chip and verification and modificationof following registers and flags:• Program counter• Index register X• Index register Y• Stack pOinter• Accumulator• Processor status registereOata programing to EPROM and reading7-18 • MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSPCA4040MELPS 740 DEDICATED BOARD (MS0740-XXXSP,MS0741-XXXSP)BLOCK DIAGRAMCONNECTOR FOR TARGET SYSTEM CONNECTIONS I J 1..---PORTADDRESSDECODER24~H24 t1 ')PORT INPUTBUFFERI) JPORT LATCHDIRECTION3./ ~PORT OUTPUTBUFFERPORT DATALATCH" "ADDRESS 16LATCH'LXln8 t 8fJI8 12Po P1 P 2 P 3,4CPU M50740-000P~ f----'TIMING 3 1GENERATORCIRCUITt"I \I I --'21, 1 ICl)a:Cl)wwOa:o00ow «0 I--h2r---Z- '-- O...Ja:i=OwOa:133::J1-OZr-- OwO a.a:O12,1.-RESET,INTERRUPT ICONTROL~+ ~DATA BUS ADDRESSBUFFERBUS BUFFERCPUCONTROL ---' BREAK DATA/PROGRAMCIRCUIT CONTROL MEMORYr-- MEMORY ~ADDRESSREAD GATEI\r----...J~a?!::: ~«I-:JwZ nO cooo a:O!:!:IDataJ)CONTROLBUSBUFFER1,-l -,JAddressDATA BUS ADDRESS IBUFFER BUS BUFFER MONITOR ROM(M5L2764K)11 2f)J8" ,8,1-' 12 V 5,3,1..-GENERATORCLOCKCIRCUITICONNECTOR(J2)L..-IICARD EDGE CONNECTOR FOR PC4000 CONNECTION-, J 3• MITSUBISHI.... ELECTRIC7-19


MITSUBISHI MICROCOMPUTERSPCA4060MELPS 760 DEDICATED .BOARD (MS0760-XXXP, MS0761-XXXP)DESCRIPTIONThe PCA4060 MELPS 760 dedicated board is for use withthe PC4000 debugging machine for the M50760-XXXP andM50761-XXXP single-chip 4-bit mi~rocomputers, and it isused by inserting the board in the PC4000 cabinet.FEATURES• Connection to user's system by a flat cable• Single-step operation and breakpoint operation capabilityfrom the PC4000 debugging machine keyboard. Debuggingfunctions such as confirmation of internal registercontents.APPLICATIONSDevelopment of hardware and software for systems usingthe MELPS 760 (M50760-XXXP, M50761-XXXP) single-chipmicrocom puter.CONFIGURATIONAs can be seen from the block diagram, the PCA4060 consistsof the following hardware.(1) Evaluation chip (M50760-000P) and peripheral circuit(2) EPROM with the PC4000 monitor program(3) Single-step and breakpoint control circuit(4) Program memory interface circuit(5) Input/output buffer/latch circuitThe board and user system can be connected by means ofan accessory cable.FUNCTIONThe debugging machine PC4000 operates as a debuggingmachine for MELPS 760 microcomputers using the monitorprogram contents of a ROM mounted on the dedicatedboard. The evaluation chip (M50760-000P) loaded on theboard executes the program stored in the program memoryin the PC4000 debugging machine.The internal status of the evaluation chip is read out undermonitor CPU control when halted by single-step operationand breakpoint operation.SPECIFICATIONSItemApplicable microcomputerICFClock frequencyICRApplicable debuggingmachinePower supplyConnection to user'ssystemDebugging functions(contents of monitor EPROM)SpeCificationM50760-XXXP, M50761·XXX P400kHz200-400kHzPC4000(connected by a card edge connector J3)Supplied by PC4000Accessory cable• Program execution from any address,stop and single-step operation• Confirmation and cliange of programRAM contents• Confirmation and modification of RAM datain evaluation chip and verification and modificationof following registers and flags:,• Program counter• A register and carry• B register• Data pOinters (X, y)• Data programing to EPROM and reading7-20 • MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSPCA4060MELPS 760 DEDICATED, BOARD (M'S0760-XXXP. MS0761-XXXP)BLOCK DIAGRAMICONNECTOR FOR TARGET SYSTEM CONNECTIONSI9 4PORT EMULATION CIRCUIT49 4RESET Do-Os F o-F3CPU M 50760- OOOPCLOCKGENERATORCIRCUITINSTRUCTIONINSERTERCIRCUIT"1CNVSS,XOUTDIINSTRUCTION INSTRUCTION ADDRESSINPUT GENERATOR BUS TIMINGBUFFER CIRCUIT BUFFER GENERATORCIRCUITL11 ~ ~ tRUN/STEPCONTROLCIRCUIT ~I 1 1I2'-......TO PARTS ONBOARDDYNAMICCONTROLPROGRAMPORT FPROGRAMCOUNTERBUFFERCOUNTERLATCHLATCH•8 ,INSTRUCTION IDECODERREGISTERRAM INPUTCIRCUIT)COMPARATOR ADDRESS_~ 101010I r ( (l CYCLE I MACHINE MONITORDECODERJ~ MONITOR IBREAK ROM ROMCONTROL #1 #2CIRCUITt)103"10128ICARD EDGE CONNECTOR FOR PC4000 CONNECTIONSI J3• MITSUBISHI.... ELECTRIC7-21


MITSUBISHI MICROCOMPUTERSPCA4360MELPS 760 EVALUATION BOARD (MS0760-XXXP. MS0761-XXXP)DESCRIPTIONThe PCA4360 evaluation board is used as an evaluationboard for MELPS 760 4-bit single-chip computers.When used in the external ROM mode, this board consists·of the evaluation chip (M50760-000P) and the programEPROM (M5L2716K) possessing equivalent functions to themasked ROM M50760-XXXP and M50761-XXXP. When creatingthe mask for a developed program, this board is suitablefor verification and running tests.FEATURES• Board computer equivalent to M50760-XXXP, M50761-XXXP• Simple program modification using an EPROM• Connection to user's system by means of a cable• Built-in clock gene~torAPPLICATIONSProgram and applications equipment. development forMELPS 760 4-bit Single-chip microcomputersFUNCTIONThe evaluation chip (M50760-000P) outputs the value of theprogram counter, and reads and executes the instructionstored in the appropriate EPROM address.It is possible to have this board emulate the operation of asingle-chip microcomputer.SPECIFICATIONSItemApplicable microcomputerClock frequencyCycle timeI VoltagePower supply ICurrentConnection with usersystemICF 400kHzSpecificationM50760-XXX P, M50761-XXX PICR 200-400kHz10,us5V±5%, single0.5mA typoAccessory cableI Jl For user system connection (20pin)ConnectorsJ ,J2 2-pin angle pin header for power supplyOuter dimensions 100 (L) X 150 (W) X 20 (H) mmCONFIGURATIONAs can be seen in the block diagram, the PCA4360 consistsof the following hardware:(1) Evaluation chip and peripheral circuit. (2) Program EPROM socketThe board and user system can be connected by means ofan accessory cable.-,---------------1BLOCK DIAGRAM10A Do M5L2716K\DATA09 ~ PROGRAM ~ BUS f--o'"STORAGE BUFFEREPROMIAI1IIPOWER ISUPPLYCONNECTORI(J2)~I Vee1 VssCLOCK JGENERATORCIRCUIT IriMINGGENERATOR CIRCUIT -Do-OsFoM50760-OOOpXinCNVss F,-F3SRESET91PORTEMULATIONCIRCUIT3II- IL ______________, _~FOFl-F 3SENSEI INPUTRESETVss~ICONNECTIONFOR TARGETSYSTEMCONNECTION(J 1)a• MITSUBISHI;"ELECTRIC7-23


MITSUBISHI MICROCOMPUTERSPCA8400MELPS 8-48 DEDICATED BOARDDESCRIPTIONThe PCA8400 is a dedicated MELPS 848 board for usewith the PC4000 debugging machine for the 8-bit singlechipmicrocomputers and is used by inserting the board inthe PC4000 cabinet.FEATURES• Connection to user's system by means of a 40-pin 01 Lplug• Control circuits and connectors for the i 8748 writingadaptor (PC41 00)APPLICATIONSThe development of hardware and software for systemsusing the MELPS 8-48 8-bit single-chip microcomputers.CONFIGURATIONAs can be seen in the block diagram, the PCA8400 consistsof the following hardware:(1) Evaluation chip (M5L8039P-6) and peripheral circuitry(2) ROM with the PC4000 monitor program(3) Single-step and breakpoint control circuit(4) Program memory interface circuit(5) Input/output buffer/latch circuitThe PC4000 is connected to this board using a cardedge connector and this board is connected to the usersystem by means of an accessory cable.FUNCTIONThe debugging machine PC4000 operates as a debuggingmachine for the MELPS 8-48 using the contents of themonitor ROM mounted on the ~dedicated board. Theevaluation chip (M5L8039P-6) loaded on the board executesthe program stored in the program memory in thePC4000 debugging machine.The internal status of the evalua~ion chip is read outunder monitor CPU control when single-step operation andbreakpoint operation are halted.An interface and connector to enable connection to theM5L8748S writing adaptor PC4100 has been provided,allowing programs to be written and read from thei8748.BLOCK DIAGRAMPORT DIRECTION ~--~--~ PORT DSWITCHING CIRCUITCOMPARISONADDRESSADDRESS LATCH8IE---------,~-~ PORT PlSINGLE-STEP'--------t--:.... CONTROL CIRCUITCLOCKGENERATOR4PORT SWITCHINGCIRCUITJPORT P2IADDRESSINSTRUCTIONDATA~IPC4000MONITOR ROMM5L2732KX 26 JM5L8155P..ITO PC4100M5L8748SWRITER- -i 8748 INTERFACE PORT---7-24 .•.. MITSUBISHI..... ELECTRIC


MITSUBISHI MICROCOMPUTERSPCA8400.MELPS 8-48 DEDICATED BOARDSPECIFICATIONSItemApplicablemicrocomputersM5L8048-XXXPM5L8049-XXXPM5M8050H-XXXPM5M8050L-XXXPSpecificationClock l Packagefrequency I VariablerangeApplicable debuggingmachinePower supply6.144MHz1-6.144MHz (By changing the oscillator crystal)PC4000 (connected by a card edge connector)Supplied from the PC4000 when inserted into thedebugging machineConnection to user'ssystemDebugging functions(contents df monitorEPROM)OtherBy an accessory cableProgram execution from any address and halt•• Data writing to EPROM and reading• Confirmation and change of the contents of programRAMSerial data transfer to an external device•the evaluation chip•Confirmation and modification of the RAM data in(M5L8039P-6) and the contents of the following.registers and flags:• Program counterAccumulator• PSWBy connecting the PC4100, read and write operationsto the i8748 can be performed.II• MITSUBISHI"ELECTRIC .7-25


MITSUBISHI MICROCOMPUTERSPCA8403MELPS 8·48 EV ALUTION BOARDDESCRIPTIONThe PCA8403 evaluation board is used as an evaluationboard for MELPS 8-48 B-bit microc()mputers.This board consists basically of the external ROM chip(M5L8039P·ll) and EPROM (M5L2732K), possessingequivalent functions to the masked ROM M5L8048-XXXPand M5L8049-XXXP. When creating the mask for adeveloped program, this board is suitable for programverification- and running tests.FEATURES• Board computer equivalent to the M5L8048-XXXP,M5L8049-XXXP.• Simple program modification using an EPROM• Connection to user's system socket by means of a 40-pinDIL plug• Built-in clock generator• Speed up of a CPU using the M5L2764K.CONFIGURATIONAs can be seen in the block diagram, the PCA8403 consistsof the following hardware:(1). Evaluation chip and peripheral circuitry(2) Program EPROM socket(3) EPROM power supply circuitThe board and user system can be connected by meansof an acce.ssory cable.SPECIFICATIONSTypeItem8-bit parallel processorSpecificationCPU M5 L8039 P-" (equivalent to Intel 8039)Cycle timeMemoryClock supplied by user system (maximum 11 MHz)Program memory: 4K bytes (M5L2732K)Data memory: 128 bytes (built-in M5L8039P-11)APPLICATIONSProgram and applications equipment development forMELPS 8-48 8-bit single-chip microcomputers.FUNCTIONThe evaluation chip (M5L8039P-11) outputs the value ofthe program counter and reads in instructions fromERROM and executes them.The board is equivalent in operation to a single-chipmicrocomputer.BLOCK DIAGRAMM5L8039P-ll1.·0InterruptsPower supplyConnector usedOuter dimensions8-bit parallel port x3Test pin ,,2INT pin5V ±5%, 600mA (max)40-pin DI L accessary plag50 (L) x 170 (W) x 35 (H) mmI+5V- EAPSEN2CLOCK Xl, X2 DBP1~I 4 PORT 2P2 UPPER ORDER 4 BITSUPPERORDER BITSTEST PIN T 1TEST PIN TOI8P1ALETo PORT 2UPPERORDER BITSTlPO WR~~1IOEADDRESSIN ADDRESS~LATCHROM DATA-r--'"t14DATA BUSPORTr--INPUTBUFFER-lIIALE1-1P2 LOWER ORDER 4 BITSPORT 2IINPUT BUFFER~T2 OUTP:T LATCHRD WRDATA BUSPORTOUTPUT r-LATCH~ DBIII7-26 • MITSUBISHI.... ELECTRIC


APPENDICES


MITSUBISHI MICROCOMPUTERSMELPS 760 MASK ROMORDERING METHODMASK ROM ORDERING METHODMitsubishi Electric corp. receives via EPROMs the data forwriting programs in the mask ROMs of single-chip 4-bitmicrocomputer.When placing an order, submit three sets of one or morethan one EPROMs in which the data for one pattern arewritten together with the prescribed confirmation document(s).It use of different media is intended, make a request accordingly.EPROM SPECIFICATIONS1. M5L2716K, M5L2732K, Intel's 2716 or 2732 may be used,but M5L2716K and M5L2732K are regarded as standard.2. The data and address of EPROM are processed by regardingthe content of "H" as "1".3. Write in the EPROMs to be submitted the kind of orderto be placed as well as the distinction as to addressassignment (the address to be aSSigned is given in theconfirmation documents).4. If a discrepancy (discrepancies) between the EPROMssubmitted is found, a notice to that effect will be given.5. Everything written from the start address of an EPROMonward is treated as data.MASK ROM PROCESSING. SYSTEMPrograms for automatic design of mask ROMs have beenprepared and the followings are generated automatically:1. Drawing data for mask ROM generation.2. Proof lists for checking errors in making mask ROMs.3. Test pograms for large-scale tester.A CAD system for this shown in the figure below.ITEMS TO CONFIRM FOR ORDERING1. Confirmation document for masking···················1 copy2. Data for ROMs .. ····························· 3 sets in EPROMsMELPS 760 MASK ROM DEVELOPMENT CAD SYSTEMFROM CUSTOMERMITSUBISHI ELECTRIC6, C7 7vvVWWliVVIILARGETESTER• WATERTEST• FINALTEST.-------1. QA TEST• MITSUBISHI.... ELECTRIC8-3


MITSUBISHI MICROCOMPUTERSMELPs 760 MASK ROMORDERING METHODMELPS760 MASK-PROGRAMMABLE ROM CONFIRMATION MATERIALSINGLE-CHIP 4-BIT MICROCOMPUTERS M50760-XXXSPMITSUBISHI ELECTRICCustomerCompany nameCompany addressTelPreparedSignatureCompany contactIDateApprovedThe single-chip microcomputer type number to order andthe type of EPROMs to be supplied should be specified bychecking V in the boxes. Three sets of EPROMs should besupplied.EPROM type number 02716 02732Address of EPROM OA (00016 - 3FF16) OA (00016 - 3FF16)Note 1: The high-level data of both data outputs and address inputs of the supplied EPROM will be programmed as '1', andlow-level as '0'.2 : Cleary indicate the type number of EPROMs and address designation letter symbols A and B on the suppliedEPROMs.3 : The data of the addresses in parentheses on the EPROM are programmed onto the ROM.4 : The data from each PROM in the set is compared and if 2 of the 3 are equal, the equal value will be programmedinto the ROM. When the 3 values are different programming is halted and the customer is notified of the error. Theerror report will show the address and data.CUSTOMER'S IDENTIFICATION MARKIf you require a special identification mark, please specify in the following format.Mitsubishi IC type numberNote 5 : A mark field should start with the box at the extreme right.6 : The identification mard should be no more than 12 characters consisting of alphanumericcharacters (except J.I. and 0) or dashes.COMMENTS8-4•. MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSMELPS 740 MASK ROMORDERING METHODMASK ROM ORDERING METHODMitsubishi Electric corp. receives via EPROMs the data forwriting programs in the mask ROMs of single-chip 8-bitmicrocomputer.When placing an order, submit three sets of one or morethan one EPROMs in which the data for one pattern arewritten together with the prescribed confirmation document(s).It use of different media is intended, make a request accordingly.EPROM SPECIFICATIONS1. M5L2716K, M5L2732K, Intel's 2716 or 2732 may be used,but M5L2716K and M5L2732K are regarded as standard.2. The data and address of EPROM are processed by regardingthe content of "H" as "1".3. Write in the EPROMs to be submitted the kind of orderto be placed as well as the distinction as to addressassignment (the address to be assigned is given in theconfirmation documents).4. If a discrepancy (discrepancies) between the EPROMssubmitted is found, a notice to that effect will be given.5. Everything written from the start address of an EPROMonward is treated as data.MASK ROM PROCESSING SYSTEMPrograms for automatic design of mask ROMs have beenprepared and the followings are generated automatically:1. Drawing data for mask ROM generation.2. Proof lists for checking errors in making mask ROMs.3. Test pograms for large-scale tester.A CAD system for this shown in the figure below.ITEMS TO CONFIRM FOR ORDERING1. Confirmation document for masking···················1 copy2. Data for ROMs···· ........................... 3 sets in EPROMsMASK OPTIONSAs for option, make entries in the confirmation documentsby referring to the data book.ROMs are made in accordance with the EPROMs and confirmationdocument submitted, then the EPROMs will be returnedbut the documents will not be returned.MELPS 740 MASK ROM DEVELOPMENT CAD SYSTEMFROM CUSTOMERMITSUBISHI ELECTRICII•• WATERTEST• FINALTESTtE-----...... QA-TEST• MITSUBISHI..... ELECTRIC8-5


MITSUBISHI MICROCOMPUTERSMELPS 740 MASK ROMORDERING METHOD'MELPS740 MASK-PROGRAMMABLE I ROM CONFIRMATION ,MATERIALSINGLE-CHIP 8-BIT MICROCOMPUTERS M50740-XXXSPMITSUBISt:ll ELECTRICCustomerCompany nameCompany addressCompany contactTelDatePreparedApprovedSignatureThe single-chip microcomputer type number to order andthe type of EPROMs to be supplied should be specified bychecking .,; in the boxes. Three sets of EPROMs should besupplied.EPROM type number 02716 02732Address of EPROM OA (00016 - 3FF16) OA (00016 - 3FF16)Notel: The high-level data of both data outputs and address inputs of the supplied EPROM will be programmed as '1', andlow-level as '0'.2 : Cleary indicate the type number of EPROMs and address designation letter symbols A and B on the suppliedEPROMs.3 : The data of the addresses in parentheses on the EPROM are programmed onto the ROM.4 : The data from each PROM in the set is compared and if 2 of the 3 are equal, the equal value will be programmedinto the ROM. When the 3 values are different programming is halted and the customer is notified of the error. Theerror report will show the address and data.CUSTOMER'S IDENTIFICATION MARKIf you require a special identification mark, please specify in the following format.Mitsubishi IC type numberNote 5 : A mark field should start with the box at the extreme right.6 : The identification mard should be no more than 12 characters conSisting of' alphanumericcharacters (except J.I. and 0) or dashes.COMMENTS8-6'. MITSUBISHI"ELECTRIC


MITSUBISHI MICROCOMPUTERSMELPS 8-48 MASK ROMORDERING METHODMASK ROM ORDERING METHODDescribed below is the ordering method applicable whenprograms submitted by the customer are written into themask ROMs.An automatic mask ROM design program is preparedfor writing programs into mask ROMs, and (1) the draftingdata for mask ROM generation, (2) the reference list formask ROM preparation error checks and (3) an automatictest protram for the large-scale tester designed to test themask ROMs are all automatically generated.When the object program is stored in the MELPS8-48single-chip microcomputer mask ROM, the order for theobject program medium is received as an EPROM form.Consequently, the EPROM or EPROMs which have storedthe object program equivalent to one single-chip microcomputerchip should be submitted accompanied by theprescribed confirmation sheets for 3 sets of EPROMs respectively.EPROM SPECIRICATIONS1. Usable EPROMs include Mitsubishi's M5L2716K,M5L2732K or Intel's 2716, 2732, 8748, 8749 or theirequivalent. The M5L2716K, M5L2732 and Intel's 8748,8749 are the standard EPROMs.2. "High" is treated as 1 for the EPROM data andaddress.3. <strong>Al</strong>l the data from the head address to the final addressare treated as the EPROM's effective data.CHECKPOINTS1'. Cleary indicate the type number of EPROM.MELPS 8-48 MASK ROM DEVELOPMENT CAD SYSTEMFROM CUSTOMERMITSUBISHI ELECTRIC60, CJ Iv'l'VWIIYVVVIILARGETESTER- WATERTEST- FINALTEST1------;- QA TEST• MITSUBISHI.... ELECTRIC8-7


MITSUBISHI MICROCOMPUTERSMELPS 8-48 MASK ROMORDERING METHODMELPS8-48 MASK-PROGRAMMABLE ROM CONFIRMATION MATERIALSINGLE-CHIP 8-BIT MICROCOMPUTERS M5L8048-XXXP, M5L8049-XXXP, P-8, P-6, M5L8049H-XXXP, M5M8050H-XXXP,M5M8050L-XXXP, M5M80C49-XXXPMITSUBISHI ELECTRICSignatureCustomerCompany namePreparedCompany addressTelCompany contactDateApprovedThe single-chip microcomputer type number to order andthe type of EPROMs to be supplied should be specified bychecking \lin the boxes. Three sets of EPROMs should besupplied.~ermicrocomputer type number02716 02732OM5L8048-XXXP OA (00016 - 3FF16) OA (00016 - 3FF16) 08748OM5L8049-XXXPOM5L8049-XXXP-8 OA (00016 - 7FF16) OA (00016 - 7FF16) 08749OM5L8049-XXXP-6OM5L8049H-XXXP OA (00016 - 7FF16) OA (00016 - 7FF16) 08749OM5M8050H-XXXP OA (00016 - 7FF16)OM5M8050L-XXXP DB (80016 - FFF16)OA (00016 -FFF16)-Notel: The high-level data of both data outputs and address inputs of the supplied EPROM will be programmed as '1', andlOW-level as '0'.2 : Cleary indicate the type number of EPROMs and address designation letter symbols A and B on the suppliedEPROMs.3 : The data of the addresses in parentheses on the EPROM are programmed onto the ROM.4 : The data from each PROM in the set is compared and if 2 of the 3 are equal, the equal value will be programmedinto the·ROM. When the 3 values are different programming is halted and the customer is notified of the error. Theerror report will show the address and data.CUSTOMER'S IDENTIFICATION MARKIf you require a special identification mark, please specify in the following format.Mitsubishi IC type numberNote 5 : A mark field should start with the box at the extreme right.6 : The identification mard should be no more than 12 characters consisting of alphanumericcharacters (except J.1. and 0) or dashes.COMMENTS8-8.• MITSUBISHI..... ELECTRIC


MITSUBISHI MICROCOMPUTERSMELPS 8-48 MASK ROMORDERING METHODMELPS8-48 MASK-PROGRAMMABLE ROM CONFIRMATION MATERIALSINGLE-CHIP 8-BIT MICROCOMPUTERS M5M80C49-XXXPMITSUBISHI ELECTRICCustomerCompany nameCompany addressCompany contactTelDatePreparedApprovedSignatureThe single-chip microcomputer type number to order andthe type of EPROMs to be supplied should be specified bychecking V in the boxes, Three sets of EPROMs should besupplied,~ermicrocomputer type number02716 02732OM5M80C49P-XXXP OA (000 16 - 7FF 16) OA (000 16 - FFF 16) 08749NoteThe high-level data of both data outputs and address inputs of the supplied EPROM will be programmed as '1', andlow-level as '0',Cleary indicate the type number of EPROMs and address designation letter symbols A and B on the suppliedEPROMs,The data of the addresses in parentheses on the EPROM are programmed onto the ROM.The data from each PROM in the set is compared and if 2 of the 3 are equal, the equal value will be programmedinto the ROM. When the 3 values are different programming is halted and the customer is notified of the error. Theerror report will show the address and data.CUSTOMER'S IDENTIFICATION MARKIf you require a special identification mark, please specify in the following format.COMMENTSMitsubishi IC type numberNote 5 : A mark field should start with the box at the extreme right.6 : The identification mard should be no more than 12 characters consisting of alphanumericcharacters (except J.I. and 0) or dashes.II• MITSUBISHI.... ELECTRIC8-9


MITSUBISHI MICROCOMPUTERSMELPS 8-41 MASK ROMORDERING METHODMASK ROM ORDERING METHODDescribed below is the ordering method applicable whenprograms submitted by the cL!stomer are written into themask ROMs.An automatic mask ROM design program is preparedfor writing programs into mask ROMs, and (1) the draftingdata for mask ROM generation, (2) the reference list formask ROM preparation error checks and (3) an automatictest protram for the large-scale tester designed to test themask ROMs are all automatically generated.When the object program is stored in the MELPS8-48single-chip microcomputer mask ROM, the order for theobject program medium is received as an EPROM form.Consequently, the EPROM or EPROMs which have storedthe object program equivalent to one single-chip microcomputerchip should be submitted accompanied by theprescribed confirmation sheets for 3 sets of EPROMs respectively.EPROM SPECIRICATIONS1. Usable EPROMs include Mitsubishi's M5L2716K,M5L2732K, or Intel's 2716,2732,8741,8741 A, 8742 or theirequivalent. The M5L2716K and M5L2732K are the'standardEPROMs.2. '/High" is tr.eated as 1 for the EPROM data andaddress.3. <strong>Al</strong>l the data from the head address to the final addressare treated as the EPROM's effective data.CHECKPOINTS1. Cleary indicate the type number of EPROM.MELPS 8-41 MASK ROM DEVELOPMENT CAD SYSTEMFROM CUSTOMERMITSUBISHI ELECTRICLARGETESTER• WATER,TEST• FINALTEST.--------1. QA TEST8-10• MITSUBISHI"ELECTRIC


MITSUBISHI MICROCOMPUTERSMELPS 8-41 MASK ROMORDERING METHODMELPS8-41 MASK-PROGRAMMABLE ROM CONFIRMATION MATERIALSLAVE COMPUTERS M5L8041A-XXXP, M5L8042-XXXPMITSUBISHI ELECTRICCustomerCompany nameCompany addressCompany contactTelDatePreparedApprovedSignatureThe Slave computer type number to order and the type ofEPROMs to be supplied should be specified by checkingV in the boxes. Three sets of EPROMs should be supplied.~bermicrocomputer type number02716 02732OM5L8041 A-XXXP OA (00016 - 3FF16) OA (00016 - 3FF16)0874108741AOM5L8042-XXXP OA (00016 - 7FF16) OA (00016 - 7FF16) 08742NoteThe high-level data of both data outputs and address inputs of the' supplied EPROM will be programmed as '1', andlOW-level as '0'.2 Cleary indicate the type number of EPROMs and address designation letter symbols A and B on the suppliedEPROMs.3 The data of the addresses in parentheses on the EPROM are programmed onto the ROM.4 The data from each PROM in the set is compared and if 2 of the 3 are equal, the equal value will be programmedinto the ROM. When the 3 values are different programming is halted and the customer is notified of the error. Theerror report will show the address and data.CUSTOMER'S IDENTIFICATION MARKIf you require a special identification mark, please specify in the following format.NoteMitsubishi IC type numberA mark field should start with the box at the extreme right.The identification mard should' be no more than 12 characters consisting of alphanumericcharacters (except J.I. and 0) or dashes.IICOMMENTS• MITSUBISHI.... ELECTRIC8-11


CONTACT ADDRESSES FOR FURTHER INFORMATIONJAPANElectronics Marketing DivisionMitsubishi Electric Corporation2-3, Marunouchi 2-chomeChiyoda-ku, Tokyo 100, JapanTelex: 24532 MELCO JTelephone: (03) 218-3473(03) 218-3499Facsimile: (03) 214-5570HONG KONGRyoden Electric Engineering Co., Ltd.22nd fl., Leighton Centre77, Leighton RoadCauseway Bay, Hong KongTelex: 73411 RYODEN HXTelephone: (5) 795-2427Facsimile: (852) 123-4344TAIWANMELCO Taiwan Co., Ltd.Room 1303, 13th fl., Huel Fong Bldg.27, Sec. 3, Chung Shan N. RoadTaipei, R.O.C.Telex: 11211 MITSUBISHITelephone: (597) 3111U.S.A.Mitsubishi Electronics America, Inc777 North Pastoria AvenueSunnyvale CA 94086, U.S.A.Telex: 172296 MELA SUVLTelephone: (408) 730-5900Facsimile: (408) 730-4972Mitsubishi Electronics America, Inc200 Unicorn Park DriveWoburn, MA 01801, U.S.A.Telex: 951796 MELASB WOBNTelephone: (617) 938-1220Facsimile: (617) 938-1075Mitsubishi Electronics America, Inc.3247 West Story Road,Los Colinas Business ParkIrving, TX 75062, U.S.A.Telephone: (214) 258-1266Facsimile: (214) 659-9313Mitsubishi Electronics America, Inc.799 North Bierman Circle,Mt. Prospect, ILL 60056, U.S.A.Telex: 270636 MESA CHI·MPCTTelephone: (312) 298-9223-8Facsimile: (312) 298-9223-8WEST GERMANYMitsubishi Electric Europe GmbHBrandenburger Str. 404030 Ratingen, West GermanyTelex: 8585070 MED DTelephone: (02102) 4860Facsimile: (02102) 486-115U.K.Mitsubishi Electric (UK) Ltd.18th Floor, Centre Point,103 New Oxford st.,London WC1A1 EB, U.K.Telex: 296195 MELCO GTelephone: (379) 7160Facsimile: (836) 0699AUSTRALIAMitsubishi Electric Australia Pty. Ltd.73-75, Epping Road, North Ride,N.S.w. 2113 AustraliaP.O. BQX 1567 Macquarie CentreTelex: . MESYO AA 26614Telephone: (888) 5777Facsimile: (887) 3635• MITSUBISHI.... ELECTRIC


MITSUBISHI DATA BOOKSINGLE-CHIP MICROCOMPUTERSMarch, First Edition 1984Editioned byCommittee of editing of Mitsubishi Semiconductor Data BookPublished oyMitsubishi Electric Corp., Semiconductor DivisionThis book, or parts thereof, may not be reproduced in any form without permission ofMitsubishi Electric Corporation.:~['


1984 MITSUBISHI DATA BOOKSINGLE-CHIP MICROCOMPlTTERSJ..MITSUBISHI ELECTRIC CORPORATIONHEAD OFFICE: MITSUBISHI DENKI BLDG., MARUNOUCHI, TOKYO 100. TELEX: J24532 CABLE: MELCO TOKYOH-C5229-A Ki-8403 Printed in Japan (ROD)New publication. effective Mar, 1984Specifications subject to change without notice.


This book contains the typical characteristics ofMITSUBISBI MICROCOMPUTER .8-48 series,which are omitted from the data book.MITSUBISHI ·ELECTRIC


MITSUBISHI MICROCOMPUT~K:'MSL8048-XXXP IMSL803SLPSINGLE-CHIP 8-BIT MICROCOMPUTERTYPICAL CHARACTERISTICS~ 3.8o>w 3.6C)«~~ 3.4I­::l0..~ 3.2o...JW~ 3.0iC)i:DATA BUS HIGH-LEVELOUTPUT VOLTAGE VS. HIGH-LEVELOUTPUT CURRENTVee = 5VTa = 25"C"~..........'-......~----0.2 -0.4 -0.6 -0.8 -1.0~0>WC)«I- ...J0>I- ::l0..I-::l0...JW>W...J;;0...JDATA BUS LOW-LEVELOUTPUT VOLTAGE VS. LOW-LEVELOUTPUT CURRENT0.5Vee = 5VTa = 25"C0.40.30.20.1V/~///10HIGH"LEVEL OUTPUT CURRENTIOH(mA)LOW-LEVEL OUTPUT CURRENTIOL(mA)~">wC)«I- ...J0>I-::l0..~...JW>W...J;;0...J5P 1 • P 2 LOW-LEVEL INPUTVOLTAGE VS. LOW-LEVELINPUT CURRENTVee = 5V""-""Ta = 25"C'\ r\\\\~">wC)«~0>I-::l0..~...JW~...J;;0...J5RESET LOW-LEVEL INPUTVOLTAGE VS. LOW-LEVELINPUT CURRENT"Vee = 5VTa=25"C\ ,~\\-0.05 -0.1 -0.15 -0.2 -0.25-0. 02 -0. 04 -0. 06 -0. 08 -0. 1LOW-LEVEL INPUT CURRENT II(mA)LOW-LEVEL INPUT CURRENTII(mA)NORMARIZED SUPPLY CURRENT (ledVS. AMBIENT TEMPERATUREU 1.6.2~ 1.4wa:a:::l() 1. 2~0..0..::len 1. 0oWNa:« 0.8::Ea:ozVee = 5VVee = 5V"" '-.... ['.....,,~0.6-25 25 50 75100.E"I-zwa:a:::l()~0..0..::len0WNa:«:Ea:0zNORMARIZED SUPPLY CURRENT (100)1.61.4VS. AMBIENT TEMPERATUREVee = 5VVee = 5V1.2'" ~1.00.80.6-25~ ~ ~25 50 75100AMBIENT TEMPERATURE Ta("C)AMBIENT TEMPERATURE Ta("C)• MITSUBISHI"ELECTRIC


MITSUBISHI MICROCOMPUTERSMSLS049·XXXP,P·S,P·6MSLS039P.ll,P·S,P·6SINGLE-CHIP a-BIT MICROCOMPUTERTYPICAL CHARACTERISTICS:;r o>w(!)~..Jo>....:::lQ.....:::lo..JW>W..J±(!)J:DATA BUS HIGH-LEVELOUTPUT VOLTAGE VS. HIGH-LEVELOUTPUT CURRENT3. 83.63.43.23.0Vee = 5VTa = 25°e"~ ..........~i""--. ""'--0.2 -0.4 -0.6 -0.8 -1.0DATA BUS LOW-LEVELOUTPUT VOLTAGE VS. LOW-LEVELOUTPUT CURRENT~ 0.5Vee = 5V~ Ta = 25°e~/0.4w(!)~o 0.3>....:::lQ.~ 0.2o..JWiij 0.1..J~VVVg 0o 10/HIGH-LEVEL OUTPUT CURRENT IOH(mA)Ph P 2 LOW-LEVEL INPUTVOLTAGE VS. LOW-LEVELINPUT CURRENTVee = 5VTa = 25°eLOW-LEVEL OUTPUT CURRENT IOL(mA)RESET LOW-LEVEL INPUTVOLTAGE VS. LOW-LEVEL5~ __ ~I~N~P~U~T~C~U~R~RrE~N~T ____ ~Vee = 5VTa = 25°ew(!)~..Jo>....:::lQ.~..JW>W..J~o..Jo~~~~~~ __ ~ ___ ~ ___ ~-0.05 -0.1 -0.15 -0.2 -0.25 -0.3w(!)~g....:::lQ.~..JWiij..J~o..J0~0----~0~.2~--~0.-4----~0.~6---~0.~8---~1.0LOW-LEVEL INPUT CURRENT II(mA)LOW-LEVEL INPUT CURRENTII(mA)NORMARIZED SUPPLY CURRENT {IcC>VS. AMBIENT TEMPERATURE1.6~ 1.4wa:a:B 1.2>­..JQ.'"Q. :::l CJ)oWNit:«:Ea:oz1.0Vee = 5VVoo = 5V~~0.8"'~0.6 25 o 25 50 75100NORMARIZED SUPPLY CURRENT {loo)VS. AMBIENT TEMPERATURE1.6.... 1. 4zwa:a:B 1.2>­..JVee = 5VVoo = 5V~'"Q.1.0Q.:::lCJ)oWN~ 0.8:Ea:oz 0.6-25~ ~ I-....25 50 75100AMBIENT TEMPERATURETace)AMBIENT TEMPERATURET ace)• MITSUBISHII.. ELECTRIC


MITSUBISHI MICROCOMPUTERSMSL8049H-XXXP/MSL8039HLPSINGLE-CHIP 8-BIT MICROCOMPUTERTYPICAL CHARACTERISTICS"> 3.8l:o>3.6wC)~o 3.4>~::>c..~ 3.2o...JWGj 3.0...J±C)DATA BUS HIGH-LEVELOUTPUT VOLTAGE VS. HIGH-LEVELOUTPUT CURRENTVee = 5VTa = 25"C..........I'..........~--- :--~ 2.8o -0. 2 -0. 4 -0. 6 -0. 8 -1. 0~ 0.5So>w 0.4C)c..~ 0.2o...JW~ 0.1~o...JDATA BUS LOW-LEVELOUTPUT VOLTAGE VS. LOW-LEVELOUTPUT CURRENTVee = 5VTa = 25'CV/ /V~/V2 6 8 10HIGH-LEVEL OUTPUT CURRENTIOH(mA)LOW-LEVEL OUTPUT CURRENTIOL(mA)~;>wC)~::>c..~...JW>W...J~0...J5oPl. P 2 LOW-LEVEL INPUTVOLTAGE VS. LOW-LEVELINPUT CURRENTVee = 5V..............~Ta = 25'C~'"~\\-0. 1 -0. 15 -0. 2 -0. 25 -0. 3 -0. 35~;>wC)~::>c..~...JW>W...J~0...J5oRESET LOW-LEVEL INPUTVOLTAGE VS. LOW-LEVELINPUT CURRENTVee =5V"Ta = 25"C'\ ,1\\\o -0. 02 -0. 04 -0. 06 -0. 08 -0. 1LOW-LEVEL INPUT CURRENTII(mA)LOW-LEVEL INPUT CURRENTII(mA)U 1.6.2~Z 1.4wa:a:::>(,) 1.2~c..c..en ""'" ::> 1.0owN0:0.80.6-25VS. AMBIENT TEMPERATUREVee = 5VVee = 5V~-........... ~ ""'"-o 25 50 75AMBIENT TEMPERATURE Ta('C)100'0 1.6~~Zwa:a:::>(,)NORMARIZED SUPPLY CURRENT (loo)1.41.2VS. AMBIENT TEMPERATUREVee = 5VVee = 5V" ~ ~~~~c..c..::>enowN0:


MITSUBISHI MICROCOMPUTERSMSM80S0H-XXXP/MSM8040HPSINGLE·CHIP a·BIT MICROCOMPUTERTYPICAL CHARACTERISTICS>" 3.8X~wc.!l«~DATA BUS HIGH-lEVELbUTPUT VOLTAGE VS. HIGH-lEVELOUTPUT CURRENT3.6o 3.4>t-:::>Q.5 3.2o.oJWGj 3.0.oJr.c.!l~Vee = 5VTa = 25'C"- ~~---U.2 -0.4 -0.6 -0.8 -1.0~o> 0.4wc.!l«~o 0.3>t- :::>~ 0.2:::>o.oJWGj 0.1.oJ::o.oJDATA BUS lOW-lEVELOUTPUT VOLTAGE VS. lOW-lEVELOUTPUT CURRENT0.5Vee = 5VTa = 25'C7/// ,// V/10HIGH-LEVEL OUTPUT CURRENTIOH(mA)LOW-LEVEL OUTPUT CURRENTIOL(mA)oPh P 2 lOW-lEVEL INPUTVOLTAGE VS. lOW-lEVELINPUT CURRENTVee = 5VTa = 25'C~~'"'"i\.."'~ "-0.05 -0.1 -0.15 -0.2 -0.25 -0.3RESET lOW-lEVEL INPUTVOLTAGE VS. lOW-lEVELINPUT CURRENT5\\o o~\\~Vee = 5VTa = 25'C-0. 02 -0. 04 -0. 06 -0; 08 -0. 1LOW-LEVEL INPUT CURRENT1,(mA)LOW-LEVEL INPUT CURRENT1,(mA)NORMARIZED SUPPLY CURRENT (ledVS. AMBIENT TEMPERATURE1.6Vee = 5VVee = 5V~ 1.4wa:a:8 1.2~Q.Q.~ 1.0oWN~ 0.8~a:oZ 0.6-25 o 25 50 75" ~ .............. ..............~100NORMARIZED SUPPLY CURRENT (\DD)1.6t- 1. 4zwa:a:8 1.2~Q.Q.~ 1.0oWN~ 0.8~a:~ 0.6-25VS. AMBIENT TEMPERATUREVee = 5VVee = 5V~"-~~----25 50 75100AMBIENT TEMPERATURE Ta('C)AMBIENT TEMPERATURETa('C)• MITSUBISHI"ELECTRIC


MITSUBISHI MICROCOMPUTERSMSM80S0L-XXXP/MSM8040LPSINGLE·CHIP a·BIT MICROCOMPUTERTYPICAL CHARACTERISTICS'> 3.8~~w 3.6(!)~~ 3.4I­:;)a.~ 3.2ow-'>~ 3.0±(!)J:DATA BUS HIGH-LEVELOUTPUT VOLTAGE VS. HIGH-LEVELOUTPUT CURRENTVee =5VTa = 25"C.........,..............--------0. 2 -0. 4 -0. 6 -0. 8 -1. 0~o>w(!)DATA BUS LOW-LEVELOUTPUT VOLTAGE VS. LOW-LEVELOUTPUT CURRENT0.5Vee = 5VTa = 25"C0.4«~o 0.3>I­::>a.~ 0.2o-'wGj 0.1-'~o-' 07/'V//Vo 10~HIGH-LEVEL OUTPUT CURRENTIOH(mA)LOW-LEVEL OUTPUT CURRENTIOL(mA)~;>w(!)«~0>I-:;)a.~w-'w>-'~0-'5Pl. P 2 LOW-LEVEL INPUTVOLTAGE VS. LOW-LEVELINPUT CURRENTVee = 5VTa = 25"C~\1\\~00 -0.05 -0.1 -0.15 -0.2 -0.255w(!)«~o>I­:;)a. 2~-' wGj-'~oRESET LOW-LEVEL INPUTVOLTAGE VS. LOW-LEVELINPUT CURRENTVee = 5VTa = 25·e\\~\\-' o o~-0. 01 -0. 02 -0. 03 -0. 04 -0. 05LOW-LEVEL INPUT CURRENTII(mA)LOW-LEVEL INPUT CURRENTII(mA)NORMARIZED SUPPLY CURRENT (IcdVS. AMBIENT TEMPERATURE1.6Vee = 5VVee = 5VI- 1. 4zwa:a:~ 1.2>­a. -'a."'-~ 1.0 ..............................~"""'-oWN~ 0.8~a:oZ 0.6-25o 25 50 75AMBIENT TEMPERATURE T ace)100NORMARIZED SUPPLY CURRENT (100)VS. AMBIENT TEMPERATURE1.6I- 1.4Zwa:a:~ 1.2~a.a.:;) 1. 0enowN~ 0.8~Vee = 5VVee = 5V,"--a:oz 0.6-25 o 25...............------50 75AMBIENT TEMPERATURE T a( ·e)100• MITSUBISHI.... ELECTRIC


MITSUBISHI MICROCOMPUTERSMSM80C49-XXXP/MSM80C39P-6SINGLE-CHIP a-BIT CMOS MICROCOMPUTERTYPICAL CHARACTERISTICS~o>~ 4.8«~o>~ 4.6c..I­ ::>o..J ~~ 4.4w..J±(!)IDATA BUS HIGH-LEVELOUTPUT VOLTAGE VS. HIGH-LEVELOUTPUT CURRENT~~~" "'Vee = SVTa = 2S'C4.2o -1 -2 -3 -4DATA BUS LOW-LEVELOUTPUT VOLTAGE VS. LOW-LEVELOUTPUT CURRENTo. 4~---,--~--~--..,~ Vee=SV~ Ta= 25°C~ O. 3J-----I----+---+~--f~o>~ O. 2 t-----t----t~-_+---ic..I­ ::>oirl~..J::o..Jo. 1 t-----t~---+--_+---io~-~--~----~---~o 6HIGH-LEVEL OUTPUT CURRENTIOH(mA)LOW-LEVEL OUTPUT CURRENTIOL(mA)w(!)«~o>I­ ::>c..~..JW~..J::9P 1• P2 LOW-LEVEL INPUTVOLTAGE VS. LOW-LEVELS~ __ -TI~N~P=U~T~C~U~R~R~E~NTT ____ ~Vee = SVTa = 25°C1~--~----~----~--~~o -0. 02 -0. 04 -0. P6 -0. 08~:>w(!)«I-..J0>I-::>c..~..JW~..J::0..J8RESET LOW-LEVEL INPUTVOLTAGE VS. LOW-LEVELINPUT CURRENT'" ~\Vee = SVTa = 25°Co o -20\-40 -60 -80LOW-LEVEL INPUT CURRENT 1,(mA)LOW-LEVEL INPUT CURRENTII(mA)'0~I-ZwII:II:::>u>-..Jc..c..::>C/l0WNa:«:EII:0ZNORMARIZED SUPPLY CURRENT {ledVS. AMBIENT TEMPERATURE1.4 Ta = 25°Cf = 6MHz1.21.00.80.64 4.5/1/5.5AMBIENT TEMPERATURE T aCC)NORMARIZED SUPPLY CURRENT (100)VS. AMBIENT TEMPERATURE1.0 Vee = SV/Ta = 25°CI-ffi 0.75/II:II:::>u~c.. 0.5c..::>C/loWN 0.25a:«:EII:oZo o/AMBIENT TEMPERATURE Ta(OC)• MITSUBISHI..... ELECTRIC


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CONTACT ADDRESSES FOR FURTHER INFORMATIONJAPANElectronics Marketing DivisionMitsubishi Electric Corporation.2-3, Marunouchi 2-chomeChiyoda-ku, Tokyo 100, JapanTelex: 24532 MELCO JTelephone: (03) 218-3473(03) 218-3499Facsimile: (03) 214-5570HONG KONGRyoden Electric Engineering Co., Ltd.22nd fl., Leighton Centre77, Leighton RoadCauseway Bay, Hong KongTelex: 73411 RYODEN HXTelephone: (5) 795-2427Facsimile: (852) 123-4344TAIWANMELCO Taiwan Co., Ltd.Room 1303, 13th fl., Huei Fong Bldg.27, Sec. 3, Chung Shan N. RoadTaipei, R.O.C.Telex: 11211 MITSUBISHITelephone: (597) 3111U.S.A.Mitsubishi Electronics America, Inc.777 North Pastoria AvenueSunnyvale CA 94086, U.S.A.Telex: 172296 MELA SUVLTelephone: (408) 730-5900Facsimile: (408) 730-4972Mitsubishi Electronics America, Inc.200 Unicorn Park DriveWoburn, MA 01801, U .SATelex: 951796 MELASB WOBNTelephone: (617) 938-1220Facsimile: (617) 938-1075Mltsubishi Electronics America, Inc.3247 West Story Road,Los Colinas Business ParkIrving, TX 75062, U.SATelephone: (214) 258-1266Facsimile: (214) 659-9313Mitsubishi Electronics America, Inc.799 North Bierman Circle,Mt. Prospect, ILL 60056, U.S.A.Telex: 270636 MESA CHI-MPCTTelephone: (312) 298-9223-8Facsimile: (312) 298-9223-8WEST GERMANYMitsubishi Electric Europe GmbHBrandenburger Str. 404030 Ratingen, West GermanyTelex: 8585070 MED DTelephone: (02102) 4'860Facsimile: (02102) 486-115U.K.Mitsubishi Electric (U.K.) Ltd.18th Floor, Centre Point,103 New Oxford st.,London WC1A1EB, U.K.Telex: 296195 MELCO GTelephone: (379) 7160Facsimile: (836) 0699AUSTRALIAMitsubishi Electric Australia Pty. Ltd.73-75, Epping Road, North Ride,N.S.W. 2113 AustraliaP.O. Box 1567 Macquarie CentreTelex: MESYO AA 26614Telephone: (888) 5777Facsimile: (887) 3635• MITSUBISHI.... ELECTRIC

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