DS2155 T1/E1/J1

More documents

Recommendations

Info

DS215510.2 T1 Transmit TransparencyThe software-signaling insertion-enable registers, SSIE1–SSIE4, can be used to select signaling insertionfrom the transmit-signaling registers, TS1–TS12, on a per-channel basis. Setting a bit in the SSIExregister allows signaling data to be sourced from the signaling registers for that channel.In transparent mode, bit 7 stuffing and/or robbed-bit signaling is prevented from overwriting the data inthe channels. If a DS0 is programmed to be clear, no robbed-bit signaling will be inserted nor will thechannel have bit 7 stuffing performed. However, in the D4 framing mode, bit 2 will be overwritten by azero when a yellow alarm is transmitted. Also, the user has the option to globally override the SSIExregisters from determining which channels are to have bit 7 stuffing performed. If the T1TCR1.3 andT1TCR2.0 bits are set to one, then all 24 T1 channels will have bit 7 stuffing performed on them,regardless of how the SSIEx registers are programmed. In this manner, the SSIEx registers are onlyaffecting channels that are to have robbed-bit signaling inserted into them.10.3 T1 Receive-Side Digital-Milliwatt Code GenerationReceive-side digital-milliwatt code generation involves using the receive digital-milliwatt registers(T1RDMR1/2/3) to determine which of the 24 T1 channels of the T1 line going to the backplane shouldbe overwritten with a digital-milliwatt pattern. The digital-milliwatt code is an 8-byte repeating patternthat represents a 1kHz sine wave (1E/0B/0B/1E/9E/8B/8B/9E). Each bit in the T1RDMRx registersrepresents a particular channel. If a bit is set to a one, then the receive data in that channel will bereplaced with the digital-milliwatt code. If a bit is set to zero, no replacement occurs.46 of 242
DS2155Register Name:T1RDMR1Register Description: T1 Receive Digital Milliwatt Enable Register 1Register Address: 0ChBit # 7 6 5 4 3 2 1 0Name CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1Default 0 0 0 0 0 0 0 0Bits 0 to 7/Receive Digital Milliwatt Enable for Channels 1 to 8 (CH1 to CH8).0 = do not affect the receive data associated with this channel1 = replace the receive data associated with this channel with digital-milliwatt codeRegister Name:T1RDMR2Register Description: T1 Receive Digital Milliwatt Enable Register 2Register Address: 0DhBit # 7 6 5 4 3 2 1 0Name CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9Default 0 0 0 0 0 0 0 0Bits 0 to 7/Receive Digital Milliwatt Enable for Channels 9 to 16 (CH9 to CH16).0 = do not affect the receive data associated with this channel1 = replace the receive data associated with this channel with digital-milliwatt codeRegister Name:T1RDMR3Register Description: T1 Receive Digital Milliwatt Enable Register 3Register Address: 0EhBit # 7 6 5 4 3 2 1 0Name CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17Default 0 0 0 0 0 0 0 0Bits 0 to 7/Receive Digital Milliwatt Enable for Channels 17 to 24 (CH17 to CH24).0 = do not affect the receive data associated with this channel1 = replace the receive data associated with this channel with digital-milliwatt code47 of 242
Page 1 and 2: DS2155T1/E1/J1 Single-Chip Transcei
Page 3 and 4: 3 of 242DS21551.1 FEATURE HIGHLIGHT
Page 5 and 6: 1.1.7 HDLC ControllersTwo independe
Page 7 and 8: 11.3 E1 INFORMATION REGISTERS .....
Page 9 and 10: 34.5 IDENTIFICATION REGISTER ......
Page 11 and 12: Figure 37-11 TRANSMIT SIDE TIMING..
Page 13 and 14: DS21553.1 DOCUMENT REVISION HISTORY
Page 15 and 16: LINE INTERFACE UNIT Figure 4-2DS215
Page 17 and 18: BACKPLANE INTERFACE Figure 4-4DS215
Page 19 and 20: DS2155Signal Name:TSSYNCSignal Desc
Page 22 and 23: DS2155Signal Name:RPOSISignal Descr
Page 24 and 25: 5.6 JTAG Test Access Port PinsDS215
Page 26 and 27: 5.9 L and G Package PinoutThe DS215
Page 28 and 29: 5.10 10mm STBGA PackageDS215510mm S
Page 30 and 31: ADDRESS R/W REGISTER NAMEREGISTERAB
Page 32: ADDRESS R/W REGISTER NAMEREGISTERAB
Page 35: DS2155Register Name:PCDR1Register D
Page 40 and 41: DS21559. CLOCK MAPFigure 9-1 shows
Page 42 and 43: DS2155Register Name:T1RCR2Register
Page 44 and 45: DS2155Register Name:T1TCR2Register
Page 48 and 49: 10.4 T1 Information RegisterDS2155R
Page 50 and 51: DS215511. E1 FRAMER/FORMATTER CONTR
Page 52 and 53: DS2155Register Name:E1TCR1Register
Page 54 and 55: DS215511.2 Automatic Alarm Generati
Page 56 and 57: E1 ALARM CRITERIA Table 11-2DS2155A
Page 59 and 60: DS2155Register Name:IMR2Register De
Page 65 and 66: DS2155Register Name: IOCR2Register
Page 67 and 68: DS2155Bit 3/Local Loopback (LLB). I
Page 69: DS2155Register Name:PCLR3Register D
Page 73 and 74: 15.2 Path Code Violation Count Regi
Page 75 and 76: DS2155Register Name:FOSCR1Register
Page 77 and 78: 16.2 Receive DS0 Monitor RegistersD
Page 79 and 80: DS215517.1.1 Processor-Based Receiv
Page 81 and 82: DS2155Register Name:Register Descri
Page 85 and 86: DS215517.2.1.1 T1 ModeIn T1 ESF fra
Page 91 and 92: DS2155Register Name:SSIE3Register D
Page 93 and 94: DS215517.2.4 Hardware-Based Transmi
Page 95 and 96: 18.1 Idle Code Programming Examples
Page 97 and 98:
DS2155Register Name:TCICE3Register
Page 99 and 100:
DS215519. CHANNEL BLOCKING REGISTER
Page 101 and 102:
DS2155Register Name:TCBR3Register D
Page 103 and 104:
DS2155Register Name:Register Descri
Page 105 and 106:
20.1 Receive SideSee the IOCR1 and
Page 107 and 108:
DS215521. G.706 INTERMEDIATE CRC-4
Page 109 and 110:
Page 111 and 112:
DS2155Register Name:IMR8Register De
Page 113 and 114:
Page 115 and 116:
DS215523.3 Internal Register Scheme
Page 117 and 118:
Page 119 and 120:
Page 121 and 122:
Page 123 and 124:
Page 125 and 126:
Page 127 and 128:
HDLC CONTROLLER REGISTERS Table 24-
Page 129 and 130:
Page 131 and 132:
24.3 HDLC MappingDS215524.3.1 Recei
Page 133 and 134:
24.3.2 TransmitThe HxTCS1-HxTCS4 re
Page 135 and 136:
DS2155Register Name:SR6, SR7Registe
Page 137 and 138:
Page 139 and 140:
24.3.5 HDLC FIFOSDS2155Register Nam
Page 141 and 142:
Page 143 and 144:
DS215525. LINE INTERFACE UNIT (LIU)
Page 145 and 146:
DS215525.2.2 Receive G.703 Section
Page 147 and 148:
DS2155an accuracy of ±32ppm for T1
Page 149 and 150:
E1 ModeDS2155L2 L1 L0 APPLICATION N
Page 151 and 152:
DS2155Register Name:LIC2Register De
Page 153 and 154:
DS2155Register Name:LIC4Register De
Page 155 and 156:
DS2155Register Name:SR1Register Des
Page 157 and 158:
25.8 Recommended CircuitsDS2155BASI
Page 159 and 160:
25.9 Component SpecificationsDS2155
Page 161 and 162:
JITTER TOLERANCE (T1 MODE) Figure 2
Page 163 and 164:
OPTIONAL CRYSTAL CONNECTIONS Figure
Page 165 and 166:
DS2155Register Name:TCD1Register De
Page 167 and 168:
DS2155Register Name:RDNCD1Register
Page 169 and 170:
DS2155Register Name:RSCD1Register D
Page 171 and 172:
27.1 BERT Register DescriptionDS215
Page 173 and 174:
Page 175 and 176:
DS2155Register Name:IMR9Register De
Page 177 and 178:
DS215527.3 BERT Bit CounterOnce BER
Page 179 and 180:
DS215528. PAYLOAD ERROR INSERTION F
Page 181 and 182:
DS215528.1 Number Of Error Register
Page 183 and 184:
DS215529. INTERLEAVED PCM BUS OPERA
Page 185 and 186:
IBO EXAMPLE Figure 29-1DS2155RSYSCL
Page 187 and 188:
DS2155Register Name:ESIBCR1Register
Page 189 and 190:
DS2155Register Name:ESIB1Register D
Page 191 and 192:
DS215532. FRACTIONAL T1/E1 SUPPORTT
Page 193 and 194:
DS215534. JTAG-BOUNDARY-SCAN ARCHIT
Page 195 and 196:
DS2155Select-IR-ScanAll test regist
Page 197 and 198:
DS215534.1 Instruction RegisterThe
Page 199 and 200:
DS215534.2 Test RegistersIEEE 1149.
Page 201 and 202:
BIT PIN SYMBOL TYPE CONTROL BIT DES
Page 203 and 204:
RECEIVE SIDE ESF TIMING Figure 35-2
Page 205 and 206:
RECEIVE SIDE 1.544MHz BOUNDARY TIMI
Page 207 and 208:
TRANSMIT SIDE D4 TIMING Figure 35-6
Page 209 and 210:
TRANSMIT SIDE BOUNDARY TIMING (With
Page 211 and 212:
DS2155TRANSMIT SIDE 2.048MHz BOUNDA
Page 213 and 214:
RECEIVE SIDE BOUNDARY TIMING (With
Page 215 and 216:
RECEIVE SIDE BOUNDARY TIMING, RSYSC
Page 217 and 218:
RECEIVE IBO FRAME INTERLEAVE MODE T
Page 219 and 220:
TRANSMIT SIDE TIMING Figure 35-18DS
Page 221 and 222:
TRANSMIT SIDE BOUNDARY TIMING, TSYS
Page 223 and 224:
TRANSMIT IBO CHANNEL INTERLEAVE MOD
Page 225 and 226:
36. OPERATING PARAMETERSDS2155ABSOL
Page 227 and 228:
37. AC TIMING PARAMETERS AND DIAGRA
Page 229 and 230:
MOTOROLA BUS TIMING (BTS = 1 / MUX
Page 231 and 232:
INTEL BUS READ TIMING (BTS = 0 / MU
Page 233 and 234:
37.3 Receive Side AC Characteristic
Page 235 and 236:
RECEIVE SIDE TIMING, ELASTIC STORE
Page 237 and 238:
37.4 Transmit AC CharacteristicsDS2
Page 239 and 240:
TRANSMIT SIDE TIMING, ELASTIC STORE
Page 241 and 242:
38. MECHANICAL DESCRIPTIONSDS215538
show all

DS2155 T1/E1/J1

Create successful ePaper yourself

Delete template?

Save as template?