DS2155 T1/E1/J1
DS2155 T1/E1/J1
DS2155 T1/E1/J1
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<strong>E1</strong> SYNC/RESYNC CRITERIA Table 11-1<strong>DS2155</strong>FRAME ORMULTIFRAMELEVELFASCRC4CASSYNC CRITERIA RESYNC CRITERIA ITU SPEC.FAS present in frame Nand N + 2, and FAS notpresent in frame N + 1Two valid MF alignmentwords found within 8msValid MF alignment wordfound and previoustimeslot 16 contains codeother than all zerosThree consecutive incorrect FASreceivedAlternate: (<strong>E1</strong>RCR1.2 = 1) Theabove criteria is met or threeconsecutive incorrect bit 2 of non-FAS received915 or more CRC4 code words outof 1000 received in errorTwo consecutive MF alignmentwords received in errorG.7064.1.14.1.2G.7064.2 and 4.3.2G.732 5.2Register Name:<strong>E1</strong>RCR2Register Description: <strong>E1</strong> Receive Control Register 2Register Address: 34hBit # 7 6 5 4 3 2 1 0Name Sa8S Sa7S Sa6S Sa5S Sa4S - - RCLADefault 0 0 0 0 0 0 0 0Bit 0/Receive Carrier Loss (RCL) Alternate Criteria (RCLA). Defines the criteria for a Receive Carrier Loss conditionfor both the framer and Line Interface (LIU)0 = RCL declared upon 255 consecutive zeros (125µs)1 = RCL declared upon 2048 consecutive zeros (1ms)Bit 1/Unused, must be set to zero for proper operation.Bit 2/Unused, must be set to zero for proper operation.Bit 3/Sa4-Bit Select(Sa4S). Set to one to have RLCLK pulse at the Sa4-bit position; set to zero to force RLCLK low duringSa4-bit position. See Functional Timing Diagrams for details.Bit 4/Sa5-Bit Select(Sa5S). Set to one to have RLCLK pulse at the Sa5-bit position; set to zero to force RLCLK low duringSa5-bit position. See Functional Timing Diagrams for details.Bit 5/Sa6-Bit Select(Sa6S). Set to one to have RLCLK pulse at the Sa6-bit position; set to zero to force RLCLK low duringSa6-bit position. See Functional Timing Diagrams for details.Bit 6/Sa7-Bit Select(Sa7S). Set to one to have RLCLK pulse at the Sa7-bit position; set to zero to force RLCLK low duringSa7-bit position. See Functional Timing Diagrams for details.Bit 7/Sa8-Bit Select (Sa8S). Set to one to have RLCLK pulse at the Sa8-bit position; set to zero to force RLCLK low duringSa8-bit position. See Functional Timing Diagrams for details.51 of 242
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