Author's personal copyARTICLE IN PRESSG. Jaberipur, B. Parhami / INTEGRATION, the VLSI journal 41 (2008) 49–64 53To keep the complexity of adder cells in check, it isdesirable to restrict the cardinality of r**edu**ndant digits to 4,thus making them representable with 2 bits (i.e., theminimum possible for a r**edu**ndant digit). This constraintleads to 1 bit of r**edu**ndancy per radix-2 h digit. Unfortunately,such encoding efficiency is gained at the cost ofnarrowing the spectrum of symmetric hybrid r**edu**ndancyto only one case besides the fully r**edu**ndant BSD numbersystem, as is stated below.Corollary 3 (Restricted symmetry with single r**edu**ndancybit). In the case of single r**edu**ndancy bit per radix-2 h digit,there are only two possible symmetric digit sets in righthybrid-r**edu**ndantnumber system: fully r**edu**ndant BSD **and**minimally r**edu**ndant radix-4.Proof. Applying the constraint n þ pp3 (i.e., 2-bit encodingof r**edu**ndant digits) to the result of Lemma 1 (i.e.,n ¼ p þ 2 h 2) leads to pp 5 22 h 1 . Given that pX0, thelatter inequality holds only for hp2. The case h ¼ 1leadston ¼ p ¼ 1 (i.e., fully r**edu**ndant BSD). The case h ¼ 2resultsin p ¼ 0**and**n ¼ 2 (i.e., minimally r**edu**ndant radix-4). &In constant-time addition of radix-r r**edu**ndant numbers,the sum digit in radix-r position i, is a function of theoper**and** digits in the same position i **and** at least those ofposition i 1 [8].Definition 4 (Look-back). The number of consecutiveradix-2 h oper**and** digits in the right context of a radix-2 hposition i, which contribute to the value of the sum digit inposition i, constitutes the look-back of position i.For digit sets with rX3 **and** most cases of r ¼ 2 (a fewcases of r ¼ 2 **and** all cases of r ¼ 1), it has been shownthat the required look-back is 1 (2). In other words, thesum digit in radix-2 h position i is a function of four (six)oper**and** digits; the two oper**and** digits in radix-2 h position i**and** the two in radix-2 h position i 1 (**and** the two in radix-2 h position i 2) [8]. It is interesting to note that for theminimally r**edu**ndant case of r ¼ 1, the look-back of 2leads to more complex addition schemes. Thus, therepresentational cost reflected in rX3 may be more thancompensated for by the need for smaller look-back. Thefew cases of r ¼ 2 which require a look-back of 2 are bestavoided, because they offer no advantage to compensatefor the more complex addition scheme.Definition 5 (Partial look-back). When, depending on theencoding **and** implementation (e.g., HSD in [7]), some bitpositions of a look-back digit do not contribute to thederivation of a position sum, the look-back is said to bepartial.The abstract view of a hybrid-r**edu**ndant adder in Fig. 1is based on a primary perception of complete separation ofadder cells for r**edu**ndant **and** nonr**edu**ndant positions. Theonly connection between the two kinds of cells would bethrough carry **and**/or borrow propagation. But Phataket al. have used a technique called equal-weight grouping(EWG), which entrusts the higher bits of a digit in radix-2position i 1, together with lower bits of a radix-2 digit inposition i to a single adder cell in position i. This adder cellhas been shown to be less complex than one designedwithout EWG. To investigate the consequences of EWGfor hybrid-r**edu**ndant addition, we consider the 2-bitrepresentation of a r**edu**ndant digit x i to be hx h i xl ii, withx h i **and** x l i having the weights 2 iþ1 **and** 2 i , respectively.We then define EWG formally as follows.Definition 6 (Equal-weight grouping, EWG). The higherweighted bit of a r**edu**ndant digit in radix-2 position i 1has the same weight as the lower-weighted bit (only bit, inthe case of a nonr**edu**ndant position) of the digit in positioni, thus constituting a group of 2 equally weighted bits,regardless of bit polarities. EWG allows us to intermix theprocessing of bits from various radix-2 positions in order toobtain a more efficient hardware realization.Definition 7 (Representationally closed addition). An additionscheme is representationally closed when the twooper**and**s are from the same number system (i.e., theequally weighted digits of the two oper**and**s belong to thesame digit set) **and** the value of the resultant sum digit, inthe corresponding digit-position, also belongs to the samedigit set. Furthermore, representational closure requiresthat these identical digit sets all have the same encoding.Representational closure is vital for general-purposearithmetic, where the same adder circuit is reused toprocess the results of previous additions. But equal-weightgrouping, although simplifying adder cells in fully r**edu**ndantadders, does not always lead to representationalclosure in true hybrid-r**edu**ndant addition. For example,Position indexi i – 1i– 2Position sum range[−4, 2] [−4, 2] [−4, 2]Equal-weightDecompositionRecomposition[0, 2] + [–2, 0] [0, 2] + [–2, 0] [0, 2] + [–2, 0][–2, 2] [–2, 2] [–2, 2][–2, 0] + [0, 1] [–2, 0] + [0, 1] [–2, 0] + [0, 1][–2, 1] [–2, 1] [–2, 1]Fig. 2. Addition of fully r**edu**ndant SDB oper**and**s with equal-weight grouping.

Author's personal copy54ARTICLE IN PRESSG. Jaberipur, B. Parhami / INTEGRATION, the VLSI journal 41 (2008) 49–64Position indexPosition sum rangei + 1Nonr**edu**ndantiNonr**edu**ndanti – 1R**edu**ndanti – 2Nonr**edu**ndant[0, 2] [–4, 2] [0, 2]Equal-weight[0, 2] + [–2, 0] [0, 2] [0, 2] + [0, 1][–2, 2] [0, 3]Emitted transfer[0, 1][–2, 0] [0, 2] + [0, 1][0, 3][0, 1]Absorbed transfer[0, 1][–2, 0] + [0, 1] [0, 1] [0, 1][–2, 1]Fig. 3. Addition of true SDB-hybrid-r**edu**ndant oper**and**s with equal-weight grouping.Figs. 2 **and** 3 represent, by means of digit-set conversion[15], a fully SDB-r**edu**ndant **and** a true SDB-hybridr**edu**ndantaddition. Composition of two SDB digits resultsin the interval ½ 4; 2Š, whereas that of two posibits produces½0; 2Š. The processes of decomposition (e.g., ½ 4; 2Š¼ 2 ½ 2; 0Šþ½0; 2Š) **and** recomposition (e.g., ½ 2; 0Šþ½0; 1Š ¼½ 2; 1Š) are self-explanatory. As is evident fromFigs. 2 **and** 3, the negabits of oper**and**s in position i 1,contribute to the generation of negabits in position i. Thiscauses a representational shift which, owing to the additionof fully r**edu**ndant oper**and**, remains hidden in Fig. 2, butthat is clearly visible in Fig. 3. It is easy to see that the samerepresentationally shifted behavior occurs for true SDChybrid-r**edu**ndantaddition with r**edu**ndant digits in ½0; 3Š,while a direct adaptation of an addition scheme based onthe adder cells given in [4] for the same number systemwould be representationally closed. Also representationallyclosed addition of true SDB-hybrid oper**and**s is certainlypossible (e.g., [16]). The sink functionality of position imay be seen in Fig. 3, where carry propagation starts atposition i þ 1.The fully r**edu**ndant SDB-hybrid addition of Fig. 2 isbased on digit set conversion of [13], where the resultantdigit may assume any value of the original digit set ½ 2; 1Š.But an adder cell for the same purpose, offered in [12], doesnot preserve the oper**and**’s digit set **and** produces digitvalues in ½ 1; 1Š. A brief assessment of the consequences ofthis r**edu**ction in digit sets is offered below.Definition 8 (Digit set preservation). The digit set of anumber representation is preserved under an arithmeticoperation if the result digit may assume all the values in thedigit set.Example 2 (Impact of digit set nonpreservation). The digitset conversions of Figs. 2 **and** 3 preserve the digit set½ 2; 1Š. But the addition scheme of [12] for SDB-hybriddigits r**edu**ces the digit set ½ 2; 1Š to ½ 1; 1Š, as noted in [13].Briefly, with the scheme in Figs. 2 **and** 3, two 1 r**edu**ndantdigits in position i are converted to 1 1 (in positions i þ 1**and** i) via equal-weight grouping, leading to a digit 2inposition i þ 1. On the other h**and**, the addition scheme of[12] decomposes the resulting 2 digit into 1 0, therebyaffecting position i þ 2.A drawback of the digit-set nonpreserving additionscheme, mentioned in Example 2, is that addition of mostsignificant digits may signal a false overflow. The digit-setpreserving scheme may also signal an apparent overflow[17], but this is less likely.3. Realization of hybrid-r**edu**ndant addersThe adder presented by Phatak **and** Koren for BSDhybrid-r**edu**ndantoper**and**s (first entry in our Table 2, [7]Fig. 1), with its r**edu**ndant radix-2 positions utilizing theadder cell of [18], requires 42 (32) transistors for r**edu**ndant(nonr**edu**ndant) positions. Phatak **and** Koren’s correspondingdesign for r**edu**ndant radix-2 positions withSDB or SCB r**edu**ndant digits (second **and** third entriesin our Table 2, [12], Fig. 3a), requires seven multiplexers, afew gates, **and** several inverters. An analysis of the latter ofthese two adders shows that the effect of equal-weightgrouping is to produce a representationally shifted result inwhich the r**edu**ndant position moves from i at the input toi þ 1 at the output (see also the explanations followingDefinition 7 in Section 2). The foregoing discussionsuggests that for designing a true SDB-hybrid-r**edu**ndantadder that is representationally closed, specialized addercells (besides the multiplexer-based design cited above) areneeded for isolated r**edu**ndant positions **and** immediatelyhigher-weighted nonr**edu**ndant positions. A high-leveldesign for such adders is offered in [16].Aoki et al. [9] have shown that an augmented (4; 2)-compressor, with some input/output inverters, can be usedfor r**edu**ndant positions of a BSD-hybrid-r**edu**ndant adder.Kornerup has used such augmented (4; 2)-compressors notonly for the r**edu**ndant position, as above, but also in placeof the multiplexer-based cell of Phatak **and** Koren (see [13],Sections 4.1 **and** 4.2). However, none of these modificationsleads to representational closure when applied to atrue hybrid-r**edu**ndant adder. Aoki et al. [9] have alsoshown that st**and**ard full-adders, augmented by suitable