Author's personal copyARTICLE IN PRESSG. Jaberipur, B. Parhami / INTEGRATION, the VLSI journal 41 (2008) 49–64 53To keep the complexity of adder cells in check, it isdesirable to restrict the cardinality of redundant digits to 4,thus making them representable with 2 bits (i.e., theminimum possible for a redundant digit). This constraintleads to 1 bit of redundancy per radix-2 h digit. Unfortunately,such encoding efficiency is gained at the cost ofnarrowing the spectrum of symmetric hybrid redundancyto only one case besides the fully redundant BSD numbersystem, as is stated below.Corollary 3 (Restricted symmetry with single redundancybit). In the case of single redundancy bit per radix-2 h digit,there are only two possible symmetric digit sets in righthybrid-redundantnumber system: fully redundant BSD andminimally redundant radix-4.Proof. Applying the constraint n þ pp3 (i.e., 2-bit encodingof redundant digits) to the result of Lemma 1 (i.e.,n ¼ p þ 2 h 2) leads to pp 5 22 h 1 . Given that pX0, thelatter inequality holds only for hp2. The case h ¼ 1leadston ¼ p ¼ 1 (i.e., fully redundant BSD). The case h ¼ 2resultsin p ¼ 0andn ¼ 2 (i.e., minimally redundant radix-4). &In constant-time addition of radix-r redundant numbers,the sum digit in radix-r position i, is a function of theoperand digits in the same position i and at least those ofposition i 1 .Definition 4 (Look-back). The number of consecutiveradix-2 h operand digits in the right context of a radix-2 hposition i, which contribute to the value of the sum digit inposition i, constitutes the look-back of position i.For digit sets with rX3 and most cases of r ¼ 2 (a fewcases of r ¼ 2 and all cases of r ¼ 1), it has been shownthat the required look-back is 1 (2). In other words, thesum digit in radix-2 h position i is a function of four (six)operand digits; the two operand digits in radix-2 h position iand the two in radix-2 h position i 1 (and the two in radix-2 h position i 2) . It is interesting to note that for theminimally redundant case of r ¼ 1, the look-back of 2leads to more complex addition schemes. Thus, therepresentational cost reflected in rX3 may be more thancompensated for by the need for smaller look-back. Thefew cases of r ¼ 2 which require a look-back of 2 are bestavoided, because they offer no advantage to compensatefor the more complex addition scheme.Definition 5 (Partial look-back). When, depending on theencoding and implementation (e.g., HSD in ), some bitpositions of a look-back digit do not contribute to thederivation of a position sum, the look-back is said to bepartial.The abstract view of a hybrid-redundant adder in Fig. 1is based on a primary perception of complete separation ofadder cells for redundant and nonredundant positions. Theonly connection between the two kinds of cells would bethrough carry and/or borrow propagation. But Phataket al. have used a technique called equal-weight grouping(EWG), which entrusts the higher bits of a digit in radix-2position i 1, together with lower bits of a radix-2 digit inposition i to a single adder cell in position i. This adder cellhas been shown to be less complex than one designedwithout EWG. To investigate the consequences of EWGfor hybrid-redundant addition, we consider the 2-bitrepresentation of a redundant digit x i to be hx h i xl ii, withx h i and x l i having the weights 2 iþ1 and 2 i , respectively.We then define EWG formally as follows.Definition 6 (Equal-weight grouping, EWG). The higherweighted bit of a redundant digit in radix-2 position i 1has the same weight as the lower-weighted bit (only bit, inthe case of a nonredundant position) of the digit in positioni, thus constituting a group of 2 equally weighted bits,regardless of bit polarities. EWG allows us to intermix theprocessing of bits from various radix-2 positions in order toobtain a more efficient hardware realization.Definition 7 (Representationally closed addition). An additionscheme is representationally closed when the twooperands are from the same number system (i.e., theequally weighted digits of the two operands belong to thesame digit set) and the value of the resultant sum digit, inthe corresponding digit-position, also belongs to the samedigit set. Furthermore, representational closure requiresthat these identical digit sets all have the same encoding.Representational closure is vital for general-purposearithmetic, where the same adder circuit is reused toprocess the results of previous additions. But equal-weightgrouping, although simplifying adder cells in fully redundantadders, does not always lead to representationalclosure in true hybrid-redundant addition. For example,Position indexi i – 1i– 2Position sum range[−4, 2] [−4, 2] [−4, 2]Equal-weightDecompositionRecomposition[0, 2] + [–2, 0] [0, 2] + [–2, 0] [0, 2] + [–2, 0][–2, 2] [–2, 2] [–2, 2][–2, 0] + [0, 1] [–2, 0] + [0, 1] [–2, 0] + [0, 1][–2, 1] [–2, 1] [–2, 1]Fig. 2. Addition of fully redundant SDB operands with equal-weight grouping.
Author's personal copy54ARTICLE IN PRESSG. Jaberipur, B. Parhami / INTEGRATION, the VLSI journal 41 (2008) 49–64Position indexPosition sum rangei + 1NonredundantiNonredundanti – 1Redundanti – 2Nonredundant[0, 2] [–4, 2] [0, 2]Equal-weight[0, 2] + [–2, 0] [0, 2] [0, 2] + [0, 1][–2, 2] [0, 3]Emitted transfer[0, 1][–2, 0] [0, 2] + [0, 1][0, 3][0, 1]Absorbed transfer[0, 1][–2, 0] + [0, 1] [0, 1] [0, 1][–2, 1]Fig. 3. Addition of true SDB-hybrid-redundant operands with equal-weight grouping.Figs. 2 and 3 represent, by means of digit-set conversion, a fully SDB-redundant and a true SDB-hybridredundantaddition. Composition of two SDB digits resultsin the interval ½ 4; 2Š, whereas that of two posibits produces½0; 2Š. The processes of decomposition (e.g., ½ 4; 2Š¼ 2 ½ 2; 0Šþ½0; 2Š) and recomposition (e.g., ½ 2; 0Šþ½0; 1Š ¼½ 2; 1Š) are self-explanatory. As is evident fromFigs. 2 and 3, the negabits of operands in position i 1,contribute to the generation of negabits in position i. Thiscauses a representational shift which, owing to the additionof fully redundant operand, remains hidden in Fig. 2, butthat is clearly visible in Fig. 3. It is easy to see that the samerepresentationally shifted behavior occurs for true SDChybrid-redundantaddition with redundant digits in ½0; 3Š,while a direct adaptation of an addition scheme based onthe adder cells given in  for the same number systemwould be representationally closed. Also representationallyclosed addition of true SDB-hybrid operands is certainlypossible (e.g., ). The sink functionality of position imay be seen in Fig. 3, where carry propagation starts atposition i þ 1.The fully redundant SDB-hybrid addition of Fig. 2 isbased on digit set conversion of , where the resultantdigit may assume any value of the original digit set ½ 2; 1Š.But an adder cell for the same purpose, offered in , doesnot preserve the operand’s digit set and produces digitvalues in ½ 1; 1Š. A brief assessment of the consequences ofthis reduction in digit sets is offered below.Definition 8 (Digit set preservation). The digit set of anumber representation is preserved under an arithmeticoperation if the result digit may assume all the values in thedigit set.Example 2 (Impact of digit set nonpreservation). The digitset conversions of Figs. 2 and 3 preserve the digit set½ 2; 1Š. But the addition scheme of  for SDB-hybriddigits reduces the digit set ½ 2; 1Š to ½ 1; 1Š, as noted in .Briefly, with the scheme in Figs. 2 and 3, two 1 redundantdigits in position i are converted to 1 1 (in positions i þ 1and i) via equal-weight grouping, leading to a digit 2inposition i þ 1. On the other hand, the addition scheme of decomposes the resulting 2 digit into 1 0, therebyaffecting position i þ 2.A drawback of the digit-set nonpreserving additionscheme, mentioned in Example 2, is that addition of mostsignificant digits may signal a false overflow. The digit-setpreserving scheme may also signal an apparent overflow, but this is less likely.3. Realization of hybrid-redundant addersThe adder presented by Phatak and Koren for BSDhybrid-redundantoperands (first entry in our Table 2, Fig. 1), with its redundant radix-2 positions utilizing theadder cell of , requires 42 (32) transistors for redundant(nonredundant) positions. Phatak and Koren’s correspondingdesign for redundant radix-2 positions withSDB or SCB redundant digits (second and third entriesin our Table 2, , Fig. 3a), requires seven multiplexers, afew gates, and several inverters. An analysis of the latter ofthese two adders shows that the effect of equal-weightgrouping is to produce a representationally shifted result inwhich the redundant position moves from i at the input toi þ 1 at the output (see also the explanations followingDefinition 7 in Section 2). The foregoing discussionsuggests that for designing a true SDB-hybrid-redundantadder that is representationally closed, specialized addercells (besides the multiplexer-based design cited above) areneeded for isolated redundant positions and immediatelyhigher-weighted nonredundant positions. A high-leveldesign for such adders is offered in .Aoki et al.  have shown that an augmented (4; 2)-compressor, with some input/output inverters, can be usedfor redundant positions of a BSD-hybrid-redundant adder.Kornerup has used such augmented (4; 2)-compressors notonly for the redundant position, as above, but also in placeof the multiplexer-based cell of Phatak and Koren (see ,Sections 4.1 and 4.2). However, none of these modificationsleads to representational closure when applied to atrue hybrid-redundant adder. Aoki et al.  have alsoshown that standard full-adders, augmented by suitable