DESIGN NOTEStraight Talk About Jitter TalkBy: Eduard Van Keulen, Sr. Strategic Applications Engineer, Micrel, Inc.Jitter is typically a variation in cycle lengthor phase of a clock signal. These phase variationsare partly random and partly deterministicor periodic.Jitter and phase noise are essentially the same,wherein one looks at jitter in the time domainand phase noise in the frequency domain. Therandom variations are mostly caused by thermalnoise and the deterministic variations are fromcross talk with other signals. With high-end,low noise clocks one sees mostly random noisewhen a lot of effort was expended to preventdeterministic components in the jitter. Randomjitter can be higher in ‘lower-end’ clocks, butusually, when period jitter gets to levels suchas 300ps peak-to-peak, it is dominated bydeterministic jitter. This is what happens withclocks generated by ICs that process a variety ofsignals. Take an FPGA for example; there maybe many other signals inside the FPGA that cancross talk to the generated clock and period jitterworse than 300ps peak-to-peak can occur.General purpose, multi output, multi PLL clockgenerators can also generate clocks with ratherlarge period jitter. This is again caused by manydifferent signals sharing the same silicon andpower domains and cross talk causing deterministicjitter. This article will discuss the variouscauses of jitter and how best to manage thecondition.Time synchronizing systems such as IEEE1588or time reference systems like GPS can generateclocks with a very accurate frequency, adoptingthe accuracy of the system’s reference clock.These systems ‘assemble’ this clock with timeslices to assure an accurate average frequency.Unfortunately the addition and removal of timeslices causes very significant jitter. Period jitterin excess of 20,000ps peak-to-peak has beenobserved. See Figure 1 below with a waveform ofa 10MHz clock from an IEEE1588 system.Figure 1: The deterministic jitter from adding and removingdiscrete time slices is clearly visible.Jitter attenuating devices have been around fora while and are used to clean up noisy clocks.These devices consist of a synthesizer that recreatesthe incoming clock but with as little as possiblejitter and phase noise in the output clock.The synthesizer locks to the incoming clock witha slow lock (low phase locked loop bandwidth)that avoids passing most of the jitter and phasenoise to the output clock. Frequently, a jitterattenuator locks a voltage controlled crystaloscillator to the incoming clock for good phasenoise performance. Jitter attenuators requireexternal components such as a crystal and loopfilter components. One can also use jitter attenuatormodules with the whole jitter attenuatingcircuit integrated in one unit. However, althoughthis solution does a good job of cleaning jitter,for most applications they are bulky, expensive,and over designed.To simplify the design process, Micrel hasreleased a series of ”JitterBlocker” ICs that aresmall, very simple to use, and require the additionof no external components such as crystalsor loop filter components. In addition, these devicesalso offer the multiplication of the incomingsignal to up to 850MHz. The designer need onlyapply power and an input clock to create cleanedup output clocks. JitterBlockers are programmedat the factory for the best possible jitter blockingperformance in any specific application. Micrelcurrently offers three variations.Micrel’s PL902, for example, focuses on singleendedclocks with very large amounts of jittersuch as the clock from an IEEE1588 system. Inthis case, the Micrel solution would reduce thejitter to below 100ps peak-to-peak. Figure 2shows a 10MHz IEEE1588 clock at the input ofthe PL902 and the PL902 output clock.➡Figure 2: 10MHz IEEE1588 clock from JitterBlocker inputto JitterBlocker output.The PL902 JitterBlocker is available in a smallSOT23 package and does not require anyexternal components. The PL902 is also verysuited to clean clocks generated by an FPGA orASIC. Figure 3 shows a jitter histogram of a clockwith 460ps peak-to-peak of period jitter that isreduced to only 75ps peak-to-peak after passingthrough the PL902.181.800.FUTURE.1 • www.FutureElectronics.com
DESIGN NOTE➡Figure 3: Deterministic/jitter at JitterBlocker input cleaned upat JitterBlocker outputThe PL902 JitterBlocker is factory programmableand can be configured to clean clock frequenciesbetween 1MHz and 200MHz with single endedCMOS logic. Frequency translation is possible sothe designer can take a ”dirty” 10MHz clock forexample and turn it into a clean 50MHz clock.The PL902 also has fan-out capability with up tothree clock outputs.Micrel’s PL903 and PL904 JitterBlockers focus onphase jitter cleaning with differential or singleendedclock outputs. This function is performedby attenuating spurious components in thephase noise and to lower the phase noise floorto achieve enhanced phase jitter. The PL903 andPL904 also do not require any external componentsto aid the jitter attenuation, so it is easyto insert them into a clock path that requirescleaning. Figure 4 shows an example phase noiseplot of a clock with a large spurious signal fromcross-talk with other signals.➡Figure 4: Spur at JitterBlocker input attenuated and phasenoise floor loweredIn this example, the spurious signal dominatesthe phase jitter with a value of 4.9ps RMS. Afterpassing through the JitterBlocker, the spurioussignal is attenuated with more than 20dB andthe noise floor at 10MHz from the carrier has alsodropped significantly. The result is just 0.46psRMS of phase jitter in the output clock.Systems such as Giga-bit Ethernet requiredifferential clocks with very low phase noise atfrequencies such as 156.25MHz. Micrel’s PL903and PL904 are well suited to clean up theseclocks in case cross-talk has added spurioussignals to the phase noise. Through factoryprogramming, the output logic of the PL903and PL904 can be set to LVDS, HCSL, LVPECL orLVCMOS. Customization through programmingalso allows frequency translation. For example,an input clock of 156.25MHz can be cleanedand converted to 625MHz at the same time. Themaximum output frequency for the PL903 andPL904 is 850MHz. The PL903 is available in a4 x 4mm QFN package and the PL904 is availablein a 5 x 5mm QFN package.SummaryWith these JitterBlockers, Micrel has simplifiedjitter attenuation and made it significantly lessexpensive. This makes jitter cleaning affordablefor most systems. Using the example of aclock from the IEEE1588 system, Micrel’s PL902that fits in a small SOT23 package, can reduce20,000ps-pp of period jitter to 100ps-pp.The PL903 and PL904 can reduce pico secondsof phase jitter to the femto seconds requiredfor systems such as Giga-bit Ethernet. TheJitterBlockers do all this without the need forexternal components like crystals or loop filters.To buy products or download data, go towww.FutureElectronics.com/FTM1.800.FUTURE.1 • www.FutureElectronics.com19
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