Help You to Win! C*Core's Scalable Design Platform - Power.org
Help You to Win! C*Core's Scalable Design Platform - Power.org
Help You to Win! C*Core's Scalable Design Platform - Power.org
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C*Core CPU Road MapThe <strong>Power</strong> Architecture and <strong>Power</strong>.<strong>org</strong> word marks and the <strong>Power</strong> and <strong>Power</strong>.<strong>org</strong> logos and related marks are trademarks and service marks licensed by <strong>Power</strong>.<strong>org</strong>.
Application of C*CoreThe <strong>Power</strong> Architecture and <strong>Power</strong>.<strong>org</strong> word marks and the <strong>Power</strong> and <strong>Power</strong>.<strong>org</strong> logos and related marks are trademarks and service marks licensed by <strong>Power</strong>.<strong>org</strong>.
C*Core Business ModelThe <strong>Power</strong> Architecture and <strong>Power</strong>.<strong>org</strong> word marks and the <strong>Power</strong> and <strong>Power</strong>.<strong>org</strong> logos and related marks are trademarks and service marks licensed by <strong>Power</strong>.<strong>org</strong>.
Business Model of C*Core• IP Provider– Embedded C*Core CPU– C*Core based SoC design platform• <strong>Design</strong> Service Company– Turn-key design– Cus<strong>to</strong>m chip specification ->GDS– RTL <strong>to</strong> GDS– Gate netlist <strong>to</strong> GDS– System specification <strong>to</strong> GDSThe <strong>Power</strong> Architecture and <strong>Power</strong>.<strong>org</strong> word marks and the <strong>Power</strong> and <strong>Power</strong>.<strong>org</strong> logos and related marks are trademarks and service marks licensed by <strong>Power</strong>.<strong>org</strong>.
Business Model of C*Core• Provide the very best products• Make it easier <strong>to</strong> use our products• Prove that what we do actually works effectively…VerticalBusinessIntegrationSpecificationCMMI-Style ApproachAnalyzeImproveC*Core <strong>Design</strong> <strong>Platform</strong> :No need <strong>to</strong> re-invent thewheel...ImplementationVerificationProductizationThe <strong>Power</strong> Architecture and <strong>Power</strong>.<strong>org</strong> word marks and the <strong>Power</strong> and <strong>Power</strong>.<strong>org</strong> logos and related marks are trademarks and service marks licensed by <strong>Power</strong>.<strong>org</strong>.
C*Core SoC <strong>Design</strong> <strong>Platform</strong>The <strong>Power</strong> Architecture and <strong>Power</strong>.<strong>org</strong> word marks and the <strong>Power</strong> and <strong>Power</strong>.<strong>org</strong> logos and related marks are trademarks and service marks licensed by <strong>Power</strong>.<strong>org</strong>.
PLBC*Core SoC <strong>Design</strong> <strong>Platform</strong>• C*Core SoC design platform based on C9000– Make you easy <strong>to</strong> built up complex SoC based on C9000 for Variety ofapplications• Digital TV• Network• Multimedia for Au<strong>to</strong>mobile• Video Surveillance• …IrDAAudioCodecPWMLCDCSD/MMCPCIEUSBNANDGPUPLLC9000SPIUARTPS2ADCAPBAXI2APBMACSATAAXI BUSHD VideoDecoderTV EncDSPHDMIPLB2AXIDDR2/3DMAI2SRTCJTAGPORTimerThe <strong>Power</strong> Architecture and <strong>Power</strong>.<strong>org</strong> word marks and the <strong>Power</strong> and <strong>Power</strong>.<strong>org</strong> logos and related marks are trademarks and service marks licensed by <strong>Power</strong>.<strong>org</strong>.
C*Core SoC <strong>Design</strong> <strong>Platform</strong>• C*Core C9000– High-performance (2.5 DMIPS/MHz ), Out-of-Order, 5-issue / 9-pipeline superscalar RISC CPU– Integrated floating-point unit– L1 caches that support cache coherency in SMP systems– Tightly coupled <strong>to</strong> an L2 cache controller that supports coherency managementThe <strong>Power</strong> Architecture and <strong>Power</strong>.<strong>org</strong> word marks and the <strong>Power</strong> and <strong>Power</strong>.<strong>org</strong> logos and related marks are trademarks and service marks licensed by <strong>Power</strong>.<strong>org</strong>.
C*Core SoC <strong>Design</strong> <strong>Platform</strong>• IPs in CSOC9000 <strong>Platform</strong>– CPU• C9000– Operating System• Android 2.3 /Linux 2.6.3x, Support Adobe Flash Player 10.3.– HD Video• 4Ch 1080P Encode and Decode, Support AVS, Google WebM videoformat– On Chip DDR2/3 SRAM Controller– HD Audio• DTS-HD 7.1 Master Audio, Dolby 7.1 TrueHD, and DSP is integrated– 2D/3D GPU• Support OPENGL ES 2.0 and OPEN VG 1.1.– Wireless• Wi-Fi, Blue<strong>to</strong>oth, 3G,GPS baseband– Display• 2048xN TFT panel muti-point <strong>to</strong>uch panel– Interface• PCIe/USB/HDMI /SATAII/LVDS/TV CVBS/• Ethernet 10/100/1000 Mbps, full-duplex MACsThe <strong>Power</strong> Architecture and <strong>Power</strong>.<strong>org</strong> word marks and the <strong>Power</strong> and <strong>Power</strong>.<strong>org</strong> logos and related marks are trademarks and service marks licensed by <strong>Power</strong>.<strong>org</strong>.
PLBC*Core SoC <strong>Design</strong> <strong>Platform</strong>• C*Core SoC design platform based on C2000– Make you easy <strong>to</strong> built up complex SoC based on C2000 for Variety ofapplications• Industry Control• Network• Au<strong>to</strong>motive• OA• Wireless• …IrDA1553BPWMLCDCSD/MMCPCIeUSB2.0NAND FlashContllerPLLCACHEJTAGC2000SPIUARTPS2CANAPBAXI2APBAXI BUS插 入 C2000 platfromEthernetSATAEBMTV EncDSPPLB2AXIMMUTraceDDR2/3IICGPIOsRTCINTCDMAThe <strong>Power</strong> Architecture and <strong>Power</strong>.<strong>org</strong> word marks and the <strong>Power</strong> and <strong>Power</strong>.<strong>org</strong> logos and related marks are trademarks and service marks licensed by <strong>Power</strong>.<strong>org</strong>.
C*Core SoC <strong>Design</strong> <strong>Platform</strong>• C*Core C2000Features– Five-stage 32-bit singleissuepipeline– 32 General PurposeRegisters (GPR)/Staticbranch prediction– MMU with a 64-entryI-PortI-OCMBus InterfaceCacheI-CacheControllerMMUShadowITLBC2000PLB/AHB Master WrapperInstructionCacheUnifiedTLBDataCacheD-CacheControllerShadowDTLBD-PortD-OCM– Separate instruction anddata L1 caches, withconfigurable size– 1.52 DMIPS/MHzAPUCPUInstruction UnitPre-fetchBuffersDecoderExecute UnitALU32 GPRsMACDCR– Support PLB4/AXI/AHB/OCM/DCR bus pro<strong>to</strong>calsJTAGTraceFacilitiesDebugUnitTimersPIT FIT WatchdogInterruptUnitInterruptsThe <strong>Power</strong> Architecture and <strong>Power</strong>.<strong>org</strong> word marks and the <strong>Power</strong> and <strong>Power</strong>.<strong>org</strong> logos and related marks are trademarks and service marks licensed by <strong>Power</strong>.<strong>org</strong>.
C*Core SoC <strong>Design</strong> <strong>Platform</strong>• C*Core C2002 Features– Optimized for au<strong>to</strong>motive application, compatible with C2000 in C/C++ level– Three <strong>to</strong> Four-stage single-issue pipeline– Optional I-Cache optimized for embedded-flash– AHB bus with enhanced ECC(SEC/DED) support– Faster Interrupt response with vec<strong>to</strong>r interrupt support– Optional multiple ports Memory protection unit– 1.6 DMIPS/MHzThe <strong>Power</strong> Architecture and <strong>Power</strong>.<strong>org</strong> word marks and the <strong>Power</strong> and <strong>Power</strong>.<strong>org</strong> logos and related marks are trademarks and service marks licensed by <strong>Power</strong>.<strong>org</strong>.
C*Core SoC <strong>Design</strong> <strong>Platform</strong>• IPs in CSOC2000 <strong>Platform</strong>– CPU• C2000/C2002– Operating System• Linux 2.6.3x.– On Chip DDR2/3 SRAM Controller– HD Audio• DTS-HD 7.1 Master Audio, Dolby 7.1 TrueHD, and DSP is integrated– Display• 2048xN TFT panel muti-point <strong>to</strong>uch panel– Interface• PCIe/USB/SATAII/LVDS/TV CVBS• Ethernet 10/100/1000 Mbps, full-duplex MACsThe <strong>Power</strong> Architecture and <strong>Power</strong>.<strong>org</strong> word marks and the <strong>Power</strong> and <strong>Power</strong>.<strong>org</strong> logos and related marks are trademarks and service marks licensed by <strong>Power</strong>.<strong>org</strong>.
C*Core SoC <strong>Design</strong> <strong>Platform</strong>• C*Core SoC design platform based on C300– Make you easy <strong>to</strong> built up SoC based on C300 for Variety ofapplications• Security Information• Touch Panel• Industrial control• …CDK SoC-<strong>Platform</strong>C*CoreC300TIM SPIPIT SCIRTC I2CPLL RSAVerification IPDatabaseMCEICDMA1553BCANPMUAMBA 2.0 ADCUCI PS2 SDCTICLCDNFCUSBDESECCTRNG PHY FlashFirmwareThe <strong>Power</strong> Architecture and <strong>Power</strong>.<strong>org</strong> word marks and the <strong>Power</strong> and <strong>Power</strong>.<strong>org</strong> logos and related marks are trademarks and service marks licensed by <strong>Power</strong>.<strong>org</strong>.
C*Core SoC <strong>Design</strong> <strong>Platform</strong>• C*Core C300 Features– 32bit load/s<strong>to</strong>re architecture– Single cycle 32×16 multiplier– 4 stage pipeline– Fixed-length 16-bitinstructions– 16x32bit general purposeregisters– Bus pro<strong>to</strong>col support CLB/AHB– Fast interrupt support– 16x32bit alternative registersfor fast context switching– Vec<strong>to</strong>red/au<strong>to</strong>-vec<strong>to</strong>redinterrupts– 128 interrupt/exceptionvec<strong>to</strong>rsThe <strong>Power</strong> Architecture and <strong>Power</strong>.<strong>org</strong> word marks and the <strong>Power</strong> and <strong>Power</strong>.<strong>org</strong> logos and related marks are trademarks and service marks licensed by <strong>Power</strong>.<strong>org</strong>.
C*Core SoC <strong>Design</strong> <strong>Platform</strong>• IPs in CSOC300 <strong>Platform</strong>– CPU• C300– Embedded FLASH/PROM Interface– NAND Flash Controller• Support MLC Nandflash: Samsung, Micron, ST• Support 72 bits ECC• Support boot from NAND flash– SD/MMC• Compatible with SD Host Controller 2.0,MMC3.31,4.0,4.1• Compatible with SDIO Card specification 1.0.1– USB2.0 Host/Slave• Support USB2.0 Device or Host• Two USB ports, can be used as USB Dangle for blue <strong>to</strong>oth, WLAN, or 3G• Support EHCI– 12 bit ADC• For Keypad scan, Touch Screen, Temperature detection– Interface• SPI/UART/7816/PWM/IIC/EPORT/CAN/1553B/PS2…– Support RSA,ECC,SHA-1,MD5,AES,3DES,SHA, and OSCA (SM1~SM4)– TRNGThe <strong>Power</strong> Architecture and <strong>Power</strong>.<strong>org</strong> word marks and the <strong>Power</strong> and <strong>Power</strong>.<strong>org</strong> logos and related marks are trademarks and service marks licensed by <strong>Power</strong>.<strong>org</strong>.
C*Core SoC <strong>Design</strong> <strong>Platform</strong>• C*Core SoC design platform based on CSOC000– Make you easy <strong>to</strong> built up complex SoC based on CS00 for Variety ofapplications, especially for Ultra LOW POWER applications.• Security Information• Portable S<strong>to</strong>rage• Touch Panel• Smart Meters• …CDK SoC-<strong>Platform</strong>C*CoreCS00TIM SPIPIT SCIRTC I2CPLL RSAVerification IPDatabaseMCEICDMA1553BCANSWPAHB liteADCADC PS2 SD/MMCTIC7816-3NFCUSBDESOSCACTRNG PHY FlashFirmwareThe <strong>Power</strong> Architecture and <strong>Power</strong>.<strong>org</strong> word marks and the <strong>Power</strong> and <strong>Power</strong>.<strong>org</strong> logos and related marks are trademarks and service marks licensed by <strong>Power</strong>.<strong>org</strong>.
C*Core SoC <strong>Design</strong> <strong>Platform</strong>• C*Core CS00 Features• ¬ Ultra Low power 32bit RISC Core• ¬ Optimized 3-stage pipeline• ¬ Configurable 32x32bit hardware multiplier(Single Cycle or 32-cycles) • ¬ Most single cycle execution• λ High code density• ¬ A vec<strong>to</strong>r interrupt controller is embedded• ¬ AHB-lite bus pro<strong>to</strong>col• ¬ Memory Protection UnitRegionAddressCS0AddressAddressCompareAddressScrambleAddressPeripheralHREADYHRESPControlAndStatusHREADYHRESPPeripheralC0AttributesPermissionCompareGateAttributesMemoryRegionPermissionKeyMemoryData OutEncryptionDecryptionData OutMemoryData InData InThe <strong>Power</strong> Architecture and <strong>Power</strong>.<strong>org</strong> word marks and the <strong>Power</strong> and <strong>Power</strong>.<strong>org</strong> logos and related marks are trademarks and service marks licensed by <strong>Power</strong>.<strong>org</strong>.
C*Core SoC <strong>Design</strong> <strong>Platform</strong>• IPs in CSOC000 <strong>Platform</strong>– CPU• CS00– Embedded FLASH/PROM Interface– NAND Flash Controller• Support MLC Nandflash: Samsung, Micron, ST• Support 72 bits ECC• Support boot from NAND flash– SD/MMC• Compatible with SD Host Controller 2.0,MMC3.31,4.0,4.1• Compatible with SDIO Card specification 1.0.1– USB2.0 Host/Slave• Support USB2.0 Device or Host• Support EHCI– SWP– RTC– 12 bit ADC• For Keypad scan, Touch Screen, Temperature detection– Interface• SPI/UART/7816/PWM/IIC/EPORT/CAN/1553B/PS2…– Support RSA,ECC,SHA-1,MD5,AES,3DES,SHA, and OSCA (SM1~SM4)– TRNGThe <strong>Power</strong> Architecture and <strong>Power</strong>.<strong>org</strong> word marks and the <strong>Power</strong> and <strong>Power</strong>.<strong>org</strong> logos and related marks are trademarks and service marks licensed by <strong>Power</strong>.<strong>org</strong>.
C*Core SoC <strong>Design</strong> <strong>Platform</strong>• A scalable platform <strong>to</strong> accelerate SOC design• A flexible, configurable and extendable framework <strong>to</strong> setup SOCprojects based on C*Core• Au<strong>to</strong>mate and ease the integration of new IP modules in<strong>to</strong> theplatform• Allows cus<strong>to</strong>mers <strong>to</strong> focus on designing their own high-valuedifferentiated IP modules• Maximize the reusability from RTL code <strong>to</strong> test benchThe <strong>Power</strong> Architecture and <strong>Power</strong>.<strong>org</strong> word marks and the <strong>Power</strong> and <strong>Power</strong>.<strong>org</strong> logos and related marks are trademarks and service marks licensed by <strong>Power</strong>.<strong>org</strong>.
C*Core SoC <strong>Design</strong> <strong>Platform</strong>• Support multiple projects design concurrently• Provide a simulation environment on <strong>to</strong>p of popular EDA <strong>to</strong>ols.• Allow <strong>to</strong> verify different IP modules at distinct levels of abstractions.• Optimized direc<strong>to</strong>ry structure <strong>to</strong> ease project management• Operating system support available ( Linux/ <strong>Win</strong>dows CE/ VxWorks/Android )The <strong>Power</strong> Architecture and <strong>Power</strong>.<strong>org</strong> word marks and the <strong>Power</strong> and <strong>Power</strong>.<strong>org</strong> logos and related marks are trademarks and service marks licensed by <strong>Power</strong>.<strong>org</strong>.
C*Core SoC <strong>Design</strong> <strong>Platform</strong>• A flexible environment for system-level verification including HW/SW co-verification.• Provide <strong>Power</strong>PC simula<strong>to</strong>r for hardware and software partition,and co-development• Include plenty of pre-verified IP modules ( RTL, test patterns,synthesis scripts, device driver, etc. )• Generate verification results au<strong>to</strong>matically• Various verification modesThe <strong>Power</strong> Architecture and <strong>Power</strong>.<strong>org</strong> word marks and the <strong>Power</strong> and <strong>Power</strong>.<strong>org</strong> logos and related marks are trademarks and service marks licensed by <strong>Power</strong>.<strong>org</strong>.
C*Core SoC <strong>Design</strong> <strong>Platform</strong> ( example )C9000Cus<strong>to</strong>mBlockSDRAMI/FUSB PHYUSB 2.0USB ISB 1.1Ethernet PHYEthernetPLB2AHBAMBA AHBVideo/AudioInterruptControllerAHB/APBBridgeAHB/PCIeBridgeDDR2/3 1394aSATAAMBA APBDDR PHYSATA PHYPCI ExpressWatchdogTimerGPIOUARTPCIe PHYOS BSP DRIVERC*Core(C9000)IPTotalSolutionWholeSystemThe <strong>Power</strong> Architecture and <strong>Power</strong>.<strong>org</strong> word marks and the <strong>Power</strong> and <strong>Power</strong>.<strong>org</strong> logos and related marks are trademarks and service marks licensed by <strong>Power</strong>.<strong>org</strong>.
DVB SoC Based on C*Core SoC <strong>Design</strong> <strong>Platform</strong>Single Chip DVB-Sreceiver SoC with highestintegration level in theworldGX6101MThe first <strong>to</strong>tally-domesticdirect broadcast satellitechipsetGX1121+GX3001The only domestic chipset thatsupports AVS and MPEG2synchronouslyGX3101+GX1501The <strong>Power</strong> Architecture and <strong>Power</strong>.<strong>org</strong> word marks and the <strong>Power</strong> and <strong>Power</strong>.<strong>org</strong> logos and related marks are trademarks and service marks licensed by <strong>Power</strong>.<strong>org</strong>.
Information Security SoC Based on C*Core SoC<strong>Design</strong> <strong>Platform</strong>LENOVO “(heng zhi)” (inSecurity PC)q Application: Security PCq CPU: C*Core C310KingTrust “ZDTX001”q Application: Encrypted communicationsand Authorization/Network Securityq CPU: C*Core CS320Aisino Chip “ACS3401”q Application: Information Securityq CPU: C*Core C340Huada Infosecq Application: Server Encryptionq CPU: C*Core C310The <strong>Power</strong> Architecture and <strong>Power</strong>.<strong>org</strong> word marks and the <strong>Power</strong> and <strong>Power</strong>.<strong>org</strong> logos and related marks are trademarks and service marks licensed by <strong>Power</strong>.<strong>org</strong>.
Consumer SoC based on C*Core SoC <strong>Design</strong> <strong>Platform</strong>Fujitsu NF46001 chipq Application: Master controller forprintersq CPU: C*Core CS310C*Core chips and solutions fortax machinesq Application: Tax machine, POSmachineq CPU: C*Core C310Master controller chips forShanghai Junqi USB drivesq Application: USB drivesq CPU: C*Core C306The <strong>Power</strong> Architecture and <strong>Power</strong>.<strong>org</strong> word marks and the <strong>Power</strong> and <strong>Power</strong>.<strong>org</strong> logos and related marks are trademarks and service marks licensed by <strong>Power</strong>.<strong>org</strong>.
Touch Panel Controller Based on C*Core SoC<strong>Design</strong> <strong>Platform</strong>Application: Touch Panel ControllerSoCFeatures:• CPU: C306• Supporting capacitive multi-<strong>to</strong>uchpanel with different sizes The <strong>Power</strong> Architecture and <strong>Power</strong>.<strong>org</strong> word marks and the <strong>Power</strong> and <strong>Power</strong>.<strong>org</strong> logos and related marks are trademarks and service marks licensed by <strong>Power</strong>.<strong>org</strong>.
3D Display Controller based on C*CORE SoC<strong>Design</strong> <strong>Platform</strong>Application: Naked eye 3D display SoCchips (cell phone) Features:• CPU: C410• Supporting naked eye 3Ddisplay, low cost The <strong>Power</strong> Architecture and <strong>Power</strong>.<strong>org</strong> word marks and the <strong>Power</strong> and <strong>Power</strong>.<strong>org</strong> logos and related marks are trademarks and service marks licensed by <strong>Power</strong>.<strong>org</strong>.
Summary• C*Core can provide a series of high performance CPUwhich are fully Compatible with <strong>Power</strong>PC• C*Core provide SoC design platform which can helpcus<strong>to</strong>mer <strong>to</strong> accelerate SoC design for differentapplications• C*Core scalable design platform help you <strong>to</strong> win!The <strong>Power</strong> Architecture and <strong>Power</strong>.<strong>org</strong> word marks and the <strong>Power</strong> and <strong>Power</strong>.<strong>org</strong> logos and related marks are trademarks and service marks licensed by <strong>Power</strong>.<strong>org</strong>.
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