Understanding Verilog Blocking and Nonblocking ... - Sutherland HDL

BlockingProcedural AssignmentsSutherlandH D L6➤ The = token represents a blocking procedural assignment➤ Evaluated and assigned in a single step➤ Execution flow within the procedure is blocked until theassignment is completed➤ Evaluations of concurrent statements in the same time stepare blocked until the assignment is completedThese examples will not work ⎯ Why not?//swap //swap bytes bytes in in word wordalways always @(posedge clk) clk)begin beginword[15:8] = word[ word[ 7:0]; 7:0];word[ word[ 7:0] 7:0] = word[15:8];end end//swap //swap bytes bytes in in word wordalways always @(posedge clk) clk)fork forkword[15:8] = word[ word[ 7:0]; 7:0];word[ word[ 7:0] 7:0] = word[15:8];join join

Non-BlockingProcedural AssignmentsSutherlandH D L7➤ The

ConcurrentProcedural Assignments10SutherlandH D LThe order of concurrent evaluation is indeterminate➤ Concurrent blocking assignments have unpredictable resultsalways @(posedge clk)#5 A = A + 1;always @(posedge clk)#5 B = A + 1;Unpredictable Result:(new value of B could be evaluated beforeor after A changes)➤ Concurrent non-blocking assignments have predictable resultsalways @(posedge clk)#5 A

Delayed AssignmentProcedural Assignments12SutherlandH D L➤ An intra-assignment assignment delay places the timing control after theassignment token➤ The right-hand hand side is evaluated before the delay➤ The left-hand side is assigned after the delayalways @(A)A is evaluated at the time it changes, butB = #5 A;is not assigned to B until after 5 time unitsalways @(negedge clk)Q

Intra-Assignment DelaysWith Repeat Loops13SutherlandH D L➤ An edge-sensitive intra-assignment assignment timing control permits aspecial use of the repeat loop➤ The edge sensitive time control may be repeated severaltimes before the delay is completed➤ Either the blocking or the non-blocking assignment may beusedalways @(IN)OUT OUT

Choosing theCorrect Procedural Assignment14SutherlandH D L➤ Which procedural assignment should be used to model acombinatorial logic buffer?always @(in)#5 out = in;always @(in)#5 out

TransitionPropagation Methods15SutherlandH D L➤ Hardware has two primary propagation delay methods:➤ Inertial delay models devices with finite switching speeds;input glitches do not propagate to the output10 20 30 40 50 6010 20 30 40 50 60Buffer with a 10 nanosecond propagation delay➤ Transport delay models devices with near infiniteswitching speeds; input glitches propagate to the output10 20 30 40 50 6010 20 30 40 50 60Buffer with a 10 nanosecond propagation delay

Combinational LogicProcedural Assignments16SutherlandH D L➤ How will these procedural assignments behave?in1020 30 40 50 6033 36 45Blocking,No delayalways @(in)o1 = in;o1zero delayNon-blocking,No delayalways @(in)o2

Sequential LogicProcedural Assignments17SutherlandH D L➤ How will these procedural assignments behave?➤ Sequential assignments➤ No delaysclkin1020 30 40 50 6035 53always @(posedge clk)beginy1 = in;y2 = y1;endalways @(posedge clk)beginy1

Sequential LogicProcedural Assignments18SutherlandH D L➤ How will these procedural assignments behave?➤ Sequential assignments➤ Delayed evaluationclkin1020 30 40 50 6035 53always @(posedge clk)begin#5 y1 = in;#5 y2 = y1;endalways @(posedge clk)begin#5 y1

Sequential LogicProcedural Assignments19SutherlandH D L➤ How will these procedural assignments behave?➤ Sequential assignments➤ Delayed assignmentclkin1020 30 40 50 6035 53always @(posedge clk)beginy1 = #5 in;y2 = #5 y1;endalways @(posedge clk)beginy1

Sequential LogicProcedural Assignments20SutherlandH D L➤ How will these procedural assignments behave?➤ Concurrent assignments➤ No delaysclkin1020 30 40 50 6035 53always @(posedge clk)y1 = in;always @(posedge clk)y2 = y1;?y1y2y1y2? ? ? ??? ??shift register with race conditionalways @(posedge clk)y1

Sequential LogicProcedural Assignments21SutherlandH D L➤ How will these procedural assignments behave?➤ Concurrent assignments➤ Delayed evaluationclkin1020 30 40 50 6035 53always @(posedge clk)#5 y1 = in;always @(posedge clk)#5 y2 = y1;#5#5?y1y2y1y2 ? ? ?shift register with race condition?????? ?always @(posedge clk)#5 y1

Sequential LogicProcedural Assignments22SutherlandH D L➤ How will these procedural assignments behave?➤ Concurrent assignments➤ Delayed assignmentclkin1020 30 40 50 6035 53always @(posedge clk)y1 = #5 in;always @(posedge clk)y2 = #5 y1;always @(posedge clk)y1

Rules of Thumb forProcedural Assignments23SutherlandH D L➤ Combinational Logic:➤ No delays: Use blocking assignments ( a = b; )➤ Inertial delays: Use delayed evaluation blockingassignments ( #5 a = b; )➤ Transport delays: Use delayed assignment non-blockingassignments ( a

An Exception to Non-blockingAssignments in Sequential Logic24SutherlandH D L➤ Do not use a non-blocking assignment if another statement inthe procedure requires the new value in the same time stepbegin#5 A

Exercise 3:Procedural Assignments25SutherlandH D L➤ Write a procedure for an adder (combinational logic) thatassigns C the sum of A plus B with a 7ns propagation delay.always @(A @(A or or B) B)#7 #7 C = A + B; B;➤ Write the procedure(s) for a 4-bit 4wide shift register (positiveedge triggered) of clock and has a 4ns propagation delay.always @(posedge clk) clk)always @(posedge clk) clk)beginy1 y1

Exercise 3 (continued):Procedural Assignments26SutherlandH D L➤ Write a Verilog procedure for a “black box” ALU pipeline thattakes 8 clock cycles to execute an instruction. The pipelinetriggers on the positive edge of clock. The “black box” isrepresented as call to a function named ALU with inputs A, Band OPCODE.How many Verilogstatements does ittake to model aneight stage pipeline?always @(posedge clk) clk)alu_out