A **Circuit** **Level** **Fault** **Model** **for** **Resistive** **Shorts** **of** **MOS** **Gate** **Oxide**Xiang Lu † , Zhuo Li † , Wangqi Qiu ‡ , D. M. H. Walker ‡ and Weiping Shi ††Dept. **of** Electrical EngineeringTexas A&M UniversityCollege Station, TX 77843-3124, USAwshi@ee.tamu.eduABSTRACTPrevious researchers in logic testing focused on shorts in**MOS** gate oxides that have zero-resistance. However,most shorts are resistive and may cause delay faults. Inthis paper, we propose a simple and realistic delay faultmodel **for** gate oxide shorts. A reasonably accuratemethod is proposed to compute delay change due toresistive shorts. We also enumerate all possible faultbehaviors and present the relationship between inputpatterns and output behaviors, which is useful in ATPG.1. INTRODUCTIONDelay test detects small manufacturing defects that do notcause functional failure but affect the speed **of** thecircuits. In this paper, we consider the fault model **of**resistive gate oxide shorts, which can be used **for** delaytest.Banerjee and Abraham first considered gate oxide shorts.They assumed the shorts are zero-resistance and modeledthe shorts as stuck-at faults [1]. Hawkins and Soden [2]presented data to show the short resistance is in the range**of** 100’s to 1000’s **of** ohms. Syrzycki [3] considereddifferent structures **of** gate oxide shorts and proposedlumped-element models. Gaitonde and Walker [4] studiedsome problems faced in mapping spot defects includinggate oxide shorts to changes in the nominal circuit. Haoand McCluskey [5] studied the logic and delay behavior**of** resistive shorts. Their circuit level fault model is shownin Figure 1, which covers the external behaviors **of** gateto-sourceshorts, gate-to-drains short and gate-to-channelshorts. Note that because the polysilicon gate is generallydoped with n type dopant, there is a diode in series withthe short resistor **for** P**MOS** transistors. Hao andMcCluskey also showed that faults caused by gate oxideshorts can be dependent on input signals **of** both the gatecontaining the fault and other gates [6]. And they foundthat Very Low Voltage testing would detect such patterndependent faults caused by resistive shorts [7]. In [8], weproposed a circuit level fault model **for** resistive shorts inthe interconnect. However, resistive shorts in **MOS** gatesare more complex in certain cases.**Model**ing gate oxide shorts as delay faults helps delay testto detect more shorts. Previous models lack in explicit‡ Dept. **of** Computer ScienceTexas A&M UniversityCollege Station, TX 77843-3112, USAwalker@cs.tamu.edurelationship between delay changes and resistive shorts.In this paper we propose a physically realistic andeconomical fault model **for** delay test. **Resistive** gateoxide shorts are modeled as delay faults as well as logicfaults according to the short resistance. We alsoenumerate all possible fault behaviors and present therelationship between input patterns and output behaviors.The fault model is reasonably accurate and easy toimplement **for** delay fault simulation in large industrialcircuits.gate-todrainshortgate-tosourceshortR bR bgate-tosourceshortgate-todrainshortN**MOS** transistor P**MOS** transistorFigure 1. **Gate**-to-source and gate-to-drain shorts **for**N**MOS** and P**MOS** transistors.2. FAULT MODELThe objective **of** the gate oxide short model is totrans**for**m the effect **of** the resistive short into a delay faultor a logic fault, and compute the delay change as afunction **of** short resistance R b .To analyze electrical behaviors **of** R b in the circuit level,consider the circuit in Figure 2. There are two cells: thedriving cell with output node A and the faulty cell withoutput node B. In the figure, R 1 and R 2 are interconnectparasitic resistance, C 1 and C 2 are lumped interconnectparasitic and gate input capacitance. In Figure 2 the defectis a gate-to-source short inside an N**MOS** transistor.**Circuit**s **for** other defects are similar, except that thefaulty transistor may be P**MOS** or the short may be gateto-drain.The faulty cell contains one faulty transistor, and the rest**of** transistors are good. In this paper, we only considerthe short at input transistors, i.e. transistors driven byexternal signals. **Shorts** at other transistors can beanalyzed similarly by partitioning the faulty cell to makethe faulty transistor driven by an external signal. ForR bR b

example, an AND cell can be partitioned into a NANDcell driving an inverter, in order to analyze the short atone **of** the inverter transistors.driving cellP**MOS**N**MOS**AR 1RN**MOS** 2R bC 1faulty cellP**MOS**faulty n-mosN**MOS**Figure 2. The circuit with an N**MOS** gate-to-drainshort. **Circuit**s with other shorts are similar.We assume there is only one single input transition on thefaulty cell. When a signal transition at the input **of** thedriving cell causes the transition at B, we consider thesum **of** the driving cell delay and the faulty cell delay.However, when the signal at A is static, and the transitionat B is caused by a transition at other input **of** the faultycell, we only consider the faulty cell delay. Here delay iscomputed at the 50% **of** V dd point on the signal wave**for**m,and denoted as d Rb . When there is no short, the drivingcell delay is denoted as D A , and the faulty cell delay isdenoted as D B . Both D A and D B can be computed by anycommercial tool, such as SPICE.2.1 N**MOS** gate-to-drain shortStatic analysisThe circuit in the static analysis is shown in Figure 3. R up1and R down1 are pull-up and pull-down resistance **of** thedriving cell respectively. R up2 represents the pull-upresistance in the faulty cell. The pull-down path inside thefaulty cell is divided into two parts from the faultytransistor, represented by resistors R down2 and R down3 . Thelinear resistance **of** the faulty transistor is included inR down2 .R up2BC 2When a pull-down path in the driving cell is **for**med, s 1 =“**of**f”, s 2 = “on”, s 3 = “on” and s 4 = “**of**f”. The voltage atnode A is derived asVR + R1 down1A,down= V . (1)ddR + R + R + R + Rdown11 b down3up2The voltage at node B, V B,down , can be derived similarly.Define the Bridge Threshold Resistance (BTR) R A,down ,such that when R b < R A,down , V A,down is larger than the logiclow threshold voltage V LL . Then according to (1),( V −V)( R + R )dd LL 1 down1R = − R − R . (2)A,downdown3up2VLLThere**for**e when R b < R A,down , V A,down > V LL , there is a logicfault at A. When R b > R A,down , there will be no logic faultat A, but there might be a delay fault.When a pull-up path in the driving cell is **for**med, similarvoltage expressions V A,up at node A, V B,up at node B andcorresponding BTRs can be derived.Transition analysisWe present transition analysis by two cases. In one case, asignal transition propagates through the driving cell to thefaulty cell. In the other case, a signal transition happensonly at the faulty cell while the signal at node A is static.For each case, we assume R b is large enough such thatthere is no logic fault when the circuit is static. We modelthe resistive short as a delay fault, and propose themethod to compute the delay change due to the short.Case 1Assume a falling signal transition happens at node A, andaccordingly a rising signal transition happens at node B.During the transition, the faulty N**MOS** transistor is cut**of**fand a pull-up path inside the faulty cell in **for**med. Ifthere is no R b present, C 1 is discharged only throughR down1 and C 2 is charged only through R up2 . With thepresent **of** R b , a current path through R b is **for**medbetween node A and B. Then C 1 is partially discharged toC 2 because the initial voltage at A is higher than that at B.At the same time, C 1 is also charged by the faulty cellthrough R b . The circuit in transition analysis is illustratedin Figure 4.s 3R 2R up1R down3s 1AR b ss 42R 1RR down2down1BV AR up2R 1R bR down3R 2 V BR down1C 1C 2Figure 3. The circuit under static analysis.Figure 4. With the present **of** R b , a current path is**for**med between node A and B.

Our delay model works as follows. Through analyzing thecircuit in Figure 4, we compute the driving cell delay d A,Rband the faulty cell delay d B,Rb . Considering both delays arefunctions **of** R b , we compute the ratio between the delaywith some certain value **of** R b and the delay with R b = ∞,then approximate d Rb asdA,RdbB,RbdR= DA+ DB. (3)bdA,Rdb =∞B,Rb=∞The computation **of** d A,Rb is as follows.First we introduce an effective resistance R A,eff to replacethe discharging path R b -R down3 -R 2 -C 2 . The value **of** R A,eff iscomputed by equalizing the average current **of** the twocircuits in Figure 5, during a certain time interval T d . Thevalue **of** T d is the time **for** the voltage **of** C 1 in the circuit**of** Figure 5(a), dropping from its initial voltage V 0 to 50%**of** the total dropping range. The equivalent currentmethod is also used to calculate effective capacitance in[9]. In this paper we use it to compute R A,eff .V 0 R b+R down3+R V2 0 R A,effC 1 C 2C 1(a) (b)Figure 5. R A,eff is computed by equalizing the averagecurrent in the two circuits.We getC2ln(2)RA , eff= ⋅⋅ ( Rb+ Rdown3+ R2) .C 2( C1C2)1+ C +2ln( )2C+ C1Second, because we replace path R b -R down3 -R 2 -C 2 withR A,eff , the circuit becomes a first order linear system andthe driving cell delay can be derived asdA,down A,upA, R bdf 1+ ln() ⋅ RA⋅VA,down− 0.5Vdd2V −V= C , (4)where d f1 is the intrinsic falling delay **of** the driving cell,R A =(R down1 +R 1 )//(R b +R down3 +R up2 )//R A,eff . The symbol “//”represents the parallel computation **of** two resistances.Note when R b is infinity, d A,Rb=∞ is the sum **of** intrinsicgate delay and gate load delay under the lumped C delaymodel.The computation **of** d B,Rb is similar. For the rising signaltransition at B, path C 1 -R b -R down3 -R 2 is a charging path.We insert a resistance R B,eff at A to equalize the chargingeffect **of** the path. The value **of** R B,eff is computed similarly.Here the value **of** T d is the time **for** the voltage **of** C 2 inthe circuit **of** Figure 6(a), rising to 50% **of** the total risingrange.1V 0 R b+R down3+R 2V 0R B,effC 1 C 2C 2(a) (b)Figure 6. R B,eff is computed by equalizing the averagecurrent in the two circuits.There**for**e, we getC1ln(2)RB , eff= ⋅⋅ ( Rb+ Rdown3+ R2) .C 2( C1C2)1+ C +2ln( )C + 2CThen the faulty cell delay is derived asd1B,down B,upB, R b⋅ dr2+ ln() ⋅ RB⋅VB,down− 0.5Vdd2V −V= α C , (5)where d r2 is the intrinsic rising delay **of** the faulty cell,α=(V dd – V B,up )/V dd is introduced to scale d r2 because theinitial voltage **for** the rising transition at B is not zero, andR B =(R down1 +R 1 +R B,eff +R b +R down3 )//R up2 +R 2 .Experiments are per**for**med on a circuit, which consists **of**an inverter as the driving cell, and an NAND gate as thefaulty cell. TSMC 180 nm 1.8V technology is used.Assume V LL = 0.7V, then Bridge Threshold Resistance(BTR) R A,down = 1284Ω according to our model. Results **of**delay ~ R b computed by our model and by SPICEsimulation are shown in Figure 7. Our model providesreasonably accurate approximation **of** the delay changewith present **of** R b . When R b < R A,down , there is a logic faulton node A and when R b ≥ R A,down , there is a decreasingdelay fault.Delay (ps)232119171513119R A,downlogic faultdecreasing delay fault0 5000 10000 15000 20000R b (ohm)2SPICEEstimatedFigure 7. Decreasing delay estimated and computed bySPICE with increasing values **of** R b .Case 2Consider an N**MOS** transistor T g , which is in series withthe faulty N**MOS** transistor T f . Assume there is a rising

signal driving T g , resulting in a falling transition at B. Thesignal at node A, which is driving T f , is static high.During the transition, a pull-down path through T f and T gis **for**med. The simplified circuit is shown in Figure 8,where R down3 represents the linear resistance **of** T f and theN**MOS** block connecting output **of** the faulty cell, andR down2 represents the linear resistance **of** the N**MOS** blockconnecting T f and Gnd.R up1AR down3BR 2C 2R b RR down21Figure 8. C 2 is discharging through the pull-down pathin the faulty cell.The final voltage at B is dependent on the value **of** R b ,and can be derived asVR= down2B,upVddRup1+ R1+ Rb+ R. (6)down2Then the faulty cell delay is computed asdV −V= C ,dd B,upB, R bdf 2+ ln() ⋅(Rdown2+ Rdown3+ R2) ⋅50% Vdd−VB,upwhere d f2 is the intrinsic rising delay **of** the faulty cell.Similarly, we approximate d Rb asdRbd=dB,RbB,Rb=∞⋅ D . (7)BExperiments results on the same circuit are shown inFigure 9. The BTR **for** V B,up is R B,up = 1798Ω. The figureshows that when R b < R B,up , there is a logic fault on nodeA and when R b ≥ R B,up , there is a increasing delay fault inthe faulty cell.Delay (ps)454035302520R B,upincreasing delay faultlogic faultSPICEEstimated0 5000 10000 15000 20000R b (ohm)Figure 9. Increasing delay estimated and computed bySPICE with increasing values **of** R b .22.2 N**MOS** gate-to-source shortIn the case **of** an N**MOS** gate-to-source short, it mayaffect the circuit behaviors in two ways. 1) The short actsas a resistor that connects A and Gnd, thus reducing thevoltage at A due to voltage division. The value **of** theresistor is R b +R down , where R down represents the linearresistance **of** the N**MOS** block between the faultytransistor and Gnd. Note that whether the current paththrough R b to Gnd is **for**med depends on the side inputs **of**the faulty cell. Then the short can be viewed as a resistivebridge between interconnect and GND, and modeledusing the method proposed in Li et al. [8]. 2) The shortconnects A and B through the faulty N**MOS** transistor,and currents flow through A to the faulty cell output, thenthough some N**MOS** transistors to Gnd. There**for**e thevoltage at B is affected and a functional fault possiblyhappens at B. A delay fault at B possibly happens and thedelay change can be derived similarly.2.3 P**MOS** gate-to-drain shortThe gate-to-drain short in a P**MOS** transistor can bemodeled as a bridge resistance in series with a diodebetween the interconnect and Vdd. The diode is always**for**ward-biased and is represented by a certain voltagedrop across the bridge. The behavior **of** the diode can beanalyzed similarly with the method in Hao andMcCluskey [3]. Due to the diode, currents can never flowthrough A to B.2.4 P**MOS** gate-to-source shortSimilar analysis to N**MOS** gate-to-drain shorts can beper**for**med, except **for** the voltage drop effect due to thediode. And when a pull-up path is **for**med in the drivingcell, currents cannot flow through A to B due to the diode.3. CONCLUSIONSIn this work, we propose a circuit level fault model **for**resistive gate oxide shorts in **MOS** transistors. Theresistive short is modeled as a logic fault when the shortresistance is less than the value **of** bridge thresholdresistance (BTR). Otherwise it is modeled as a delay fault.We derive expressions **of** BTR **for** all possible shortbehaviors. To detect a logic fault, the test pattern shouldbe selected to maximize BTR. With explicit expressions**of** BTR, it is possible to compare per**for**mance **of** differenttest patterns analytically. Previous methods, **for** examplethe stuck-at fault model [1] and the short resistivebehavior analysis in [5], are insufficient **for** that.For the case that the short provokes delay changes in thecircuit, we propose a fast yet reasonably accurate delayestimation method and provide closed **for**m delayfunctions in terms **of** the short resistance. In Table I, **for**each type **of** short, we list delay behaviors **for** differentinput signals. T f is the faulty N**MOS**/P**MOS** transistor and

T g is another N**MOS**/P**MOS** transistor. The rising/fallingsignal on T g or T f provokes a rising or a falling transitionat the output **of** the faulty cell. In the table, “T f | T g ” meansthe two transistors are in parallel, “T f ~ T g ” means the twotransistors are in series, “decrease” means decreasingdelay, “increase” means increasing delay, and “0” meansthere is no change in delay when the short is present. Thetable enumerates all input patterns that will causeincreasing delay (or decreasing delay) at the output B dueto the short defect. The amount **of** delay change is givenby such **for**mulae as (3) and (7). The table andcorresponding delay **for**mula can guide ATPG to find thebest test patterns that can maximize the detectability.Table I. Behaviors **for** each type **of** short underdifferent input signals.Shortnmosg-sshortnmosg-dshortpmosg-dshortpmosg-sshortInput **of**faultytransistor T fInput **of**othertransistorT gDelay changerising static increasefalling static decreasestatic rising 0(T f | T g ), increase(T f ~ T g )static falling 0(T f | T g ), decrease(T f ~ T g )rising static decreasefalling static decreasestaticrisingdecrease(T f | T g ),increase(T f ~ T g )static fallingincrease(T f | T g ),decrease(T f ~ T g )rising static decreasefalling static increasestatic rising decrease(T f | T g ),0(T f ~ T g )static falling increase (T f | T g ),0(T f ~ T g )rising static decreasefalling static increasestatic rising decrease(T f | T g ),0(T f ~ T g )static falling increase(T f | T g ),0(T f ~ T g )[4] D. Gaitonde and D. M. H. Walker, “**Circuit**-levelmodeling **of** spot defects,” DFT 1991, pp. 63-66.[5] H. Hao and E. J. McCluskey, “On the modeling andtesting **of** gate oxide shorts in C**MOS** logic gates,”DFT 1991, pp. 161-174.[6] H. Hao and E. J. McCluskey, “‘**Resistive** shorts’within C**MOS** gates,” ITC 1991, pp. 292-301.[7] H. Hao and E. J. McCluskey, “Very-low-voltagetesting **for** weak C**MOS** logic ICs,” ITC 1993, pp.275-284.[8] Z. Li, X. Lu, W. Qiu, W. Shi and H. Walker, "Acircuit level fault model **for** resistive opens andbridges", ACM Trans. on Design Automation **of**Electronic Systems, 8(4), 2003, pp. 546-559.[9] J. Qian, S. Pullela and L. Pillage, “**Model**ing the“Effective capacitance” **for** the RC interconnect **of**C**MOS** gates,” IEEE Trans. CAD, 13(12), 2001, pp.1526–1535.REFERENCES[1] P. Banerjee and J. Abraham, “Generating tests **for**physical failures in **MOS** logic circuits,” ITC 1983,pp. 554-559.[2] C. F. Hawkins and J. M. Soden, “Electricalcharacteristics and testing considerations **for** gateoxide shorts in C**MOS** ICs,” ITC 1985, pp. 544-555.[3] M. Syrzycki, “**Model**ing **of** gate oxide shorts in **MOS**transistors,” IEEE Trans. CAD, 8(3), 1989, pp. 193-202.