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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 59, NO. 7, JULY 2012 439Understanding the Basic Advantages of BulkFinFETs for Sub- and Near-Threshold LogicCircuits From Device MeasurementsF. Crupi, Member, IEEE, M. Alioto, Senior Member, IEEE, J. Franco, P. Magnone,M. Togo, N. Horiguchi, and G. Groeseneken, Fellow, IEEEAbstract—This study aims to understand the potential ofbulk FinFET technology from the perspective of sub- and nearthresholdlogic circuits down to 100-mV bias voltage. Measurementsare performed on bulk FinFETs with a channel length of60 nm, a fin height of 33 nm, and a fin width of only 14 nm andwith a high-k/metal-gate stack having an equivalent thickness ininversion of 1.6 nm. For comparison purposes, measurements arealso performed on bulk planar FETs with the same channel lengthand similar gate stack. FinFETs show a stronger dependence ofthe drain current on the gate voltage and a lower dependenceon the drain and body biases w.r.t. planar devices. After adjustingfor the different threshold voltages, FinFETs exhibit perfect balancebetween n- and p-FETs at any applied bias in the sub- andnear-threshold regimes. As a consequence, FinFET logic circuitshave significantly improved voltage scalability from the perspectiveof dc robustness and of performance/energy.Index Terms—Bulk FinFET, digital circuits, subthresholdCMOS, VLSI.I. INTRODUCTIONULTRALOW-POWER (ULP) operation of digital integratedcircuits has paved the way for many new applicationssuch as wireless sensor networks, biomedical andimplantable devices/networks, ambient intelligence, and wearablecomputing. From a circuit-level perspective, ULP operationis enabled by very aggressive voltage scaling belowthe threshold voltage –. Operation in subthreshold posesmany challenges at various levels of abstraction. In general,ultralow-voltage operation determines a degradation in the dcrobustness and strong performance penalty and provides noenergy gain below a certain voltage. These issues set the limitsto the practical voltages that can be employed in ULP systems.Fig. 1. Cross-sectional TEM image of the bulk FinFET with fin height of33 nm and fin width of 14 nm.Better scalability can be obtained by using devices that aremore amenable for aggressive voltage scaling. Among them,the bulk FinFET has been widely shown to be a particularlygood candidate  and has been announced by Intel to bethe replacement of bulk CMOS at 22 nm and below. Sincethe technology used in ULP applications is set by mainstreamapplications, it is necessary to understand the impact and thepotential advantages that can be brought by FinFETs in thiscontext.In this work, various aspects of ULP CMOS logic circuits operatingin subthreshold and near threshold are analyzed throughwafer measurements of devices. To this purpose, we adoptand extend a methodology recently proposed to perform anearly assessment of a newly developed technology –. Tohave a fair comparison with CMOS technology, planar devicesimplemented with the same length and similar gate stack as theFinFETs are also comparatively analyzed. The main focus is onthe voltage scalability of FinFET w.r.t. planar devices in termsof dc robustness, performance, and energy.Manuscript received January 28, 2012; revised March 30, 2012; acceptedMay 11, 2012. Date of publication June 19, 2012; date of current versionJuly 13, 2012. This brief was recommended by Associate Editor T. Zhang.F. Crupi is with the Dipartimento di Elettronica, Informatica e Sistemistica,Università della Calabria, 87036 Rende, Italy (e-mail: email@example.com).M. Alioto is with the Dipartimento di Ingegneria dell’Informazione, Universitàdi Siena, 53100 Siena, Italy.J. Franco and G. Groeseneken are with the Interuniversity MicroelectronicsCenter (imec), 3001 Leuven, Belgium, and also with the Department ofElectrical Engineering (ESAT), Katholieke Universiteit Leuven, 3001 Leuven,Belgium.P. Magnone is with the Advanced Research Center on Electronic Systemsfor Information and Communication Technologies E. De Castro (ARCES),Università di Bologna, 40125 Bologna, Italy.M. Togo and N. Horiguchi are with the Interuniversity MicroelectronicsCenter (imec), 3001 Leuven, Belgium.Digital Object Identifier 10.1109/TCSII.2012.2200171II. FINFET VERSUS PLANAR DEVICESDevices were fabricated at imec using 300-mm (100) Siwafers. A cross-sectional transmission electron microscopy(TEM) image showing the triple-gate FinFET architecture ofthe device is shown in Fig. 1. The gate length (L) of FinFETsunder investigation is 60 nm, the fin height (H FIN ) is 33 nm,and the fin width (W FIN ) is 14 nm. Since the drain currentflows on the top and on the sidewalls of the fin and since thedevices under investigation consisted of five fingers in parallel(N FIN =5), the total effective width is computed as W =N FIN × (2H FIN + W FIN ) = 400 nm. The gate stack of theFinFET devices consisted of 5-nm physical vapor depositionTiN metal electrode on 2.1-nm HfSiO high-k dielectric in1549-7747/$31.00 © 2012 IEEE
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