Online proceedings - EDA Publishing Association

24-26 September 2008, Rome, ItalyTABLE IISUMMARY OF THE PARAMETER VALUES VARIATIONS OBTAINED AFTER ACCELERATED AGEING TESTS (V: VALUE, %: PERCENTAGE CHANGE).After stressBeforeParam-TSTTCTstress HVD TST hot TST coldeters∆T = 150 0 C ∆T = 225 0 C I ds = 0mA I ds = 3mA I ds = 6mAV % V % V % V % V % V % V % V %G m (10 -6 S)V gs =4V 1.27 0.92 27.5 1 21.2 0.85 33 0.8 37 0.73 42.5 1.24 2.7 0.74 41.7 0.71 44R ds_on (Ω)V gs =10V 1.14 1.20 5.28 1.19 4.38 1.21 6.2 1.23 7.89 1.27 11.4 1.16 1.7 1.25 9 1.30 14C gd (pF)V gd =-1.5V 1.90 1.31 31 1.52 20 1.09 42 1.00 47 0.97 48 1.85 2.6 1.02 46 0.96 49C rss (pF)V ds =0V 2.72 2.60 4.76 2.65 3 2.56 6.2 2.50 8.42 2.46 10 2.71 1 2.51 8 2.43 11V ds =28V0.57 0.50 12.2 0.52 8.77 0.48 15 0.46 19.2 0.44 23 0.57 0 0.46 19.2 0.43 24S 12 (dB)Frq=2 GHz -37.8 -36.5 3.4 -36.8 2.5 -36.2 4.2 -36 5 -33.9 11 -37.8 0 -35.5 6 -32.8 13S 21 (dB)Frq=2 GHz -6.1 -7.1 17 -6.9 14 -7.7 27 -7.9 30.2 -8.1 33.4 -6.1 1 -7.9 31 -8.3 36The detail of the lateral electric field distribution of theactive silicon layer in channel and drift regions is shown inFig. 6, using physical simulation software (Silvaco-Atlas,2D). This strong electric field favoured the generation ofcharge states at the silicon-oxide interface [13], [19]. Sincethe LDMOS is used in these conditions, where drain isbiased with high voltage simultaneously with thermalexcitation due to thermal cycling and shock (making easy thecurrent flow), these two factors translated the correlation ofthermal and electrical stresses [4].The hot carrier degradation effect is closely related withcurrent density and with the total number of free electrons atthe silicon-oxide interface, where most of the electrons areconcentrated deep inside the drift region [13], [18], [19].Hence, the electron concentration contours across theactive silicon layer can be observed from Fig. 7. It could benoticed that the concentration is very high at the gate level,on the right (drain side) in such a way that it provides asignificant increase of the surface current density at the gateedge. Consequently many electrons are accelerated to highvelocities by this high electric field peak. They becomehighly energized and should be accelerated away from theirnormal directional flow.Lateral Electric Field [V/cm]4,0x10 53,5x10 53,0x10 52,5x10 52,0x10 51,5x10 51,0x10 55,0x10 4GATEN - LDD region0,02,0 2,2 2,4 2,6 2,8 3,0 3,2 3,4 3,6 3,8 4,0X position [µm]Fig. 6. Lateral electric field distribution in N-LDMOS structure,with V ds =40V and V gs =3.5V bias0,00,1maxN-LDDIn other words, the drain-source voltage increases theelectric field below the gate towards the trench LDD regionand near the oxide layer, therefore enhancing the trappingprocess. So the degradation rate is accelerated [13], [20],[21]. This means that the tracking of these parametersenables to consider the hot carrier injection as dominantdegradation phenomenon in spite of the power efficiencyimprovement. To reduce the possibility of electrons betrapped at the oxide-silicon interface, the current lines mustbe moved away and the electric field must be decreased inthis zone in order to improve the device reliability, byoptimising the fabrication process and the device structure orlayout [8], [22].Y position [µm]0,20,30,40,5min0 1 2 3 4 5 6 7X position [µm]Fig. 7. Electron concentration distribution of N-LDMOS,with V ds =40V and V gs =3.5V bias©EDA Publishing/THERMINIC 2008 126ISBN: 978-2-35500-008-9