Online proceedings - EDA Publishing Association

24-26 September 2008, Rome, ItalyFPGA Power Model for Minimizingthe Thermal DissipationÁbel Vámos, Márta RenczBudapest University of Technology and Economics, Department of Electron DevicesH-1111 Budapest, Goldmann György tér 3, Hungary, Phone: (+36-1) 463-2702, Fax: (+36-1) 463-2973e-mail: vamos@eet.bme.hu, rencz@eet.bme.huAbstract—In the field of application specific ICs the FPGAbecame more and more important. When such a system is underconstruction the designer has very few information about thefinal dissipation of the circuit. The solution should be a powermodel which can give prediction about the final dissipation ofthe particular functionality of the FPGA device. In this papermethods are described for power modeling and power-awaredesigning.I. INTRODUCTIONHE Field Programmable Gate Array (FPGA) devicesTbecame popular among digital designers. Even if theproduct planned to be released with an ASIC in theprototyping phase FPGAs are used to implement the design.Advancements in process technologies, FPGA architectures,and CAD tools are allowing increasingly larger and fastersystems to be implemented on FPGAs.As designs get larger and add more system functionsimplemented on FPGAs, and as the advanced silicon processtechnology moves into smaller geometries, powerconsumption is became the most important problem forFPGA vendors and designers. When designing a printedcircuit board (PCB), the power consumed by a devicedetermines not only the power supply, but also the requiredcooling system. Therefore, obtaining an accurate estimate ofpower consumption is essential to design a system’s powersupplies, voltage regulators, and cooling.With the higher reachable frequency the power estimationand the thermal dissipation are also growing. The powerconsumption is a problem for the held hand, battery basedequipments, but the wired equipments have the problem ofthe thermal dissipation. If a backbone network center is takenas an example the possibility of cooling is limited, as theclimate system is designed for the area of the room. With thenewest technology the dissipated heat on the same area willgrow, the concern will be more frequent.This paper discusses the main problems and methods ofpredicting power consumption in FPGAs. In the paper animprovement is proposed for achieving lower powerdissipation in the design. The discussed problems concern thefollowing themes: getting accurate signal activities, staticpower modeling, and dynamic power modeling. Accuratepower estimation relies on two important factors: signalactivities and power models. Power models define the powercharacteristics of the device. This has to be provided by thesilicon vendor, in this case from the FPGA vendor. The signalactivities define the behavioral characteristics of each signalin the design. The designer must provide accurate signalactivities to obtain the best possible estimate of overall powerconsumption. In the currently used FPGA power estimationtools use the following sources to provide information onsignal activity [1]:• Simulation results,• User-entered node, entity, and clock assignments,• User-entered default toggle rate assignment.II. POWER DISSIPATION IN FPGASThere are two types of power dissipation in integratedcircuits: static and dynamic. Static power is dissipated whencurrent leaks between the various terminals of a transistor,while dynamic power is dissipated when individual circuitnodes toggle.Although static power is increasing relative to dynamicpower for newer process technologies, dynamic powerremains the dominant source of power dissipation in FPGAs.Power estimation CAD tools are provided by the FPGAvendors. These tools predicting only from a general togglingrate value for the whole circuit.This paper introduces a technique that reduces dynamicpower in FPGAs by actively minimizing the number ofunnecessary transitions called glitches. The techniqueinvolves adding programmable delay elements within thelogic blocks of an FPGA to align the arrival times of earlyarrivingsignals to the inputs of the lookup tables (LUTs) andto filter out glitches generated by earlier circuitry.III. POWER MODELSA. Static Power ModelsStatic power is the power consumed by a device due toleakage currents when in stable state, with no activity orswitching in the circuit. The amount of leakage current varieswith die size, junction temperature, and process variation.Static power can be modeled using a set of exponentialequations that vary with junction temperature (T j ):BTjP = Ae Cstatic+©EDA Publishing/THERMINIC 2008 148ISBN: 978-2-35500-008-9