24-26 September 2008, Rome, ItalyWhen the temperature dependence of the thermalconductivity k ( x, y,z,t)is ignored, the above equation (1)can instead of equation (3)( )2k x,y,z,t ∇T( x,y,z,t) + p( x,y,z,t) = 0(3)Consider the discretization of the substrate in Fig. 1, eachthermal tile in the tile-based floorplan represents a smallvolume of silicon, Δ = δxδyδz, where δ x , δ y , and δ z arerespectively the unit width, depth, and height of the thermaltile. By applying the finite difference approximation for thespatial derivatives in the equation (3) at the thermal tiles i asTT 1 T T 2 Tx1TiTx2Tiy i y i Tz1TiTz2 Ti+ + + + + +∂/ x kAx∂/ x kAx∂/ x kAy∂/ x kAy∂/ x kAz∂/ x kAzp( x,y,z,t) = 0(4)or equivalently( Tx1−Ti) gi,x1+ ( Tx2−Ti) gi,x2+ ( Ty1−Ti) gi,y1+ ( Ty2−Ti) gi,y2+( Tz1−Ti) gi,z1+ ( Tz2−Ti) gi,z2+ p( x,y,z,t) = 0(5),where T i is the temperature at the thermal tile i , k is thethermal conductivity of unit silicon, = δyδz, = δxδz,A zgA x A ygi, x1gi,x2= kAxi, z1= gi,z2= kAz/ δ .= δyδz, Δ = δxδyδz, = / δx,= g kA / δy, and gzi, y1i,y2=yyxAmbient TemperatureFig. 1 Tile-based thermal modelIn the tile-based thermal model, a set of tiles are consideredfor thermal analysis. Each thermal tile models a small volumeof the die stack and is connected to adjacent tiles in x , y ,and z directions by thermal resistors. By using a discreteapproximation of the steady state thermal equation,2− k ∇ T ( x,y,z,t) = p( x,y,z,t), the results in the matrixequation, G tile ⋅ Ttile= Ptile, can be used to estimate thetemperatures of all the thermal tiles, where G tile is a thermalconductivity matrix, T tile is a temperature vector and P tile isa power vector. Traditionally, the solution of this matrixequation can be obtained by inverting the matrixT = G−1 ⋅ P in O n ) time and calculating the matrixtiletiletile( 3 tilemultiplication Ttile= R ⋅ Ptilein O ( ntile2 ) time, where n tile istotal amount of tiles. In conclusion, the computationalcomplexity for tile-based thermal model is the cube of totaltiles.B. Power Vector CalculationAt firstly, the tile-based thermal model partitions thefloorplan into some basic unit tiles and the volume for everyztile is defined by the designer. The original floorplan includestwo regions: cell region and space region. When the regionincluding logical gates or functional circuits is named cellregion, the remaining region are called space region. Afterpartitioning, the floorplan can be made up of many tiles. Allof the tiles can be classified into three types such as cell tile,space tile, and mixed tile.1. Cell tile denotes the partitioning tile only contains oneor more than one logical gate or functional circuit. Thetotal power is the summation of every logical gate orfunctional circuit power inside the tile.CTPower = ∑ cr _ PD × cr _ volume _ tile (6)ijj,where CTPower i is the total power for the cell tile i ,cr j _ PD denotes the power density for the logicalgate or functional circuit j and cr j _ volume _ tileiisthe volume for the logical gate or functional circuit jinside the cell tile i .2. Space tile denotes the tile only includes space regionand the total power is always zero.STPower = 0(7)3. Mixed tile is a special type in the tile-based thermalmodel. Because the partitioning tile does not clearlyhave cell region or space region, it can mix two types.The total power for mixed tile sums up the powers oflogical gate or functional circuit inside the mixed tile.MTPower = ∑ cr _ PD×cr _ volume _ tile (8)kll,where MTPower k is the total power for the mixed tilek , cr l _ PD denotes the power density for the logicalgate or functional circuit l and cr l _ volume _ tilekisthe volume for the logical gate or functional circuit linside the mixed tile k .According to above definitions and equations, total powerfor every tile is calculated. All of the total power valuesfinally makes up the power vector P .C. Adjacent Relationship and Thermal ConductivityCalculationIn tile-based thermal model, the adjacent relation betweenevery tile and ambient temperature can be simply got. In Fig.2, a tile has six sides (Front, Back, Left, Right, Top, and Down)and every side of a tile only be contacted with one side of theother tile or ambient temperature. Hence, the adjacent relationis defined fully-contact adjacency. According to the positionof every tile in the tile-based floorplan, there are threepossible adjacent relation types. (1) Type I: In Fig. 2 (a), thedark tile is surrounded by eight tiles but only four tiles arecontacted. Therefore the six adjacent sides contain four tilesin F, B, L, and R directions and two ambient temperatures in Tand D directions. (2) Type II: When the dark tile is in theboundary of tile-based floorplan, it contacts with three tilesand three ambient temperatures as shown in Fig. 2 (b). (3)Type III: The four corners in tile-based floorplan arecategorized into Type III in the Fig. 2 (c) and the dark tilecontacts two tiles and four ambient temperatures. Injlt ileik©<strong>EDA</strong> <strong>Publishing</strong>/THERMINIC 2008 59ISBN: 978-2-35500-008-9
conclusion, every tile is contacted with at most four other tilesand at least two ambient temperatures; moreover, the totalamount of the contact sides is always equal to six.LFTDBR(a) Type I (b) Type II (c) Type IIIFig. 2 Adjacent relation for tile-based thermal modelUsing adjacent relation between every tile, the thermalconductivity for every thermal block can be derived. Thebasic thermal conductivity equation asAG = k(9)LW / m°C , A is the,where k is the thermal conductivity ( )2contact area ( m ) and L is the distance between two heatsource (m).In the tile-based thermal model, the thermal conductivityfor every side of a tile only has two kinds. One is tile to tileand the other is tile to ambient temperature as shown in Fig. 3.In tile to tile, the distance L is from one tile center to theother tile center and the contact area A is one side area of atile. The main difference from the two kinds is the distancecalculation. The distance L of tile to ambient temperature isfrom the center of a tile to the tile boundary. When thethermal conductivity of six sides for a tile is completelycalculated, the summation of thermal conductivities of sixsides is the real thermal conductivity for a tile asAtileAtileAtileAtileg tilei = k F + k B + k L + k R +LiFLiBLiLLiR(10)AtileAtilekT+ k DLiTLiD,where g tilei denotes the thermal conductivity for tile i , k F ,k B , k L , k R , k T , and k D are the thermal conductivities forsix directions, and L iF , L iB , L iL , L iR , L iT , and L iD arethe distance from tile i to six-directions. The contact area isthe same hence only uses A to denote.ALtileALAmbientTemperature24-26 September 2008, Rome, Italyremaining tiles are mixed tiles. The total power for every tileis respectively calculated using equations (6), (7), and (8).Therefore, power vector P is obtained. According thet ileadjacent relation types, T7~T9, T12~14, T17~19 are Type I,and T6, T10, T11, T15, T16, and T20 are Type II. The fourcorners T1, T5, T21, and T25 are Type III. Then the thermalconductivity for every tile can be calculated according toequation (10) and the thermal conductivity matrix G tile is got.Finally, the temperature vector T tile for every tile is derived.R1R2(a) Original FloorplanR3T21 T22 T23 T24 T25T16 T17 T18 T9 T20T11 T12 T13 T14 T15T6 T7 T8 T9 T10T1 T2 T3 T4 T5(b) Tile-Based FloorplanFig. 4 Tile-based floorplanIII. PROBLEM FORMULATIONIt is well known that feasible space region in a givenfloorplan can be applied to not only introduces the bufferinsertion to speed up the interconnect delay [6] but alsoarranges necessary decoupling capacitance to maintain thesignal integrity and leakage reduction [7]. In general, thehighest block temperature in a floorplan is defined as thefloorplan temperature. In addition to the requirement ofperformance and signal integrity, the redistribution of feasiblespace is also applied to reduce the floorplan temperature [8].For a block-level floorplans: Given a LB-compactfloorplan including the functional blocks (B1, B2,…, Bn) andfloorplan region. The space region between functional blockscan be partitioned into rectangular space blocks (W1, W2,…,Wm). Hence, any block-level floorplan shown as Fig. 5 can berepresented by a set of functional blocks (B1~B10) and spaceblocks (W1~W8). The problem is to insert and redistribute thespace blocks in the floorplan region such that the finalfloorplan temperature is minimized. Our purpose is tocalculate temperature for every functional block and displaythe temperature difference between all functional blocks.B8W6 W7 W8B10B9(a) Tile to tile (b) Tile to ambient temperatureFig. 3 Adjacent relation for tile-based thermal modelFinally, the power vector P t ileand thermal conductivitymatrix G tile are obtained, P t ileand G tile are substituted intoTtile= Gtile−1 ⋅ Ptile, temperature vector T tile for every tile isderived.For example, the Fig. 4(a) is the original input floorplanincluding three circuit regions (R1, R2, and R3) and theremaining region is space region. After partitioning, thefloorplan has twenty-five tiles from T1 to T25 as drawn in Fig.3 (b). According to the classified tile types, T1~T10, T16, andT21 are functional tiles, T24 and T25 are space tile and theB4B1W1W5B6W4B5W2B2Fig. 5 Block-level floorplanB3B7W3©<strong>EDA</strong> <strong>Publishing</strong>/THERMINIC 2008 60ISBN: 978-2-35500-008-9
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