Online proceedings - EDA Publishing Association

8000 micronsVisible:- Silicon substrate (yellow), 500 um thick- Top metal (green), 4 um thick- Bump Bonds (red), 40 um thick- HBT devices: C-B junctions (dark blue), 0.5 um thickHeat Sources: HBT CB-junctionsILD = Inter Layer Dielectric (SiO2) removed for viewingFigure 6. Full chip 3D model of IC1.The next step is to generate a 3D computational mesh forthe thermal solver, which in our case is based on the finitevolumenumerical method. For computational efficiency, the3D mesh should be nonuniform, refined only locally toresolve particular small features of the IC/model, but be ascoarse as possible in other areas. Our tool generates thebinary tree (“bin-tree”) type of mesh. Our first attempt togenerate such a mesh for a full-chip model of IC1, as shownin Figure 6, produced a very big mesh – about 1.7 millioncells – too large to solve on single PC. We found that themain reason for that was very fine meshing around nonrectangularfeatures, such as spiral inductors and trapezoidalpads, see Figure 7.Bond PadHBT C-BjunctionsSpiralinductor2300 microns24-26 September 2008, Rome, ItalyAfter having removed all spirals and small triangles, ourIC1 full-chip mesh was 1.1 million cells - still not feasible tosolve on a single PC. So, additional coarsening steps had tobe done, but without loosing the main thermal properties ofthe IC. As indicated before, the bump bond structure iscritical for the overall thermal characteristics on the full-chipscale. So, we focused our effort on the bond structure model,and the next coarsening steps included:• remove & replace the thin layers and small layoutfeatures containing fine metallic structures, alreadyrepresented by “k eff -layers” (see Figure 3);• replace the entire multi-layer bump bond structure by“keff-Bond”.The above steps were successfully applied, and allowed todecrease the size of the 3D mesh just for one bump bondfrom 2,000 cells in previous mesh (the coarsest possible) to40 cells in the new mesh. This is illustrated in Figure 8.keff_1keff_2TopMetalk_eff 3D Thermal Model of entire Bond Pad Mesh ~ 2,000 cellsIC Si SubstrateGoldBump Bondk = 317 W/K.m“keff-Bond” Mesh: 40 cellsIC Si Substrate“keff-Bond”k eff = 30.7 W/K.mFigure 8. Replacing the entire multi-layer Bump Bond structure (withseveral keff-blocks) by one “keff-Bond”. The 3D mesh for one bond isreduced from 2000 cells to 40 cells.With the coarsening approach described above, using the“k eff -Bond” structures, we built another 3D thermal modeland 3D mesh for the full IC1 chip. That coarser model,however, was still able to resolve a single transistor’s C-Bjunction (0.5 μm voxels were used), which ultimatelyproduced a full-chip 3D bin-tree mesh containing about196K cells - easy to solve on a PC. Two views of that meshare presented in Figure 9.Figure 7. IC1 Full Chip 3D Mesh – zoom in.On the other hand, such layout elements like spiralinductors have very little effect on the thermalcharacteristics, especially on the full-chip scale. We haveverified this by running additional test 3D thermalsimulations with the spiral inductors removed. Thetemperature results were not affected.Therefore, to enable generation of a reasonably sized 3Dmesh for the entire chip, we decided to do the following:• try to remove the layout elements that are not importantfor thermal results but generate a lot of fine mesh cells,• or, if some elements are important for thermal results,try to replace them by “effective thermal conductivity”(k eff ) blocks of simpler shape and/or bigger size.a) top view of the 3D mesh (about half of the entire IC1 is shown here).b) side view of the 3D mesh (fragment of IC1)Figure 9. The full-chip-scale mesh with “keff-Bonds”. This is a binary tree(bin-tree) mesh type, containing ~196K cells.©EDA Publishing/THERMINIC 2008 67ISBN: 978-2-35500-008-9