Online proceedings - EDA Publishing Association

24-26 September 2008, Rome, ItalyLogical Effort Model Extension with Temperature andVoltage VariationsChun-Hui Wu, Shun-Hua Lin, and Herming ChiuehSystem-on-Chip Design LaboratoryDepartment of Communications EngineeringNational Chiao Tung University, Hsinchu, 30010, Taiwanchwu@soclab.org, shlin@soclab.org, and chiueh@ieee.orgAbstract- The method of “Logical Effort Delay Model” allowsdesigners to quickly estimate delay time and optimize logicpaths. But the previous variances of logical effort models do notmention how to handle process, voltage, and temperature (PVT)variations appropriately, which may induce a seriousmisestimate. According to simulation results, delay timeincreases 21% while temperature increasing from 0°C to 125°C,and increases 2X while supply voltage decreasing from 1V to0.5V in 90nm process. Thus a simple linear extended logicaleffort g, 1/g=(m t t+b t )V DD +C, supporting for temperature t andsupply voltage V DD variations is presented. The proposed modelenables designers to estimate the logic path delay and tooptimize an N-stage logic network under different temperatureand supply voltage conditions. After validation, the accuracy ofthis new extended logical effort model can achieve about 90%.I. INTRODUCTIONIn the integrated circuits design, performance estimationand circuit optimization are two of the most important issues.The method of “Logical Effort Delay Model” allowsdesigners to quickly estimate and optimize single paths bymodeling equivalently delay time. This simplehand-calculated method has the advantage of reducing thedesign cycle time efficiently. In 1999, Sutherland, Sproull,and Harris introduced the theory of logical effort delay model[1]. The method of logical effort is founded on a simple modelof the delay through a single CMOS logic gate. According tothis simple model, the delay of a logic gate is defined asd abs = κR(C out + C p ) = τ(f + p) = τ(gh + p) (1)where d abs is the absolute delay, κ is a constant, R is thepull-up or pull-down resistance, C out and C p are the load andparasitic capacitance, τ is the basic delay unit, f, g, h, and p arethe stage effort, logical effort, electrical effort or fanout, andparasitic delay. The definitions of these parameters areRCt intCRtCoutptτ = κRinvCinv, g = , h= , and p= (2)R C C R Cinv inv in inv invwhere R inv and C inv are resistance and input capacitance of aninverter template, R t , C int and C pt are the resistance, inputcapacitance and parasitic capacitance of different logic gatetemplates.In addition to estimate the delay, logical effort is also usedto optimize an N-stage logic path.CoutG = gi, B = bi, H = , F = GBHC∏ ∏(3)where b i is the branching effort, and G, B, H and F are the pathlogical effort, path branching effort, path electrical effort andpath effort. The minimum path delay will be performed whenthe stage effort and the input capacitance of each gate areˆ 1/ Ni outif ghi iF , Cin.iingC= = = (4)fˆBased on above simple equations, designers can easilymanage the logic paths arrangement and obtain the optimizedpath delay.Because of the simplicity and clarity of logical effort model,many studies have been presented to improve the accuracy oflogical effort model to adapt to different design conditions.The effects of a linear input transition time and wiring RCdelay is introduced in [2] and the simulated value of g and p in0.18um process also been shown. A modified logical effortmodel, which accounts for the behavior of series connectedMOSFET structure, switching input transition time, andinternodal charges, is presented in [3]. Reference [4]introduces an extension of the logical effort model thatconsiders the I/O coupling capacitance and the input rampeffect.However, the modified logical effort models do notmention how to handle process, voltage, and temperature(PVT) variations appropriately, which may induce a seriousmisestimate. Moreover, the functional blocks on a chip willnot keep performance coherence at the same target frequencydue to temperature difference, and circuit delay will becomeworse when temperature rising [5]. As shown in Fig. 1 andFig. 2, delay time increases 21% while temperature increasingfrom 0°C to 125°C, and increases 2X while supply voltagedecreasing from 1V to 0.5V in 90nm process. Thus we hopeto extend the simple model and take temperature and supplyvoltage into account. Furthermore, each functional block on achip can be optimized under different PVT conditionsthrough the proposed model.©EDA Publishing/THERMINIC 2008 85ISBN: 978-2-35500-008-9