Online proceedings - EDA Publishing Association

24-26 September 2008, Rome, ItalyDelay (ns)90nm Process, Supply Voltage = 1V2.72.52.32.11.9-75 -25 25 75 125Tem peratur e (C)Fig. 1. Delay of 101 stages ring oscillator with different temperatures.90nm Process, Temperature = 25CDelay (ns)7654320.4 0.5 0.6 0.7 0.8 0.9 1 1.1Supply Voltage ( V)and supply voltage conditions.Because of the effect of velocity saturation, the saturationcurrent model is expressed as I d =KW(V gs -V t ), where K is thedrive ability factor, W is the transistor width, and V t is thethreshold voltage [7]. In this equation, K and V t aretemperature-dependent. In order to perform a simpleextended logical effort model, we try to express K and V t assimple linear functions of temperature t and supply voltageV DD . Fig. 5 and Fig. 6 describe the temperature and supplyvoltage effects on K and V t .Based on Fig. 5, we can observe that K is close to a linearfunction of temperature t with different V DD . Thus K isassumed as the equation K=mt+b, where m is the slope and bis the intercept. According to the simulation results as shownin Fig. 7, b can be rewritten as an approximate equationFig. 2. Delay of 101 stages ring oscillator with different supply voltages.II.LOGICAL EFFORT MODEL EXTENSIONA. Effects of Temperature and Supply Voltage VariationsIn (1), τ and h are constant in each process, but g and p willbe impacted by temperature and voltage variations since theyare functions of effective resistance and capacitance. In orderto understand how temperature and voltage variations affectthe logical effort model, we establish a test circuit to imitate areal logic path [6]. Based on (1), the equation of delay can berewritten asd abs = τ(gh + p) = τgh + τp. (5)The curves of delay time d abs vs. fanout h can be plottedwith the test circuit under different temperature and supplyvoltage conditions. The slope of the curve is τg, and then wedefine the value of g is 1 at typical values of temperature andsupply voltage. τ is a constant in each process. Thus thedistinct values of logical effort g with different temperaturesand supply voltages can be obtained. Practically it describestemperature and voltage effects on RC delay of the logic gate.Based on simulation results, we can plot the 3-D graphs ofthe value of g and 1/g versus temperature and supply voltageas Fig. 3 and Fig. 4. According to these graphs, the linearregression will be utilized to perform curve fitting and derivethe new extended model as a simple linear format from 1/gbecause the shape of the surface in Fig. 4 is flatter.B. Derivation of Logical Effort Model ExtensionBased on the definition of g, the equation of g can berewritten asRtCint kVDDCing = kReffCinRinvC= = (6)invIdwhere R eff and C in are effective resistance and inputcapacitance of the gate, V DD is the supply voltage, and I d isdrain current. As shown in Table I, according to simulationresults, k is close to a constant under different temperatureFig. 3. The values of g with different temperatures and supply voltages.Fig. 4. The values of 1/g with different temperatures and supply voltages.TABLE ISIMULATED VALUES OF k WITH DIFFERENT TEMPERATURES AND VOLTAGESk=g*Id/(Vdd*Cin)(10^12)1V 0.9V 0.8V 0.7V 0.6V 0.5V-50°C 0.1859 0.1845 0.1778 0.1786 0.1826 0.2031-25°C 0.1850 0.1844 0.1787 0.1791 0.1831 0.20090°C 0.1847 0.1840 0.1790 0.1794 0.1834 0.198825°C 0.1843 0.1826 0.1791 0.1792 0.1830 0.196350°C 0.1840 0.1807 0.1790 0.1785 0.1819 0.193575°C 0.1831 0.1793 0.1791 0.1774 0.1804 0.1906100°C 0.1815 0.1767 0.1781 0.1760 0.1784 0.1877125°C 0.1793 0.1742 0.1770 0.1729 0.1763 0.1850©EDA Publishing/THERMINIC 2008 86ISBN: 978-2-35500-008-9