Online proceedings - EDA Publishing Association

24-26 September 2008, Rome, ItalyK (A/Vm)6005004003002001001V 0.9V 0.8V0.7V 0.6V 0.5V0-75 -50 -25 0 25 50 7 5 100 125 15 0Temperature (C)Fig. 5. The value of K with different temperatures and supply voltages.Vt (V)0.30.250.20.150.10.0501V 0.9V 0.8V0.7V 0.6V 0.5V-75 -50 -25 0 25 50 75 100 125 150Temperature (C)Fig. 6. The value of V t with different temperatures and supply voltages.-0.5-0.6-0.7-0.8-0.9m (Slope)0.4 0.6 0.8 1Supply Voltage (V)b (Intercept)6005004003002000.4 0.9Supply Voltage (V)Fig. 7. The value of m and b with different supply voltages.b=m KV V DD +K 0 , where m KV and K 0 are constant. Since thevalue of t is in a range of -50~125, the effect of the value of mis much smaller than b, thus we replace m with the averagevalue m Kt .K=m Kt t+m KV V DD +K 0 (7)V t is a linear function of temperature t and the effect ofsupply voltage V DD on V t is small. In order to simplify theextended logical effort model, the effect of V DD on V t isignored and V t is expressed as the equationV t =m Vt t+V t0 (8)where m Vt and V t0 are constant.According to the simulation results as shown in Table II,we observed that the effects of temperature and voltage on C inare much smaller than on I d . In order to simplify the extendedlogical effort model, the value of C in is assumed as a constantin the proposed model.Based on previous analysis results, the equation of logicaleffort can be rewritten as (9) and (10).kVDDCin kVDDCing = =. (9)I KW ( V −V)d DD t1 KW( VDD −Vt ) KV (DD−Vt )Vt= = const ⋅ = const ⋅K(1 − ) (10)g kV C V VDD in DD DDwhere const=W/kC in is a constant. After replacing K and V t in(10) with (7) and (8), the formula can be simplified by TaylorTABLE IISIMULATED VALUES OF C in WITH DIFFERENT TEMPERATURES AND SUPPLYVOLTAGESCin (fF) 1V 0.9V 0.8V 0.7V 0.6V 0.5V-50°C 0.7886 0.7895 0.7898 0.7887 0.7840 0.7701-25°C 0.7897 0.7904 0.7903 0.7888 0.7836 0.77030°C 0.7925 0.7929 0.7925 0.7905 0.7850 0.772125°C 0.7970 0.7971 0.7963 0.7939 0.7881 0.775650°C 0.8028 0.8026 0.8015 0.7987 0.7927 0.780675°C 0.8094 0.8089 0.8076 0.8045 0.7984 0.7866100°C 0.8163 0.8157 0.8142 0.8109 0.8047 0.7933125°C 0.8234 0.8226 0.8209 0.8175 0.8113 0.8002expansion (at V DD =a) and linear regression:1A() t V B()tg = ⋅ + (11)DDconst ⋅mKt ⋅mVt 2 const( mKt ⋅ Vt 0+ K0⋅mVt)At () = ⋅ t + ⋅t2 2aaK0⋅Vt0+ const( mKV+ )2a−2⋅const ⋅mKt⋅mVt2Bt () = ⋅ta⎛2( m ⋅ V + K ⋅m) ⎞+ ⎜ − ⋅ − ⎟⋅⎝a ⎠⎛2K0⋅Vt0 ⎞+ const ⎜−mKV⋅ Vt0+ K0− ⎟⎝a ⎠Kt t0 0 Vtconst mKt mKV mVtt(12)(13)For presenting a simple linear extended logical effortmodel and after evaluating A(t) and B(t), the final extendedmodel of g is presented as the following formula:1/g = (m t t+b t )V DD +C (14)where t is the temperature, V DD is the supply voltage,const( mKt ⋅ Vt 0+ K0⋅mVt )K0⋅Vt0mtt + bt = ⋅ t + const( m )2 KV+2aa(15)and C is the average of the value of B(t). The values of m t , b t ,and C are constant in each process.The proposed extended logical effort model enablesdesigners to estimate the logic path delay and to optimize anN-stage logic network under different temperature and supplyvoltage conditions with minimum effort by (1), (3), (4) and(14). It can avoid a serious misestimate induced bytemperature and supply voltage variations.Additionally, because the parasitic delay p will bedominated by the style and area of layout and wire routing, wedon’t discuss these issues here.©EDA Publishing/THERMINIC 2008 87ISBN: 978-2-35500-008-9