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Electrical Characteristics of InAlAs/InGaAs/InAlAs ... - JSTS

Electrical Characteristics of InAlAs/InGaAs/InAlAs ... - JSTS

146H.T. KIM et al :

146H.T. KIM et al : ELECTRICAL CHARACTERISTICS OF INALAS/INGAAS/INALAS PSEUDOMORPHIC HIGH ELECTRON…layers, modulating the optical power (P opt ) from dark toP opt =2.51mW(+4dbm).II. FABRICATION AND CURRENT-VOLTAGECHARACTERISTICS OF PHEMTS UNDER DARKThe MBE-grown epitaxial structure of thecharacterized double heterostructure InAlAs/InGaAs/InAlAs PHEMTs on InP wafer with a V-shaped gateS1µmn + InGaAs:20nm1µm 1µmi In 0.52Al 0.48As:40nmN-In 0.52Al 0.48As(3x10 18 cm -3 :Si):20nmi In 0.52Al 0.48As:10nmi In 0.65Ga 0.35As :15nmSuperlattice InAlAs/InGaAs buffer:30prdGi In 0.53Ga 0.47As:40nmi-In 0.52Al 0.48As:300nmS.I. InP SubstrateD(3x10 18 cm -3 ):SiFig. 1. Epitaxial structure and schematic energy band diagramof probed InAlAs/InGaAs PHEMTs with W/L=200µm/1µmand L gs =L gd =1µm.Drain Current, I D[mA]605040302010V GS+0.8V+0.4V0.0V-0.4V-0.8V00.0 0.2 0.4 0.6 0.8 1.0 1.2Drain-to-Source Voltage, V DS[V](a) I D -V DS characteristics under darkDrain and Gate Currents, I Dand I G[A]1x10 -11x10 -21x10 -3Drain Current1x10 -41x10 -5V DS=0.2, 0.6, 0.7,0.8, 1.0,1.2V1x10 -61x10 -71x10 -81x10 -9Gate CurrentSourceGate-2.0 -1.5 -1.0 -0.5 0.0 0.5DrainR SxR GxR DxD GSR SiD GDR ch,PHEMTR ch,sFETGate-to-Source Voltage, V GS[V](b) I G -V DS characteristics under dark (with an equivalent circuitas an insert)Gate Voltage, V GS,pand V GS,IIon[V]-0.5-0.6-0.7-0.8-0.9-1.0V GS,PV GS,II-1.10.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3Drain Voltage, V DS[V]R DiV GS,PV GS,IIV GS,P=-0.43-0.31V DSV GS,II=-0.62-0.31V DS(c) Peak-(V GS,P ) and onset-gate voltages (V GS,II ) of theimpact ionization under dark.Fig. 2. Drain and gate current-voltage characteristics ofPHEMTs under dark.(W=2x100µm, L g =1.0µm) is shown in Fig. 1. Wetchemical etching and conventional optical lithographyprocesses were employed for the fabrication of PHEMTs.Between the undoped In 0.52 Al 0.48 As barrier layers,lattice-matched In 0.52 Ga 0.47 As (E g ~0.62eV) andpseudomorphic In 0.65 Ga 0.35 As (E g ~0.75eV) layers weresandwiched as a high mobility conducting channel in thePHEMT. We also note that the InGaAs channel layers

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.3, NO. 3, SEPTEMBER, 2003 147are photoresponsive for the band-to-band excess carriergeneration to the optical source with the sub-bandgapphoton energy (hν=0.799eV) while InP and InAlAslayers are transparent to it. We may also expect that thereis a spatial (real space) transfer of carriers from thechannel layer to adjacent layers overcoming the banddiscontinuities in the conduction and valence bands(∆E C ~0.5eV, ∆E V ~0.2eV in In 0.52 Al 0.48 As/In 0.65 Ga 0.35 Asheterostructure).The current-voltage characteristics of PHEMTswithout optical excitation (P opt =0mW) were probed atroom temperature (T=300K), and, the drain and gatecurrents (I D and I G ) are shown in Fig. 2(a) and (b) as afunction of the drain and gate voltages (V DS and V GS ) :(I D -V DS curve; V GS =-1.2~+0.8V and I G -V GS curve;V DS =0.1~1.1V). The saturated drain current (I DSS ), themaximum transconductance (g m,max ), and the thresholdvoltage (V T ) under dark condition (P opt =0 mW) weremeasured to be I DSS =150 mA/mm, g m,max =220 mS/mm (atV DS =1.2V), and V T ≅ -0.95V, respectively. As typicallyobserved in short-channel InP-based PHEMTs, a channellength modulation was also observed. Typical values ofthe common-source current gain cut-off frequency (f T )and maximum oscillation frequency (f max ), from deviceson the same wafer, were neasured to be f T =30GHz andf max =48GHz, respectively.Under low drain voltages, the reverse gate current inthe I G -V GS curve is mainly caused by the thermionicfieldemission and the field-assisted tunneling in additionto the thermal generation of carriers in the depletionregion under the gate [1-5]. We note that the negativebell-shaped gate leakage is observed in the I G -V GScharacteristics under high drain voltage over V DS >0.7V.This is known to be caused predominantly by thesuccessive collection of generated holes due to theimpact ionization by hot channel electrons under a highelectric field [1-2].From the I 1/2 D -V GS characteristics, it seems that twoPHEMTs, with two different threshold voltages andtransconductances, are connected in parallel. Maincontribution of the PHEMT (region-A), with a highconductivity InGaAs channel layer, has V T ~-0.95V whilea poor performance satellite FET (sFET: region-B),probably due to a parasitic conduction layer as aMESFET with an InAlAs doped layer, has V Ts ~-2.0Vunder dark condition. Equivalent circuit of the deviceunder test is shown in Fig. 2(b) as an insert.The gate current can be grouped into 3 distinct regions.In the region-A, the gate current is expected to begoverned by the minority carrier diffusion current (I G,S ),thermal generation current (I G,GnR ) in the depletionregion, and a possible contribution of the tunnelingcurrent (I G,Tunnel ) as well as the impact ionization (I G,II )under high drain bias. Under low drain bias, maincontribution of the gate current in this region-A is due toI G,S and I G,GnR . However, it is predominantly governed bythe impact ionization (I G,II ) under high drain bias aboveV DS >0.7V which is expected to depend strongly on thedevice strure. In the region-B, on the other hand, thereverse gate leakage current is expected to be governedby the thermionic field emission (I G,TFE ) component inaddition to the thermally generated current (I G,GnR ) in theextended depletion with elevated reverse gate bias. In theregion-C with a positive gate bias, the main contributionof the gate current is expected to be the thermionicemission (I G,TE ) due to enhanced injection of carriersover the built-in energy barrier and, therefore, a quasiexponentialincrease of the gate current is observed. Inthe region-B, the parasitic transistor sFET governs thedrain leakage current while the PHEMT with InGaAs asa channel layer is the dominant current-controlling pathin this structure. The onset of the impact ionization canbe explained by the onset/turn-on of the PHEMTovercoming the satellite FET as a parasitic leakage pathwith a poor channel conductivity.The peak gate voltage (V GS,P at which the reverse gatecurrent shows a peak value) and the onset-gate voltageof the impact ionization (V GS,II at which the reverse gatecurrent starts to abruptly increase probably due to theimpact ionization under high drain voltage) aresummarized in Fig. 2(c) as a function of V DS under darkcondition. They show V,=−0.43− 0.31VandVGS , II=−0.62 − 0.31Vas a linear function of VDSDS with thesame V DS -dependence (slope=-0.31 V -1 ). This is mainlydue to the accelerated electric field and increasedprobability of impact ionization resulting a parallel shiftof them with V DS . Peak gate voltage V GS,P shows aparallel shift from the V GS,II because the impactionization and resulting the gate current depend on boththe number of available carriers and the strength of theaccelerating electric field for high kinetic energy in theconducting InGaAs channel layer.GS PDS

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