3 years ago

Introduction to Cadence - UPC

Introduction to Cadence - UPC

2.5.6 Saving the

2.5.6 Saving the results:The simulation results (not the waveforms drawn) can be stored to compare them with further simulations. Thisis accomplished by using the following command, from the simulation environment window menu:Results -> Save…It is recommended to add a comment to easily identify the saved results. These results will always be associatedto the schematic cell that has been simulated.16 Introduction to schematic capture and simulation using Cadence DFW-II

3. Analog behavioural modeling and simulationIn the previous section you have completed a transitor level design of an operation amplifier and verified itsperformance through simulation. In this cell has to be used in a more complex design it is useful to have asimpler model of the cell that would simulate faster than the transitor level circuit. One possible option is tocreate a behavioral view of the same cell using VerilogA language to describe the function of the circuitcontaining only the necessary details for system-level analysis.3.1 AHDL model generationFrom the simulation results of the previous section, it has been shown that the operation amplifier has a low-passfrequency response with two poles and one zero. Since there is a dominant pole the behaviour of the circuit canbe modeled with a simple first order RC circuit and a gain function.Follow the next steps to create the cell view and write the VerilogA model:3.1.1 AHDL view creation CIW menu: File->New->Cellview… Library Name: ANALOGTUT Cell Name: op_amp View Name: veriloga Tool: VerilogA Editor OKThere is an alternative way to do this, from the schematic view of the circuit. If we use this option, the inputand output names will be added automatically to the heading of the VerilogA model:Virtuoso Scematic menú: (editando la vista schematic del circuito que queremos modelar) Design->Create Cellview->From Cellview… Library Name: ANALOGTUT Cell Name: op_amp From View Name: schematic To View Name: veriloga Tool: VerilogA Editor OKAfter clicking OK a text editor window will open (emacs) 1 .3.1.2 VerilogA model creationUse the text editor to enter the following model. You cannot just paste the code, you must write it or modify thetemplate (you can also create a file file with this code and by ftp put it in the ../op_amp/verlioga/folder… the problem is that when you will create the cell the code will have incorrect characters that you willhave to fix):// VerilogA for ANALOGTUT, op_amp, veriloga`include “constants.h”`include “discipline.h”// Pin declarationsmodule op_amp(OUT, INN, INP, VDD, VSS);1 It a text editor does not open, this is probably because the EDITOR variable in your .csh configuration file points to vi, nanoor other editors that are opened in the console window.17

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