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Introduction to Cadence - UPC

Introduction to Cadence - UPC

There are Views that

There are Views that contain the information necessary to simulate the cells. Behavioral descriptions can besimulated directly, but other cells need a particular view for each different simulator. These simulation views arenormally found only in the lowest level of the design hierarchy (devices, passives, sources, etc). A particular caseis the digital cells from standard cell libraries, which have a symbol View that is also used for simulationpurposes.The following table shows typical vies for a digital and a analog basic cell:Digital basic cellabstractabstract_mlvscmos_schlayoutmspssymbolAnalog basic celladsauCdsauLvseldoeldoDhsimhsimDhspiceSlayoutspectrespectreSsymbolFrom the point of view of the simulation process (specifically, from the netlister tool point of view) there arethree categories of views:Stopping views:These views are the primitive views necessary for the simulators. They contain the properties necessary to informto the netlist generation process how the information must be written in a specific component. These viewsusually have the same name that the simulator (Spectre, SpectreS, hspiceS, eldo, etc). As mentioned before, somebehavioral descriptions using, for example, Verilog, VHDL or VerilogA languages are also stop views. Forexample, the ahdl view is a stop view that will be simulated with the SpectreAHDL simulator, a subprogram ofthe SPICE-like simulator Spectre.Switching views:These views are intermediate levels of the design hierarchy and they will always contain instances to cells withother structural or stop views. The commonest structural view is schematic, that can contain basic elements likeresistors, capacitors or transistors, that will have a stop view (for example spectre) or other structural elementswith views of type schematic.The cmos.sch view is special a schematic view that appears in the digital cells to allow the transistor levelsimulation coexist with the logic simulation of the same cell.The views of type extracted are also structural, since they contain the devices and passive components extractedfrom layout of the circuit.Non simulation viewsSome views are not appropriate for simulation, like the physical design layout View. These views themselvescontain no useful information for any simulator but by applying some post-processing (the extraction ofparasitics and devices) they can be transformed into simulation views (for example, the extracted view).4 Introduction to schematic capture and simulation using Cadence DFW-II

1.5 View lists for simulation and analysisThe same design can be simulated in many different ways, if the proper views are available. For this reason it isnecessary to set up a process that specifies what view to use in each of the cases. The netlister selects theappropriate description of the circuit according to the type of simulation and the available view for each cell inthe hierarchy. This process is controlled by means of two view lists:Switch view list: this list defines the views that will be considered in the netlisting process. The order isimportant because it defines the order in which the available view for each cell will be analyzed.Stop view list: this list contains the stopping views according to the simulations that are selected to be used in theanalysis.The procedure of netlist generation is the following: the highest level of the hierarchy is analyzed first, lookingonly to the views that appear in the Switch view list in the order in which they are defined for the cells that itcontains. If a view for a cell is found then it is checked whether this view is in the Stop view list or not. If it isnot, the netlister descends a level into the hierarchy for that cell and iterates the process. If the view list analyzedfor a particular cell is found in the Stop view list, the information for the simulation is extracted from that viewand added to the netlist, stopping the hierarchical analysis for that cell. The process is completed when all thecells with stopping views have been visited and netlisted.Some examples of view lists set-ups for different types of simulations:a) Transistor level simulation (for pure analog designs):Switch view list: spectre schematicStop view list: spectreb) Transistor level simulation (for pure digital designs):Switch view list: spectre cmos_sch schematicStop view list: spectreIn this design, each cell having only a schematic view will be hierarchical traversed until the instanceswith a spectre View are found. Digital cells have a schematic view named cmos_sch instead ofschematic.c) Mixed signal simulation: analog section at transitor level / digital section at logic level:Switch view list: spectre symbol schematicStop view list: spectre symbolComparing with the previous case, the symbol View is placed first before schematic View. In this way, digitalcells will be first analyzed using its symbol View, which is also a simulation view (it is in the Stop view list).The relevance of the order used in the Switch view list can be explained using the following example.The basic analog components (resistors, transitory, etc.) have both a symbol View (used to instantiate thecomponents in the schematic view of the higher level) and a spectre View (used for simulation). Since the viewspectre is found first in the Switch view list and it is also found in the Stop view list, that will be the view used fornetlisting, and the symbol View will not be analyzed. Digital cells have no spectre view and their schematic viewis named cmos.schs. Therefore, the symbol View plays the same roll for digital basic cells that the spectre Viewfor basic analog components. This behavior also allows classifying the two sections of the design, since they willbe simulated using different simulators. All the spectre Views collected by the netlister will be assigned to theanalog partition and simulated by the SPICE-like simulator Spectre. All the symbol views of the digital cellscollected by the netlister will be assigned to the digital partition and simulated using Verilog or VHDL5

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