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Prediction and Comparison of High-Performance On ... - IEEE Xplore

Prediction and Comparison of High-Performance On ... - IEEE Xplore


ZHANG et al.: PREDICTION AND COMPARISON OF HIGH-PERFORMANCE ON-CHIP GLOBAL INTERCONNECTION 1159proportional to . Similar to the delay modeling shownabove, linear models are built by combining energy consumedon wire and gate together, shown in the third row of Table IV.For T-line schemes, we consider the power dissipation onthe wire and transceiver individually. The power consumed onT-lines is basically proportional to if assuming wire inputimpedance remains constant across technologies. Transceiverdynamic power is linearly proportional to , where isthe clock frequency and represents the total gate capacitanceof the transceiver. Combining these two factors togetherwith the assumption that cycle time and gate capacitancescale by the same rate as . Linear models based on the analysisare shown in Table IV. As shown in (4), compared withRC wires, if item is dominant in the total normalized energyexpression, T-lines will consume less energy as technologyscales since shrinks more rapidly than does.For energy modeling, the largest errors in R-RC/P-RC modelingcome from the same sources as discussed in previous subsection.Errors in the modeling of T-lines may relate to the neglectof wire input impedance variations across different technologies.As a result, the maximum and average percent errors for RCwires are less than 34% and 12%, respectively, whereas forT-line schemes, those values become 27% and 13%.3) Throughput: The normalized throughput (or throughputdensity) is defined aswhich is adopted to compare the amount of data can be transmittedfor a given cross area in a given time interval.From (2) and assuming that wire pitch also scales down asFO4 delay , it is observed that, for an R-RC structureRegarding a P-RC structure, normalized throughput can be derivedfrom the normalized delay expression. The flip-flop delayshould account for the item in the denominator of normalizedthroughput expression. The general throughput model forRC wires is summarized in the third row of Table IV.Unlike the RC-dominated structures, the bit rate of T-lineschemes is usually limited by the bandwidth of transceivers (exceptfor UT-TL, which is determined by the wire itself). As aresult, assuming the transceiver bandwidth is inversely proportionalto , the bit rate of T-TL/UE-TL/PE-TL structures is inverselyproportional to . For UT-TL, the bit rate is constant astechnology scales, but is approximately inversely proportionalto wire length . Therefore, a general model of bit rate of T-linescan be represented by(5)(6)(7)Bit Rate (8)where , are fitting coefficients. Considering wire pitch,for single-ended T-lines, wire pitch does not change with technologyand wire length. However, for differential T-lines, largerwire pitch is required as technology scales and wire becomeslonger. An approximate relation is shown below based on simplemodeling of wire resistance considering dc and ac componentsseparately, 8 Wire Pitch (9)where , are fitting coefficients. In deriving this equation,we neglect the minor change of supply voltage as technologyscales, and assume the most important frequency componentof T-line skin effect for each technology is also proportionalto . Combining (8) and (9), we derive the throughputmodels for each T-line scheme in Table IV.For most transceiver-limited T-line structures, even whenconsidering the increasing wire pitch as technology scales, thethroughput density will still exceed that of an R-RC structuredue to the rapid improvement of transceiver bandwidth.The proposed model may have a larger error for T-TL schemeat the most advanced technology node (22 nm) as wire lengthincreases ( 7 mm) because the bandwidth of the overall structurebecomes wire-limited and does not improve as technologyscales.For throughput models, maximum and average errors of RCwires are 18% and 9%, respectively. For T-lines, fitting errorsbecome larger, which are 32% for maximum scenario and 11%for average scenario.4) Area: Chip area consumed by different interconnect structurescomprises two parts: wire area and circuit area. Wire areais the wire pitch multiplied by the total wire length . The pitchscaling trend has been discussed in the previous section. Circuitarea will reduce quadratically as technology scales, approximatelyproportionally to . Based on the analysis in previoussubsections, the area model for each interconnection scheme isshown in the forth row of Table IV.Typically, wire area dominates total chip area. As a result,RC wires consume less area compared to T-line structures, andRC wire area decreases more quickly as technology scales comparedto T-line structures. The area of differential T-lines actuallyincreases as technology scales due to increasing wire pitch.Area model of RC wires may show a substantial error dueto the reasons cited in the subsection of delay modeling. Themaximum and average errors are 34% and 11% for RC wires.For T-line schemes, due to the dominance of wire area, fittingerrors are smaller compared with RC wires. The maximum andaverage errors are 13% and 4%, respectively.III. DESIGN METHODOLOGYIn this section, methodologies to design and optimize the sixglobal interconnection structures are discussed. As previouslymentioned, for the R-RC scheme, we adopt the optimizationframework in [4], which is based on analytical formulae and numericalexperiments to study the performance metrics under differentdesign goals across multiple technology nodes. In termsof the P-RC structure, we develop a simple MATLAB flow to optimizethe pipeline depth based on the lowest energy/bandwidthratio, with the assumption that R-RC wire between flip-flops are8 In (9), the p L value comes from the dc component of wire resistance,whereas L= p item comes from the ac component of wire resistance, causedby the skin effect.

1160 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 7, JULY 2011scheme (T-TL), termination resistance also needs to be optimizedfor achieving high throughput. The optimization routinefor this kind of scheme is comprised of two phases, namely determiningthe optimal clock rate and choosing the optimal variablesin terms of the given objective. Finally, signal integrity isstudied by SPICE simulation and the framework outputs the optimaldesign variables and corresponding performance metrics.Fig. 7. Design framework for on-chip global T-line structures(UT-TL/T-TL/UE-TL/PE-TL).optimized and the maximum pipeline depth is given. A detailedflow description is omitted here for the sake of brevity. For moreinformation regarding performance analysis of ideal pipelinedrepeated RC wires (without maximum pipelining depth limit),the basis of our pipelined RC wire flow, please refer to theAppendix A.This section focuses on the design of on-chip T-line schemes.Here, we propose a general framework by modeling on-chipT-line and transceiver circuitry separately and utilizing wellbehavedoptimization routines to generate the optimal designfor given design specification, as illustrated in Fig. 7. We willintroduce the application of this design framework on the singleendedT-line schemes (including UT-TL/T-TL) and differentialT-line schemes (including UE-TL/PE-TL), respectively, in thefollowing.A. Single-Ended T-Line SchemesThe methodology to optimize single-ended T-line structuresis proposed and discussed in [12]. Here, we summarize thismethodology according to the general design framework shownin Fig. 7.Corresponding to the proposed framework, on-chip wire ismodeled using the frequency dependent tabular model generatedby the field solver, and the characteristic of the transceivercircuit is obtained by SPICE simulation. Also, we use SPICE toevaluate the performance metrics of whole structure. Since wiredimensions are well defined, design variables of interest relateonly to the transceiver circuit (the inverter chain), including thefirst inverter size and number of stages . For the terminatedB. Differential T-Line SchemesFor differential T-line schemes, the adopted methodology isbased on the constrained nonlinear programming formulation[8] and sequential quadratic programming (SQP) approach [23].We discuss the details of this flow corresponding to the frameworkin Fig. 7 as follows.The flow begins with modeling of wires and transceiversusing different means. For on-chip wires, 2-Dtabularmodel is still utilized. For the transceiver circuit,though, we adopt a closed-form equation-based model, whichis generated by fitting SPICE simulation data. 9 To evaluate theperformance metrics of the whole structure, we combine themodels of wire and transceiver together, and then utilize theapproach in [24] to estimate the wire-end eye-opening. Theoptimization routine for differential schemes initially tries tofind the smallest wire dimension that satisfies the eye-openingconstraint by using binary search (which generates the datain Table III), and then calls the SQP subroutine to optimizethe design variables for the given design objective. The designvariables include driver impedance , passive equalizerparameters , (for PE-TL structure), and terminationresistance . The key element in formulating the differentialschemes is the eye-opening constraint. In this work, we choosethe method used in [8] to consider this constraint by addingan exponential item to the cost function. After optimization,we check the signal integrity and finally output the systemperformance metrics.IV. PREDICTION AND COMPARISON OFPERFORMANCE METRICSApplying the design methodologies discussed in Section III,we perform the experiments in this section to study the performancemetrics of our six different global interconnect structuresunder the min-d design objective across technology nodes, from90 nm down to 22 nm.A. Experimental SettingsFor parameter extraction of on-chip lossy T-lines, we use the2-D field solver CZ2D of the EIP tool suite from IBM [25]to build T-line structures shown in Fig. 6, and extract the frequency-dependenttabular model for SPICE simulation. For circuitdesign and modeling, we adopt a predictive transistor model[14], which is a Synopsys level3 MOSFET model with the parameterstuned following the ITRS roadmap.9 The details of these models can be referred to [8]. In this work, we adopt thesame closed-form equations but recalculate the coefficients based on the newerreceiver circuit design generated. As shown in [8], these equation-based modelscan achieve less than 2% and 5% relative error for the delay and power fitting,respectively.

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