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Peek 2070L Operating Manual - Quality Traffic Systems

Peek 2070L Operating Manual - Quality Traffic Systems

Section 6 — Theory of

Section 6 — Theory of Operation38 • Model 2070L Operating Manual

Detailed Systems DescriptionEngine BoardThe operational flow of the 2070L CPU Engine Board is shown on the page 5, inFigure 20. The operation of the Engine board can essentially be divided up into foursubsystems:• The MC68360 Microcontroller• Memory• Communications• Reset ManagementMicrocontroller — The 68360 microcontroller functions as the brain of the 2070L,running the core application, managing data collection and storage in memory, directingcommunications, monitoring complex states, and interacting with the user (via thedisplay module). The micro takes the state of LINESYNC from the motherboard (asgenerated by the power supply) and of DKEY_PRESENT from the CPU Host board. Itsets the state of the CPU_RESET and CPU_ACTIVE settings, which go out to themotherboard. An important function of the microcontroller is to manage the master databus, shown at the bottom of the illustration. Using the passive Bus Control LineMapping, which allows data to be sent to devices with different data bus widths and pinassignments, the microcontroller directs where data goes across the data bus tomemory and the DUART.The micro also has two lines of serial control communications going out to other itemson the engine board. The Serial Peripheral Interface (SPI) channel is used to interactwith the two SPI devices on the host board, namely the DataKey and the EEPROM. SPIdoes not get passed across the host board to the 2070L motherboard. The other serialcontrol channel available to the microcontroller is the I²C bus (aka ‘I2C’). This channel isused to connect the microcontroller to the RTC (Real-time Clock)/SRAM Supervisor chipand to the on-board EEPROM.Memory — Aside from the small EEPROM memory chip on the I²C bus, there are threemain memory locations on the Engine board: ‘Boot and Apps’ Flash, DRAM and SRAM.Boot and Apps Flash is where the operating system and the microcontroller’s programand boot block is located. It also functions as a flash drive for data storage. Boot andApps Flash memory is non-volatile; it does not require power to retain its contents.DRAM on the other hand, is a much faster dynamic memory storage location that doesrequire power to retain its memory. DRAM functions as the working memory for themicroprocessor. This is where the applications on the micro actually reside while theyare running. The SRAM is a pseudo non-volatile memory location with a protectioncontrol that prevents unintentional writes during power fluctuations. SRAM is used tostore non-volatile global variables for the running applications, as well as a secondarynon-volatile RAM drive.The SRAM is power backed-up from the RTC/SRAM supervisor, which gets its ‘batteryvoltage’ either across the Host board from several “Supercap” large capacitors on the2070 power supply, or from the +5V supply. If power is removed from the 2070, thecontents of the SRAM will be retained for several weeks. The bus control line from theRTC/SRAM Supervisor chip provides a backup safety control on the write to the SRAMchip. Unlike the bus control from the micro, which enables chip selects and writeModel 2070L Operating Manual • 39

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