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Peek 2070L Operating Manual - Quality Traffic Systems

Peek 2070L Operating Manual - Quality Traffic Systems

Section 6 — Theory of

Section 6 — Theory of Operationcapability on all of the memory chips by going low, the SRAM Supervisor bus controlmakes the chip selection of the SRAM chip a condition of the quality of the +5VDCpower supply. This means that if power is lost to the Engine board, no unwanted writesto SRAM memory will occur even though the main bus control has fallen low (i.e.enabled write capabilities,) since the SRAM Supervisor bus control has prevented thechip select from also falling low, thus preventing a write to SRAM memory. Duringnormal operations, the SRAM Supervisor toggles its bus control to follow the bus controlof the micro whenever the microprocessor needs to read or write the contents of SRAM.Communications — Communications into and out of the engine board are managed bythe microcontroller and the DUART MC68302. The DUART, a microcontroller in its ownright, is here used as a slave device to the master MC68360 microcontroller. This isdone primarily to allow the MC68360 to control more serial ports than it has internally.Serial ports 2 through 6 go directly from the MC68360 to the host board connector, whileports 1 and 8 are controlled on the DUART across the data bus by the microcontroller.Ports 1 and 8 are full function serial ports, having full handshaking capability, which isone reason why they were exported to the DUART.One final aspect of communications we need to discuss is the way that Ethernet ishandled on the Engine board. The Ethernet port on the host board provides the outsideworld access to the CPU, and connects to the PHY through the required magnetics. Themicrocontroller speaks to the PHY, where the data is converted back and forth fromserial to Ethernet signals. Ethernet control signals pass back and forth between themicro and the PHY, as well. The LEDs on the front panel of the host board areultimately controlled by the PHY.Reset Management — Various elements of the 2070 Engine board handle the way thatresets are generated and handled. Reset Management consists of the reset generator,and connections to the 68360 micro and the DUART. Resets can be generated in anumber of ways: by a POWERDOWN/POWERUP signal from the power supplyor by a reset command sent from the microprocessor.A POWERUP signal (high-to-low), which is the state where the entire system will losepower completely within a few milliseconds, sends a hard reset to the reset generator. APOWERDOWN (high-to-low), which can indicate the interim state before a POWERUP(high-to-low) is reached, or it may just be a temporary brown-out, is sent to the resetgenerator, and to the Power Interrupt and High-to-Low pins on the microcontroller.The microcontroller can also be the source of a reset command (via its Reset OUT pin).This is usually the result of a serial port command into the micro requesting a 2070reboot.Note As on the Host board, although USB components are installed onthe Engine board, the USB interface is not currently implementedin this version of the 2070L controller.40 • Model 2070L Operating Manual

Section 6 — Theory of OperationFigure 20 – CPU Engine Board block diagramModel 2070L Operating Manual • 41

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