Power Optimization and Prediction Techniques for FPGAs - Jason H ...

1.2 MotivationDespite the relative weakness of FPGAs from the power angle, their power consumption has,until recently, been largely ignored by the research community. Likewise, no commercial FPGAvendors offer hardware or software specifically targeted to low-power applications. The extentto which FPGA power can be optimized through either CAD, architecture, or circuit techniqueshas been an open question. The focus of commercial vendors, as well as the majority ofpublished research on FPGA architecture and CAD, has concentrated on improving FPGA areaefficiencyand performance. A thorough treatment of prior research on FPGA speed and areais outside the scope here; however, references [Rose 89, Rose 91, Betz 96, Betz 97a, Betz 99a]present the first and seminal work on FPGA logic and routing architecture, with importantfollow-up work appearing in [Sing 90, Marq 99, Ahme 02]. CAD algorithms that optimize thearea and performance of FPGAs are well-studied, with some of the most important papers being[Brow 90, Fran 90, Fran 91a, Lemi 93, Cong 94a, Cong 94b, McMu 95, Betz 97b]. Thougharea and speed have been the main research focus to date, power is likely to be a key considerationin the design of future FPGAs, for the reasons outlined below.A well-known consequence of technology scaling is the rapid increase in static (leakage)power relative to dynamic power. Dynamic power is consumed as a result of logic transitionsthat occur on a circuit’s signals during normal operation. It increases in proportion to therate of logic transitions (switching activity) on circuit signals and the amount of capacitancecharged and discharged during logic transitions. Leakage power is consumed when a circuit is ina quiescent, idle state. Both dynamic and leakage power consumption have become major issuesfor semiconductor vendors and their customers [Inte 02]. Moreover, the considerable increase inleakage with each process generation has significant implications for FPGAs. Leakage currentin a circuit is proportional to the circuit’s total drawn transistor width [Jian 02]. Since FPGAscontain a huge number of transistors, as required to provide programmability, the need foreffective leakage management techniques is amplified in FPGAs versus in other technologies.Given this, low leakage is certain to be a significant design objective in next-generation FPGAs.Optimizing the power consumption of FPGAs has a number of benefits.First, reduced3