Power Optimization and Prediction Techniques for FPGAs - Jason H ...

2.2 Power Dissipation in CMOS CircuitsSubstituting (2.1) into (2.2) yields:E s = C · V DD∫ t1t 0dv c (t)dt∫ VDD2dt = C · V DD dv c = C · V DD0(2.3)The energy drawn from the supply in a rising transition on the gate’s output signal, E 01 ,is equal to E s . No energy is drawn from the supply when discharging the capacitor in a fallingtransition, and therefore, E 10 = 0. The average energy consumed per transition on the gate’soutput signal is:E trans = E 01 + E 102= E s + 02= C · V DD 22(2.4)The average dynamic power consumed by the gate, P gate , depends on the average rate of logictransitions on gate’s output signal:P gate = F trans · E trans = F trans · C · V DD22(2.5)where F trans is referred to as the switching activity of the gate output signal and is expressed inunits of transitions per second. In clocked circuits, it is convenient to normalize the switchingactivity by the clock period as follows:F trans = F clk · F (2.6)where F clk represents the system clock frequency and F represents the average number oftransitions on the gate output signal per clock cycle. F is referred to as the normalized switchingactivity.Substituting (2.6) into (2.5) and summing over all signals yields the familiar equation forthe average dynamic power consumed by a CMOS digital circuit:P avg = F clk2∑i ∈ signalsC(i) · F (i) · V DD2(2.7)where P avg represents average power consumption, C(i) is the load capacitance of a signal i,11