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Power Optimization and Prediction Techniques for FPGAs - Jason H ...

Power Optimization and Prediction Techniques for FPGAs - Jason H ...

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2.2 <strong>Power</strong> Dissipation in CMOS Circuits10 4I GATE(A/cm 2 )10 010 -80 1 2 3Gate voltage (V)Figure 2.3: Gate oxide leakage dependence on oxide thickness <strong>and</strong> gate bias [Thom 98].Impact of Technology Scaling on Leakage“The number of transistors on an integrated circuit doubles every 18 months.”Moore’s Law, first stated in the 1960s, has largely remained true <strong>for</strong> four decades, <strong>and</strong> isthe basis <strong>for</strong> the incredible growth of the semiconductor industry throughout this period. Suchdrastic scaling has been made possible by the seemingly endless ability to shrink the size of atransistor, markedly increasing the density of transistors on a single IC.As transistors are made smaller, there are two important consequences. First, the exponentialgrowth in the number of devices on a single chip leads to a higher power consumption.Second, the electric fields internal to a transistor increase, which impacts transistor reliability 2 .To address these issues, supply voltage must be scaled in t<strong>and</strong>em with feature size. Figure 2.4(from [Doyl 02]) shows the scaling of transistor gate length <strong>and</strong> supply voltage versus processgeneration. The supply voltage scales at approximately 0.85X per generation; the gate lengthscales at approximately 0.65X per generation.The drive capability <strong>and</strong> associated speed per<strong>for</strong>mance of a transistor depends on the mag-2 Field strength in an MOS transistor influences failure due to gate oxide breakdown [Amer 98].15

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