Power Optimization and Prediction Techniques for FPGAs - Jason H ...

2.3 FPGA Architecture and Hardware Structuresrouting trackslogic blockf1f2f3f44-LUTclkD FFMUXI/Ob) logic blockSRAM cellSSSS...SMUXa) abstract FPGA structuref1 f2 f3 f4c) 4-LUTFigure 2.8: (a) Abstract FPGA architecture; (b) logic block; (c) LUT.spersed between rows and columns of logic blocks. Today’s commercial FPGAs use look-uptables(LUTs) as the base element for implementing combinational logic functions, and containflip-flops for implementing sequential logic. A K-input LUT (K-LUT) is a small memory capableof implementing any logic function that uses, at most, K inputs. A simplified FPGA logicblock is shown in Figure 2.8(b), comprising a 4-LUT along with a flip-flop. A programmablemultiplexer allows the flip-flop to be bypassed. Figure 2.8(c) shows the internal details of a4-LUT. 16 SRAM cells hold the truth table for the logic function implemented by the LUT.The LUT inputs, labeled f1–f4, select a particular SRAM cell whose content is passed to theLUT output.The logic blocks in commercial FPGAs are more complex than that of Figure 2.8(b) andcontain clusters of LUTs and flip-flops. Figure 2.9 shows the logic blocks in Virtex-4 andStratix II. A Virtex-4 logic block [Figure 2.9(a)] is referred to as a Configurable Logic Block(CLB) and it contains 4 SLICEs, where each SLICE has two 4-LUTs, two flip-flops, as well21