Power Optimization and Prediction Techniques for FPGAs - Jason H ...

2.5 FPGA Power OptimizationLUTswitchingactivity10310 3logic functionprimary input53331 753331 7Figure 2.17: Power-aware technology mapping.connect, as illustrated in Figure 2.17. The figure shows two mapping solutions for a circuit.The nodes represent logic functions; the shaded regions represent LUTs. Switching activityvalues are shown adjacent to each signal. In the left mapping solution, the high activity signal(with activity 10) is covered within a LUT, and therefore, this signal is not required tobe routed through the interconnect. In the right mapping solution, the high activity signal isbetween LUTs and thus, must be routed through the interconnect. It is conceivable that thetwo mapping solutions have considerably different power characteristics.In an early work, Farrahi and Sarrafzadeh proposed an algorithm that minimized power atthe expense of both area and depth [Farr 94]. Their algorithm provides a 14% power improvementover an algorithm that solely optimizes area. Li, Mak, and Katkoori presented an algorithmthat optimizes power in the portions of a circuit that are not depth-critical [Li 01]. Theirapproach reduces the mapping problem to a network flow formulation, similar to FlowMap [Cong 94a].The authors use a novel approach to translate power objectives into edge capacities in the flownetwork. In [Wang 01], the authors focused on optimizing both area and power. Their methodcomputes a set of candidate mapping solutions for each node in an input network, and appliesa cost function to select the best solution. The approach yields mapping solutions that use 14%less power than those produced by [Farr 94], while at the same time requiring fewer LUTs.Each published technology mapping algorithm has been shown to produce mapping solutions35