- Page 4 and 5: When using this document, keep the
- Page 6 and 7: Section 8. Write Precompensation Ci
- Page 8 and 9: • The delay from the detection of
- Page 10 and 11: Table 1-1.FDC Commands (cont)Comman
- Page 12 and 13: VCC1-VCC4VSS1 -VSS3NUM1NUM2SFORMIFS
- Page 14 and 15: Table 2-1.Pin Functions (cont)TypeP
- Page 16 and 17: INDEX (Index): INDEX inputs the ind
- Page 18 and 19: SECTION 3.INTERNAL REGISTERS3.1 INT
- Page 20 and 21: SECTION 4.HOST INTERFACEThis FDC ca
- Page 22 and 23: 1-01 ·--------1024SECTION 5.DRIVE
- Page 24 and 25: SECTION 6.COMMAND DESCRIPTION6.1 CO
- Page 26 and 27: HA (figure 6-3) specifies a sector'
- Page 28 and 29: 6.2.9 SCNT: Sector CountD D",,1. __
- Page 30 and 31: specified as in table 6-3.Table 6-3
- Page 32 and 33: "",1Table 6-5.Head Load TimesSet Va
- Page 34 and 35: 6.2.18 PCDCT: Precompensation Delay
- Page 36 and 37: . MT = 0: The last sector is specif
- Page 38 and 39: 6.3.6 PCN: Physical Cylinder Number
- Page 40 and 41: Read request in Non-DMA modeTXR DIR
- Page 42 and 43: 6.4.5 Command Issue FlowchartInput
- Page 44 and 45: SEEK, RECALIBRATEcommandWrite a com
- Page 46 and 47: CHECK INTERRUPTSTATUS commandRead a
- Page 48 and 49: Figure 6-36.SLEEP Command Issue Flo
- Page 50 and 51: the ID. If the ID address mark cann
- Page 52 and 53:
Table 6-10.DEN5 at the Last Byte of
- Page 54 and 55:
6.5.3 READ ERRONEOUS DATABi t D7 D6
- Page 56 and 57:
6.5.4 READ IDBit D7 D6 D5 D4- D3 D2
- Page 58 and 59:
MFM modeData: HEX Al HEX Al HEX Al
- Page 60 and 61:
6.5.6 WRITE DELETED DATABit D7 D6 D
- Page 62 and 63:
the next index pulse is detected.Wh
- Page 64 and 65:
Seek Completion: After all the calc
- Page 66 and 67:
6.5.10 COMPARE EQUALBit D7 D6 D5 D4
- Page 68 and 69:
Comparison Condition: When the data
- Page 70 and 71:
6.5.12 COMPARE HIGH OR EQUALBi t D7
- Page 72 and 73:
6.5.14 CHECK INTERRUPT STATUSBit D7
- Page 74 and 75:
6.5.16 SPECIFY 2Bit D7 I D6 I D5 I
- Page 76 and 77:
6.5.18 ABORTBit D7 I D6 r D5 1 D4-
- Page 78 and 79:
6.5.20 WRITE LONGBit D7 D6 D5 D4- D
- Page 80 and 81:
6.6 TRACK FORMATFigure 6-59 shows t
- Page 82 and 83:
IRQ is asserted to request CIS comm
- Page 84 and 85:
Table 6-15.STR Changes for Each Com
- Page 86 and 87:
Command issue startNoYesYesWrite co
- Page 88 and 89:
Command issue startNoYesThe STR mus
- Page 90 and 91:
Command issue startYesYesBSY isset
- Page 92 and 93:
FDC internalclockr-----------------
- Page 94 and 95:
7.3 PLL CIRCUITThis PLL circuit, el
- Page 96 and 97:
SECTION 9.SYSTEM APPLICATION9.1 SYS
- Page 98 and 99:
9.3 DATA TRANSFER TIMINGThe FDC per
- Page 100 and 101:
IRQ or DREQCSoR/WoEor DACKoR/WoEDAT
- Page 102 and 103:
9.4.2 DEN5 Signal for WRITEDEND Sig
- Page 104 and 105:
HD64B180To memory circuit{(Add ress
- Page 106 and 107:
IOERDcsWR/1 ~ _____________________
- Page 108 and 109:
Host(HD64180)DMAC(HD64180built-in)F
- Page 110 and 111:
HD64BlSOR/W switch circuit,--------
- Page 112 and 113:
9.7 FDD INTERFACEExamples of a 5"/3
- Page 114 and 115:
HD63265(FDC)LS153EARLY LATE Yo o Co
- Page 116 and 117:
Applicable Floppy Disk Drives: The
- Page 118 and 119:
Table 9-6.5" FDD Interface Signals
- Page 120 and 121:
SECTION 10.CHARACTERISTICS10.1 ABSO
- Page 122 and 123:
10.3.2 AC Timing SpecificationNo. I
- Page 124 and 125:
@ PWHRDTRDATA(f) PWLRDTWDATAFigure
- Page 126 and 127:
-t eye E @..e----tEr:@@ - -tEf@PWEH
- Page 128 and 129:
WGATEHSEL ;-_______________________
- Page 130 and 131:
10.4 PACKAGE DIMENSIONS• DP-48 (U
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HITACHI, LTD. SEMICONDUCTOR ANDINTE