Résumé Lars Bauer - CES - KIT
Résumé Lars Bauer - CES - KIT
Résumé Lars Bauer - CES - KIT
You also want an ePaper? Increase the reach of your titles
YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.
<strong>CES</strong> – Chair for Embedded Systems<br />
Department of Informatics<br />
<strong>KIT</strong> – Karlsruhe Institute of Technology<br />
Haid-und-Neu-Str. 7 (Building 07.21)<br />
76131 Karlsruhe, Germany<br />
Phone: +49 (0) 721 608 44218<br />
Fax: +49 (0) 721 608 43962<br />
eMail: lars.bauer@kit.edu<br />
Web: http://ces.itec.kit.edu/~bauer<br />
<strong>Résumé</strong> <strong>Lars</strong> <strong>Bauer</strong><br />
Short CV<br />
2011 – present Head of the <strong>KIT</strong> Young Investigator Group (YIG) “Methods and Architectures for emerging dynamically<br />
reconfigurable systems”.<br />
2009 – present Research Assistant, Lecturer, and Group Leader at the Chair for Embedded Systems, Computer<br />
Science Department, Karlsruhe Institute of Technology (<strong>KIT</strong>), Germany.<br />
2009 Doctorate (Dr.-Ing., Summa cum Laude) at the Department of Informatics, University of Karlsruhe<br />
(TH). Thesis: “RISPP: A Run-time Adaptive Reconfigurable Embedded Processor” (Supervisor:<br />
Prof. Dr.-Ing. Jörg Henkel).<br />
2004 – 2009 Doctoral Researcher at the Chair for Embedded Systems (Prof. Dr.-Ing. Jörg Henkel), Department<br />
of Informatics, University of Karlsruhe (TH).<br />
2004 Graduation (Dipl.-Inform., Magna cum Laude) at the University of Karlsruhe (TH).<br />
2000 – 2002 Student Assistant (HiWi) at the Department of Informatics, University of Karlsruhe (TH).<br />
1998 – 2004 Computer Science student at the University of Karlsruhe (TH) with majors in Embedded Systems,<br />
Electrical Engineering, and Software Engineering/Compiler Construction.<br />
Research Interests<br />
� Reconfigurable processors (hardware, tools, run-time systems, compilers)<br />
� reconfigurable and adaptive (multi-core) computing systems<br />
� concepts that allow (multi-core) systems to adapt to dynamically varying run-time situations or changing user<br />
requirements<br />
� extensible processors (ASIPs)<br />
Awards and Honors<br />
� Best elective lecture (based on teaching evaluation) for the lecture „Optimization and Synthesis of Embedded<br />
Systems” in the winter term 2011/2012, Department of Informatics, Karlsruhe, Germany, July 2012.<br />
� Best elective lecture (based on teaching evaluation) for the lecture „Reconfigurable and Adaptive Systems” in<br />
the summer term 2011, Department of Informatics, Karlsruhe, Germany, February 2012.<br />
� MaXentric Technologies AHS 2011 Best Paper Award for the paper “Concepts, Architectures, and Run-time<br />
Systems for Efficient and Adaptive Reconfigurable Processors”, San Diego, CA, USA, June 2011.<br />
� Promotion as Young Investigator within the Excellence Initiative of the <strong>KIT</strong> with 80,000 Euro per year over<br />
the next 4 years (2011-2015; altogether 320,000 Euro), Karlsruhe, Germany, March 2011.<br />
L. <strong>Bauer</strong>, July 17, 2012 1/6
� EDAA Outstanding Dissertations Award (prize money EUR 1,000) of the European Design and Automation<br />
Association (EDAA) for “New directions in embedded system design and embedded software”, Grenoble,<br />
France, March 2011.<br />
� Outstanding Dissertation Award (prize money EUR 1,500) of the ‘Foerderverein des Forschungszentrum<br />
Informatik (FZI)’ (Research Center for Information Technologies), Karlsruhe, Germany, February 2011.<br />
� IEEE/ACM William J. McCalla ICCAD 2010 Best Paper Candidate for the paper “Selective Instruction Set<br />
Muting for Energy-Aware Adaptive Processors”, San Jose, CA, USA, November 2010.<br />
� Ph.D. was distinguished as “Summa cum Laude”, Karlsruhe, Germany, December 2009.<br />
� Design Automation and Test in Europe Conference (DATE 2008) Best Paper Award for the paper “Run-time<br />
System for an Extensible Embedded Processor with Dynamic Instruction Set”, Munich, Germany, March 2008.<br />
� 3 European Network of Excellence on High Performance and Embedded Architecture and Compilation<br />
(HiPEAC) Paper Awards for papers at DAC 2008, FCCM 2011, and FCCM 2012.<br />
Professional Services<br />
� DATE (IEEE Design, Automation & Test in Europe) Topic D10 “Architectural and High-Level Synthesis”:<br />
Technical Program Committee member: 2013<br />
� CODES+ISSS (International Conference on Hardware/Software Codesign and System Synthesis): Technical<br />
Program Committee member: 2010, 2011, 2012<br />
� SIES (IEEE International Symposium on Industrial Embedded Systems): co-Chair of the work-in-progress session:<br />
2012<br />
� ESTIMedia (IEEE Symposium on Embedded Systems for Real-time Multimedia): Technical Program Committee<br />
member: 2011, 2012<br />
� VLSI (International Conference on VLSI Design): Technical Program Committee member: 2012<br />
� CPSNA (International Workshop on Cyber-Physical Systems, Networks, and Applications): Technical Program<br />
Committee member: 2011, 2012<br />
� PARMA (Workshop on Parallel Programming and Run-time Management Techniques for Many-core Architectures):<br />
Technical Program Committee member: 2011, 2012<br />
� ESWeek (Embedded Systems Week): Publicity Chair: 2011<br />
� RTAS (IEEE Real-Time and Embedded Technology and Applications Symposium): Technical Program<br />
Committee member: 2011<br />
� Reviewer for many international Journals and Conferences, e.g. IEEE Transactions on Very Large Scale Integration<br />
Systems (TVLSI), ACM Transactions on Design Automation of Electronic Systems (TODAES), IEEE<br />
Transactions on Computers (TC), ACM Transactions in Embedded Computing Systems (TECS), ACM Transactions<br />
on Reconfigurable Technology and Systems (TRETS), IEEE Transactions on Circuits and Systems<br />
(TCAS), International Journal of Reconfigurable Computing (IJRC), Design Automation Conference (DAC),<br />
International Conference on Computer-Aided Design (ICCAD), Asia and South Pacific Design Automation<br />
Conference (ASP-DAC), International Conference on Hardware/Software Codesign and System Synthesis<br />
(CODES+ISSS), International Conference on Compilers, Architecture, and Synthesis (CASES), ISLPED,<br />
SiPS, SASP, SCOPES, ISVLSI, ARCS, RSP, IC-SAMOS and others.<br />
Projects from Third-Party Funding<br />
� “Methods and Architectures for emerging dynamically reconfigurable systems”, 4-year project (2011-2015),<br />
funded by the Karlsruhe Institute of Technology (<strong>KIT</strong>) as a Young Investigator Group (YIG) with 80,000 Euro<br />
(approximately 1.5 research positions) per year, altogether 320,000 Euro.<br />
Role: Principal Investigator<br />
L. <strong>Bauer</strong>, July 17, 2012 2/6
Books<br />
� “Adaptive Application-Specific Invasive Microarchitectures”, 4-year project (2010-2014) within the SFB-<br />
TR 89 “Invasive Computing”, funded by Deutsche Forschungsgemeinschaft (DFG); our part: 1 research position.<br />
Role: Principal Investigator<br />
� “Invasive Run-Time Support System (iRTSS)”, 4-year project (2010-2014) within the SFB-TR 89 “Invasive<br />
Computing”, funded by Deutsche Forschungsgemeinschaft (DFG); our part: 1 research position.<br />
Role: Principal Investigator<br />
� “OTERA: Online Test Strategies for Reliable Reconfigurable Architectures”, 2-year project (2010-2012) within<br />
the SPP 1500 “Design and Architectures of Dependable Embedded Systems – A Grand Challenge in the<br />
Nano Age”, funded by Deutsche Forschungsgemeinschaft (DFG); our part: 1 research position.<br />
Role: Contribution to writing proposal and research<br />
� Industrial project in the automotive domain, 1.5-year project (2010-2012) funded by Bundesministerium für<br />
Wirtschaft und Technologie (BMWi); our part: 2 research positions.<br />
Role: Contribution to writing proposal and research<br />
� “KAHRISMA (KArlsruhe’s Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array) Architecture”,<br />
3-year project (2009-2012) funded by Deutsche Forschungsgemeinschaft (DFG); our part: 1 research<br />
position.<br />
Role: Contribution to writing proposal and research<br />
� “DodOrg: Stability and Robustness”, 2-year project (2009-2011) within the SPP 1183 “Organic Computing”,<br />
funded by Deutsche Forschungsgemeinschaft (DFG); our part: 1 research position.<br />
Role: Contribution to writing proposal<br />
� “DodOrg: Plasticity, Dynamics, and Stability”, 1-year project (2008-2009) within the SPP 1183 “Organic<br />
Computing”, funded by Deutsche Forschungsgemeinschaft (DFG); our part: 1 research position.<br />
Role: Contribution to writing proposal<br />
Invited Talks<br />
� “Adaptive Reconfigurable Instruction Set Processors”, GI/ITG Workshop on ‘Reconfigurable Systems: Architectures,<br />
Tools, Applications’, Darmstadt, Germany, April 2011.<br />
� “Automatic extraction and selection of complex modular Special Instructions for reconfigurable processor architectures”,<br />
Intel Workshop on ‘Approaches and tools for efficient design of SoCs’, St. Petersburg, Russia,<br />
November 2010.<br />
� “Run-time Adaptation for Reconfigurable Embedded Processors”, Dagstuhl Seminar on ‘Dynamically Reconfigurable<br />
Architectures’, Schloss Dagstuhl - Leibniz Center for Informatics, Germany, July 2010.<br />
� “KAHRISMA: A Multi-grained Reconfigurable Multicore Architecture”, 10th International Forum on Embedded<br />
MPSoC and Multicore (MPSoC´10), Gifu city, Gifu, Japan, June/July 2010.<br />
� “RISPP: Rotating Instruction Set Processing Platform”, Colloquium of the DFG Priority Program 1148<br />
‘Rekonfigurierbare Rechensysteme’ (Reconfigurable Computing Systems) (SPP-RR), Karlsruhe, Germany,<br />
September 2009.<br />
� “Classifying and Evaluating Performance-relevant Parameters for Reconfigurable Processors”, 9th International<br />
Forum on Embedded MPSoC and Multicore (MPSoC´09), Savannah, GA, USA, August 2009.<br />
Publications<br />
� L. <strong>Bauer</strong>, J. Henkel, “Run-time Adaptation for Reconfigurable Embedded Processors”, Springer Science +<br />
Business Media, LLC, 2011, ISBN 978-1-4419-7411-2, e-ISBN 978-1-4419-7412-9, DOI 10.1007/978-1-<br />
4419-7412-9.<br />
L. <strong>Bauer</strong>, July 17, 2012 3/6
Journals/Magazines<br />
� M. Shafique, L. <strong>Bauer</strong>, J. Henkel, “Optimizing the H.264/AVC Video Encoder Application Structure for Reconfigurable<br />
and Application-Specific Platforms”, Journal of Signal Processing Systems (JSPS’10), Special<br />
Issue: Embedded Multimedia Systems, Volume 60, Issue 2, pp. 183-210, August 2010.<br />
� L. <strong>Bauer</strong>, M. Shafique, J. Henkel, “Efficient Resource Utilization for an Extensible Processor through Dynamic<br />
Instruction Set Adaptation”, IEEE Transaction on Very Large Scale Integration (TVLSI’08), Special Section<br />
on Application-Specific Processors, Volume 16, Issue 10, pp. 1295-1308, October 2008.<br />
Conferences/Symposia<br />
� M. Abdelfattah, L. <strong>Bauer</strong>, C. Braun, M. E. Imhof, M. A. Kochte, H. Zhang, J. Henkel and H.-J. Wunderlich:<br />
“Transparent Structural Online Test for Reconfigurable Systems”, IEEE International On-Line Testing Symposium<br />
(IOLTS’12), Sitges, Spain, pp. 37-42, June 2012.<br />
� L. <strong>Bauer</strong>, C. Braun, M. E. Imhof, M. A. Kochte, H. Zhang, H.-J. Wunderlich and J. Henkel: “OTERA: Online<br />
Test Strategies for Reliable Reconfigurable Architectures”, NASA/ESA Conference on Adaptive Hardware and<br />
Systems (AHS’12), Nuremberg, Germany, pp. 38-45, June 2012.<br />
� L. <strong>Bauer</strong>, A. Grudnitsky, M. Shafique, J. Henkel: “PATS: a Performance Aware Task Scheduler for Runtime<br />
Reconfigurable Processors”, 20th Annual International IEEE Symposium on Field-Programmable Custom<br />
Computing Machines (FCCM’12), Toronto, Canada, pp. 208-215, April/May 2012.<br />
Received a “European Network of Excellence on High Performance and Embedded Architecture and Compilation”<br />
HiPEAC Paper Award.<br />
� A. Grudnitsky, L. <strong>Bauer</strong>, J. Henkel: “Partial Online-Synthesis for Mixed-Grained Reconfigurable Architectures”,<br />
IEEE/ACM 15th Design Automation and Test in Europe Conference (DATE’12), Dresden, Germany,<br />
pp. 1555-1560, March 2012.<br />
� F. Hameed, L. <strong>Bauer</strong>, J. Henkel: “Dynamic Cache Management in Multi-Core Architectures through Run-time<br />
Adaptation”, IEEE/ACM 15th Design Automation and Test in Europe Conference (DATE’12), Dresden, Germany,<br />
pp. 485-490, March 2012.<br />
� J. Henkel, A. Herkersdorf, L. <strong>Bauer</strong>, T. Wild, M. Hübner, R.K. Pujari, A. Grudnitsky, J. Heisswolf, A. Zaib, B.<br />
Vogel, V. Lari, S. Kobbe: “Invasive Manycore Architectures”, 16th Asia and South Pacific Design Automation<br />
Conference (ASP-DAC’12), Sydney, Australia, pp. 193-200, January/February 2012.<br />
� S. Kobbe, L. <strong>Bauer</strong>, J. Henkel, D. Lohmann, W. Schröder-Preikschat: “DistRM: Distributed Resource Management<br />
for On-Chip Many-Core Systems”, IEEE International Conference on Hardware/Software Codesign<br />
and System Synthesis (CODES+ISSS’11), Taipei, Taiwan, pp. 119-128, October 2011.<br />
� W. Ahmed, M. Shafique, L. <strong>Bauer</strong>, J. Henkel: “Adaptive Resource Management for Simultaneous Multitasking<br />
in Mixed-Grained Reconfigurable Multi-core Processors”, IEEE International Conference on Hardware/Software<br />
Codesign and System Synthesis (CODES+ISSS’11), Taipei, Taiwan, pp. 365-374, October<br />
2011.<br />
� J. Henkel, L. <strong>Bauer</strong>, J. Becker, O. Bringmann, U. Brinkschulte, S. Chakraborty, M. Engel, R. Ernst, H. Härtig,<br />
L. Hedrich, A. Herkersdorf, R. Kapitza, D. Lohmann, P. Marwedel, M. Platzner, W. Rosenstiel, U.<br />
Schlichtmann, O. Spinczyk, M. Tahoori, J. Teich, N. Wehn, H.-J. Wunderlich: “Design and Architectures for<br />
Dependable Embedded Systems”, IEEE International Conference on Hardware/Software Codesign and System<br />
Synthesis (CODES+ISSS’11), Taipei, Taiwan, pp. 69-78, October 2011.<br />
� J. Henkel, L. <strong>Bauer</strong>, M. Hübner, A. Grudnitsky: “i-Core: A run-time adaptive processor for embedded multicore<br />
systems”, International Conference on Engineering of Reconfigurable Systems and Algorithms<br />
(ERSA’11), Las Vegas, Nevada, USA, July 2011 (invited paper).<br />
� L. <strong>Bauer</strong>, M. Shafique, J. Henkel, “Concepts, Architectures, and Run-time Systems for Efficient and Adaptive<br />
Reconfigurable Processors”, NASA/ESA 6th Conference on Adaptive Hardware and Systems (AHS’11), San<br />
Diego, CA, USA, pp. 80-87, June 2011 (invited paper).<br />
Received the MaXentric Technologies AHS’11 Best Paper Award.<br />
L. <strong>Bauer</strong>, July 17, 2012 4/6
� W. Ahmed, M. Shafique, L. <strong>Bauer</strong>, M. Hammerich, J. Henkel, J. Becker, “Run-Time Resource Allocation for<br />
Simultaneous Multi-Tasking in Multi-Core Reconfigurable Processors”, IEEE 19th Symposium on Field-<br />
Programmable Custom Computing Machines (FCCM’11), Salt Lake City, Utah, USA, pp. 29-32, May 2011.<br />
Received a “European Network of Excellence on High Performance and Embedded Architecture and Compilation”<br />
HiPEAC Paper Award.<br />
� M. Shafique, L. <strong>Bauer</strong>, W. Ahmed, J. Henkel, “Minority-Game-based Resource Allocation for Run-Time Reconfigurable<br />
Multi-Core Processors”, IEEE/ACM 14th Design Automation and Test in Europe Conference<br />
(DATE’11), Grenoble, France, pp. 1261-1266, March 2011.<br />
� W. Ahmed, M. Shafique, L. <strong>Bauer</strong>, J. Henkel, “mRTS: Run-Time System for Reconfigurable Processors with<br />
Multi-Grained Instruction-Set Extensions”, IEEE/ACM 14th Design Automation and Test in Europe Conference<br />
(DATE’11), Grenoble, France, pp. 1554-1559, March 2011.<br />
� M. Shafique, L. <strong>Bauer</strong>, J. Henkel, “Selective Instruction Set Muting for Energy-Aware Adaptive Processors”,<br />
IEEE/ACM 28th International Conference on Computer-Aided Design (ICCAD’10), San Jose, CA, USA, pp.<br />
353-360, November 2010.<br />
Nominated as IEEE/ACM William J. McCalla ICCAD’10 Best Paper Candidate.<br />
� R. Koenig, L. <strong>Bauer</strong>, T. Stripf, M. Shafique, W. Ahmed, J. Becker, J. Henkel, “KAHRISMA: A Novel<br />
Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array Architecture”, IEEE/ACM 13th Design<br />
Automation and Test in Europe Conference (DATE’10), Dresden, Germany, pp. 819-824, March 2010.<br />
� M. Shafique, L. <strong>Bauer</strong>, J. Henkel, “enBudget: A Run-Time Adaptive Predictive Energy-Budgeting Scheme for<br />
Energy-Aware Motion Estimation in H.264/MPEG-4 AVC Video Encoder”, IEEE/ACM 13th Design Automation<br />
and Test in Europe Conference (DATE’10), Dresden, Germany, pp. 1725-1730, March 2010.<br />
� M. Shafique, L. <strong>Bauer</strong>, J. Henkel, “REMiS: Run-time Energy Minimization Scheme in a Reconfigurable Processor<br />
with Dynamic Power-Gated Instruction Set”, IEEE/ACM 27th International Conference on Computer-<br />
Aided Design (ICCAD’09), San Jose, California, USA, pp. 55-62, November 2009.<br />
� L. <strong>Bauer</strong>, M. Shafique, J. Henkel, “MinDeg: A Performance-guided Replacement Policy for Run-time Reconfigurable<br />
Accelerators”, IEEE International Conference on Hardware-Software Codesign and System Synthesis<br />
(CODES+ISSS’09), Grenoble, France, pp. 335-342, October 2009.<br />
� L. <strong>Bauer</strong>, M. Shafique, J. Henkel, “Cross-Architectural Design Space Exploration Tool for Reconfigurable<br />
Processors”, IEEE/ACM 12th Design Automation and Test in Europe Conference (DATE’09), Nice, France,<br />
pp. 958-963, April 2009.<br />
� M. Shafique, L. <strong>Bauer</strong>, J. Henkel, “A Parallel Approach for High Performance Hardware Design of Intra Prediction<br />
in H.264/AVC Video Codec”, IEEE/ACM 12th Design Automation and Test in Europe Conference<br />
(DATE’09), Nice, France, pp. 1434-1439, April 2009.<br />
� L. <strong>Bauer</strong>, M. Shafique, J. Henkel, “A Computation- and Communication-Infrastructure for Modular Special Instructions<br />
in a Dynamically Reconfigurable Processor”, IEEE 18th International Conference on Field Programmable<br />
Logic and Applications (FPL’08), Heidelberg, Germany, pp. 203-208, September 2008.<br />
� M. Shafique, L. <strong>Bauer</strong>, J. Henkel, “3-Tier Dynamically Adaptive Power-Aware Motion Estimator for<br />
H.264/AVC Video Encoding”, ACM/IEEE International Symposium on Low Power Electronics and Design<br />
(ISLPED’08), Bangalore, India, pp. 147-152, August 2008.<br />
� L. <strong>Bauer</strong>, M. Shafique, J. Henkel, “Run-time Instruction Set Selection in a Transmutable Embedded Processor”,<br />
ACM/IEEE/EDA 45th Design Automation Conference (DAC’08), Anaheim, CA, USA, pp. 56-61, June<br />
2008.<br />
Received a “European Network of Excellence on High Performance and Embedded Architecture and Compilation”<br />
HiPEAC Paper Award.<br />
� L. <strong>Bauer</strong>, M. Shafique, S. Kreutz, J. Henkel, “Run-time System for an Extensible Embedded Processor with<br />
Dynamic Instruction Set”, IEEE/ACM 11th Design Automation and Test in Europe Conference (DATE’08),<br />
Munich, Germany, pp. 752-757, March 2008.<br />
Received the DATE´08 Best Paper Award.<br />
� L. <strong>Bauer</strong>, M. Shafique, D. Teufel, J. Henkel, “A Self-Adaptive Extensible Embedded Processor”, IEEE/ACM<br />
First International Conference on Self-Adaptive and Self-Organizing Systems (SASO’07), Boston, MA, USA,<br />
pp. 344-347, July 2007.<br />
� L. <strong>Bauer</strong>, M. Shafique, S. Kramer, J. Henkel, “RISPP: Rotating Instruction Set Processing Platform”,<br />
ACM/IEEE/EDA 44th Design Automation Conference (DAC’07), San Diego, CA, USA, pp. 791-796, June<br />
2007.<br />
L. <strong>Bauer</strong>, July 17, 2012 5/6
Workshops<br />
� B. Oechslein, J. Schedel, J. Kleinöder, L. <strong>Bauer</strong>, J. Henkel, D. Lohmann, W. Schröder-Preikschat, “OctoPOS:<br />
A Parallel Operating System for Invasive Computing”, Systems for Future Multi-Core Architectures<br />
(SFMA’11), Salzburg, Austria, April 2011.<br />
� M. Shafique, L. <strong>Bauer</strong>, J. Henkel, “Optimized Application Architecture of the H.264 Video Encoder for Application<br />
Specific Platforms”, 5th IEEE Workshop on Embedded Systems for Real-Time Multimedia<br />
(ESTIMedia’07), Salzburg, Austria, pp. 119-124, October 2007.<br />
� L. <strong>Bauer</strong>, M. Shafique, J. Henkel, “Efficient Resource Utilization for an Extensible Processor through Dynamic<br />
Instruction Set Adaptation”, 5th Workshop on Application Specific Processors (WASP’07), Salzburg, Austria,<br />
pp. 39-46, October 2007.<br />
L. <strong>Bauer</strong>, July 17, 2012 6/6