Logic Simulation - GPU Technology Conference

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Logic Simulation - GPU Technology Conference

SoC Design Flow#include "shiftreg.h"int sc_main(int argc, char* argv[]) {sc_signal reset, din, dout;sc_clock clk("clk",10,SC_NS);// Local signals// Create a 10ns period clock signalElectronic SystemLevel Designshiftreg DUT("shiftreg");DUT.clk(clk);// Instantiate Device Under Test// Connect portsDUT.reset(reset);DUT.din(din);DUT.dout(dout);…}Input SpecificationArchitecture explorationSoCSimulationModelHW/SW Partitioning36Application Mapping36

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