International EDA Roadmapgoals(proposal)Joseph BorelJB‐R&D (07 2009)
Acceleration: more options in a shorter time frame forsystem on chip …with faster ramp-up of volumes and yieldsSource: CATRENEEuropean program
Product development cost evolutionSource CATRENEeuropean program
Fabless companies moving in the top twenty ranking
Business evolution consequences• Need to have a design solution starting fromsystem level specifications.• Covering ESL design down to physicalimplementation.• Deep submicron process constraints and TSVto incorporate in the design flow:‐TCAD for design for variability.‐TSV specific multitechnology constraints.‐Handling SEUs mitigation.• Open design flow to SMEs innovations.
Design Flow from Specifications to RTLSpecificationPlatformESLHW‐SWPartitionningImplementation‐ExecutableSpecifications.‐Refinements.‐Micro‐architecture‐Validation.‐Virtual Prototype‐Virtual prototypeRTLRTL & e‐SWJ. Borel JB‐R&D6
System Specification platform needs(source Nokia)J. Borel JB‐R&D July 20087
From System specification to RTLV‐1V‐2 V‐3V‐4
Needs for a standard design environment
Needs for an easy access to various librariesSource CATRENE EDA Roadmap 2009
Post Moore’s Law with TSV processCost per function22nm Cmos limit (2010)NEMs,biocells, Optical com.IP-Xact cells countCATRENE Workshopp May 26‐28 2009 J.Borel JB‐R&D.
TSV forecasted EDA Roadmap
Main steps in joint nanoprocess rules,deviceoptimisation and circuit manufacturabilityDefinition Development Platform Validation ManufacturingProductAnalogue & Digital,FT & reconfigurabilityTest chips in A&D,Memories,earlycomplex productsQualification,Ramp up performanceand maximum yieldTCAD,Design andManufacturabilityToolsTCAD, LithoModeling,DfMsimulations….Design tools forperformance,SI,manufacturability,low Power designFault toleranceof products & SIcontrol (SI,EMCs,SEUs..)ProcessVariability,proximity,effects,speed, powerconsumption…..Optimisation: cost,variability, proxyeffects, quality…Fine tuning for yieldperformance & costVs product familiesJ. Borel JB‐R&D13
Time to Market Revenue PenaltiesLearning Curve(cost)Design performance$ RevenueManufacturingperformanceMarketGrowthDeclineA ‐ On time market entryB ‐ Delayed market entry($ lost = $ Revenue D (3W‐D) )2W²Market : $R = 300M2W = 6 months$ Lost/month : 133MABCompetitiveness :Learning curve impactD(Delay)WMarket Windows2WProduct LifeTime10/08/2009Joseph Borel JB‐R&DMarch 2006Source: JB‐R&D14
Catrene 2009 EDA Roadmap chaptersV.1 Roadmap for System Level Specification of SoC/SiP (page 57).V.2 Roadmap for ESL Virtual System Modelling (page70).V.3 Roadmap for eSW and ESL to RTL (page 97).V.4.1 Roadmap for Mixed Analogue/Digital & RF (page125).V.4.2 Roadmap for Electronic Design Automation for MEMS (page126).V.5 Roadmap for ‘3D Integration’ Design Automation (page160).V.6 Roadmap for Parasitic Extraction, Modelling and Simulation (page 182)V.7 Roadmap for IP Reuse Platform (page 215).V.8 Roadmap for Verification and Validation (page 229).V.9 Roadmap for Low Power Design Solutions (page 243).V.10 Roadmap for Rapid System Protoyping (page 262)V.11 Roadmap for Test Development for SoC and SiP (page 284).V.12 Roadmap for Design for Manufacturability (page 289).V.13 Roadmap for Start-Ups Contribution to Innovation in EDA (page 296).V.14 Roadmap for Multi-Applications Platform Development (page313).V.15 Roadmap for TCAD (page324).V.16 Roadmap for Reliability (page 330).http://www.medeaplus.org/web/communication/publ_eda.php
As a conclusion to be discussed…!(with reference to EETIMES interview).1‐Major benefits of a common international EDARoadmapshouldbe common design and libraryenvironments, focussing EDA ressources on strategicneeds of System houses (the customers) andavoiding duplication of efforts.2‐DATE 09 in Europe, there were two separate panelsof EDA CTOs and Systems developers!!!3‐EDA industry CTOs should anticipate these needs andshare development efforts (not duplicate!).4‐Additionally this will help better access from StartUps tools to business through their innovations.…that’s exactly what TSMC tried to do with its reference flow!