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Device Guidelines for PCIExpress* Technology ExtensionsJaya Jeyaseelan,Client Platform Architect, Intel CorporationDavid Fair,Enterprise IHV Enabling Manager, Intel CorporationPCIS002


Agenda• Impact of devices on platform power• Introduction to the power managementextensions – LTR and OBFF• Implementation guidelines for typicaldevices on mobile and desktop platforms• Implementation guidelines for typicaldevices on server and workstationplatforms• Summary• Next steps2


Agenda• Impact of devices on platform power• Introduction to the power managementextensions – LTR and OBFF• Implementation guidelines for typicaldevices on mobile and desktop platforms• Implementation guidelines for typicaldevices on server and workstationplatforms• Summary• Next steps3


Platform Power Savings Opportunity• Usage Analysis: Typical Mobile Platform in S0 state is ~90% idle• Even when idle, platform components are kept in high power state to meet theservice latency requirements of devices– Increasing latency results in buffer overflows and failures for some devicesPlatform Power in Watts4035302520151050Average power scenario on running MM07(Office* Productivity suite)On an Intel ® Corei5 platform running Windows 7*0 10 20 30 40 50 60 70 80 90 100 110 120Time in MinutesIdle workload power(~8W – 10W)PMOpportunitySource: Intel CorporationOpportunity to reduce platform power for an idle workload5


Agenda• Impact of devices on platform power• Introduction to the PCI Express* powermanagement extensions – LTR and OBFF• Implementation guidelines for typicaldevices on mobile and desktop platforms• Implementation guidelines for typicaldevices on server and workstationplatforms• Summary• Next steps6


Power vs. Response Latency (Mobile)Platform Latency ---> increasing500msec ~10sec~100usecMaxCPU C0Max powerSystem Active State (S0)WorkloadLow Service Latencyrequirements duringactive workloads givesreliable performanceCPU CXIdleDevices andApplications haveFixed ServiceLatency expectationsfrom a platform in S0System Inactive State (Sx)High Service Latencyrequirements duringidle workloads givesmore PM opportunity8-10W 600mWPlatform Power Consumption ---> DecreasingVariable service latency indication from devices requiredfor aggressive, yet robust power managementS3ResponseLatency Penaltyincreases withlower powerstatesS4400mW7


Latency Tolerance Reporting (LTR)ActiveProcessorRootComplexLTR_Active_idleActive_IdlePCI Express* DeviceIdleLTR Mechanism• LTR message (TLP) sent bydevice dynamically as afunction of workload– Smaller values during activeworkloads– Larger value when idleLTR Benefits• Dynamic powerperformancetradeoffs• Robust power management– Platform enters lowerpower/longer latency statesonly when devices cantolerate it8


Impact of LTR on Platform Idle Power160%Power impact is higher since futureplatforms will have lower idle floorNear-term PlatformFuture Platforms% increase in Platform IdlePower140%120%100%80%60%40%20%0%When a device doesn’t support LTR,platform latency will be set to ~20usec20us 30us 60us 300us 500us 1000usData from power model for Client NotebookSource: Intel CorporationLTR ValuesLower Idle Power andIncreased Battery Life+This data is for illustration purposes only & actual data will be available as platforms become available+All products, dates, and figures specified are preliminary based on current expectations, and are subject to change without noticeCrucial that all devices support LTR for maximum power savings9


LTR - Device ImplementationOS Bus DriverConfig Regs(Add support for LTR)• Hardware driven LTR– When device latencyrequirements change frequently– For devices like Network deviceswhich asynchronously receivedata from networkPHYDataLinkLayerTransactionLayer(Add supportfor LTR TLP)PCI Express* BlockLTR Value• Software guided LTR– When device latencyrequirements change infrequently– For slave devices which executework items scheduled by software– May define an MMIO register indevice, a write to which wouldtrigger an LTR messageApplicationSelect the mechanism appropriate for your device10


Example: Active Ethernet NICLatency400usecVery LowPowerA new LTR value is in effect no later thanthe value sent in the previous LTRLowPowerHighPowerPlatform ComponentsLowPowerHighPowerLowPowerHighPowerLowPowerLatency400usecVery LowPowerLTRBus TransactionsLTR400us60us 60us 60us500usDevice BufferLTR ThresholdTimeout60usLTR=60usIdleIdleLTR=400usNetwork DataLTR _Active = 60usLTR_Active_Idle = 400usecTimeoutLatency guidance based on buffer size and utilization11


Optimized Buffer Flush/Fill (OBFF)OBFF MechanismDevice AInterrupt DMA• Indicates optimalwindows for busmastering and interruptactivityWAKE#SignalingPlatformDevice BInterrupt DMADevice C Interrupt DMA– Intel chipsets will driveWAKE# at the rootcomplex for OBFFPCIe*PCIe*PCIe*OS TickTimer InterruptOptimal WindowsA B C Traffic Pattern withno OBFF• Active Window – Platformfully active. Optimal for busmastering and interrupts• OBFF Window – Platformmemory path available formemory reads and writes• Idle Window – Platform isin low power stateIdleWinPower ManagementOpportunityActiveWinOBFFWinIdleWinTraffic Pattern withOBFFActiveWinIdleWinActiveWin12


Impact of OBFF on Platform Power70%BaselineOBFFUtilizationNear-term PlatformFuture Platforms% Deep Package C-stateresidency60%50%40%30%20%10%0%% decrease in PlatformPower0%-5%-10%-15%-20%-25%-30%5% 10% 15%5% 10% 15%-35%Utilization•Data from prototype in Intel® Xeon® Processor 5500 based server platform running Linux* 2.6.18•Source: Intel Corporation• Meaningful increase in deep package C-state residency for server platforms• For Client platforms, baseline C-state residency is high. OBFF givesadditional power savings of ~>= 200mW on DMA scenarios (network/diskfile transfers)– Still significant for battery operated mobile devices– Savings increase when idle floor is lower13Increase in platform low power state residency


Active State Power Management (ASPM)• Support ASPM on all devices– Power savings per link add up across the platform– L1 entry policy is device driven. Ensure you don’t re-enter L1 state whenwaiting for platform to come out of low power state• Support Dynamic Clock Control (CLKREQ#) on Mini-Card and ExpressCard form factors– “CLKREQ# asserted” to achieve fast exits between data bursts– “CLKREQ# de-asserted” when device is pervasively idle• Host reference clock savings (~60mW per clock) & device PLL savings (~100mWper device)• Recommended link exit Latencies– L0s: 256ns– L1:


Agenda• Impact of devices on platform power• Introduction to the power managementextensions – LTR and OBFF• Implementation guidelines for typicaldevices on mobile and desktop platforms• Implementation guidelines for typicaldevices on server and workstationplatforms• Summary• Next steps15


LTR Recommendation for Client DevicesDevices LTR_Active LTR_Act_Idle LTR_Idle CommentsWLAN 60usec 300usec(minimum)LTR_No_Req (unassociated)LTR_MaxPlatLat (associatedand radio off)Device InitiatedEthernet LAN(1Gb orlower)60usec300usec(minimum)LTR_MaxPlatLat (LPI mode)LPI – Low Power Idlemode in IEEE 802.3azstandardDevice InitiatedGraphics 60usec Optional LTR_MaxPlatLat Can be SW guidedClient Storage(e.g. memorycard reader)60usec Optional LTR_MaxPlatLat Can be SW guided+BIOS programs LTR Extended Capability Structure field with LTR_MaxPlatLat (1msec)+These numbers are preliminary. Monitor the following link for updates:http://developer.intel.com/technology/pciexpress/devnet/index.htmLTR value below 60usec will result in increased platform power• Request lower values only when necessary – for short durations16


Agenda• Impact of devices on platform power• Introduction to the power managementextensions – LTR and OBFF• Implementation guidelines for typicaldevices on mobile and desktop platforms• Implementation guidelines for typicaldevices on server and workstationplatforms• Summary• Next steps17


LTR Recommendation for Server DevicesDevices LTR_Active LTR_Act_Idle LTR_Idle CommentsEthernet LAN(1Gb orlower)60usec300usec(minimum)LTR_MaxPlatLat(LPI mode)Device Initiated≥10 Gb(Ethernet,FibreChannel,orInfiniBand)50usecOptional in 1 st genplatformsLTR_MaxPlatLat(LPI mode)Device InitiatedSATAControllerSASController50usec Optional LTR_MaxPlatLat Can be SW guided50usec Optional LTR_MaxPlatLat Can be SW guidedAny LTR value below 50usec will result in increased platform power• Request lower values only when performance is needed – for short durations• These numbers are preliminary. Monitor the following link for updates:http://developer.intel.com/technology/pciexpress/devnet/index.htm18


Use of Device Buffer WatermarksExample: Buffer Flushes for Receive Path on NIC• On-chip buffers must be flushed whenthe “high-water mark” (HWM) is hitto prevent over-runs– Defined down from the top of the buffer byat least LTR + the PCIe L1 exit latency• Depending on application, bufferslikely will be flushed based on varioustime-out situations– For example, preventing “stale” data• “Low-water marks” (LWM) arerecommended to coalesce data formore efficient bus usage– LWM effectively sets a minimum size for atransmission (to host) blockHWMLWMRx Bufferreceive data(from network)LTR + L1 Exit:flush to avoidoverrun19


Implementation Guidelines for OBFFExample: Buffer FlushOBFF State Behavior Device timers LWM HWMACTIVEOBFF(BUFFERED)IDLE• Normaloperation – senddata andinterrupts• Align deferrableinterrupts• Perform criticaltransactions asnecessary• Coalescedeferrable dataand interrupts• Perform criticaltransactions asnecessary• On transition toACTIVE, flush allbuffered data andinterrupts• Complete the flushbefore starting devicetimers and localbuffering• On timer expiry, flushbuffered data andinterrupts• Device exposes timertoggle capability bitto enable/disabletimers in OBFF IDLE(Details in whitepaper*)• Send dataonce LWM isreached• Send dataonce LWM isreached• NA• NA• NA• Details to follow in future whitepaper on Intel® Developer Network for PCI Express*Architecture @ http://developer.intel.com/technology/pciexpress/devnet/index.htm• Flush buffereddata and deliverpendinginterrupts onceHWM is reached20


Agenda• Impact of devices on platform power• Introduction to the power managementextensions – LTR and OBFF• Implementation guidelines for typicaldevices on mobile and desktop platforms• Implementation guidelines for typicaldevices on server and workstationplatforms• Summary• Next steps21


Summary• Impact of devices (even low power ones)on platform power is significant• The PCI Express* Power ManagementExtensions provide a framework forreducing the impact of devices on platformpower• Framework creates a cooperative powermanagement model and all devices in theecosystem must support the model formaximum impact• We have seen a lot of interest in thesepower management extensions and highlyencourage you to implement them– Opportunity for devices to differentiate and claimplatform power reductions22


Agenda• Impact of devices on platform power• Introduction to the power managementextensions – LTR and OBFF• Implementation guidelines for typicaldevices on mobile and desktop platforms• Implementation guidelines for typicaldevices on server and workstationplatforms• Summary• Next steps23


Next Steps• <strong>Download</strong> the PCI Express* 3.0 specfrom the PCI-SIG Website forreference on LTR and OBFF• IHVs:– Start architecting devices with a view towardsusing the Interconnect Bus extensions– Work with your OEMs/ODMs to understandrequirement and timeline– Contact Intel representative to get the enablingtools and collateral24


Additional Sources of Informationon This Topic• Other sessions:– PCIS001: PCI Express* 3.0 Technology: Logical PHYConsiderations for Intel® Platforms– PCIS003: PCI Express* 3.0 Technology: Enabling Tools andUpdates to the PIPE 3.0 Specification– EBLS001: Interconnect Bus Extensions for Energy-EfficientPlatforms– PCIQ001: PCI Express* 3.0 Q&A• More Web-based info:– http://www.pci-sig.org– Intel® Developer Network for PCI Express* Architecture• http://developer.intel.com/technology/pciexpress/devnet/index.htm– ‘Energy-efficient platform devices’ whitepaper• http://www.intel.com/technology/mobility/notebooks.htm25


Legal Disclaimer• INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS.NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUALPROPETY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMSAND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITYWHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TOSALE AND/OR USE OF INTEL ® PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TOFITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT,COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.• Intel may make changes to specifications and product descriptions at any time, without notice.• All products, dates, and figures specified are preliminary based on current expectations, and aresubject to change without notice.• Intel, processors, chipsets, and desktop boards may contain design defects or errors known aserrata, which may cause the product to deviate from published specifications. Currentcharacterized errata are available on request.• Code names featured are used internally within Intel to identify products that are indevelopment and not yet publicly announced for release. Customers, licensees and other thirdparties are not authorized by Intel to use code names in advertising, promotion or marketing ofany product or services and any such use of Intel's internal code names is at the sole risk of theuser• Performance tests and ratings are measured using specific computer systems and/orcomponents and reflect the approximate performance of Intel products as measured by thosetests. Any difference in system hardware or software design or configuration may affect actualperformance.• Intel, Core, Intel Sponsors of Tomorrow. and Intel Sponsors of Tomorrow. logo and the Intellogo are trademarks of Intel Corporation in the United States and other countries.• *Other names and brands may be claimed as the property of others.• Copyright ©2010 Intel Corporation.26


Risk FactorsThe above statements and any others in this document that refer to plans and expectations for the second quarter, the year and thefuture are forward-looking statements that involve a number of risks and uncertainties. Many factors could affect Intel’s actualresults, and variances from Intel’s current expectations regarding such factors could cause actual results to differ materially fromthose expressed in these forward-looking statements. Intel presently considers the following to be the important factors that couldcause actual results to differ materially from the corporation’s expectations. Demand could be different from Intel's expectations dueto factors including changes in business and economic conditions; customer acceptance of Intel’s and competitors’ products; changesin customer order patterns including order cancellations; and changes in the level of inventory at customers. Intel operates inintensely competitive industries that are characterized by a high percentage of costs that are fixed or difficult to reduce in the shortterm and product demand that is highly variable and difficult to forecast. Additionally, Intel is in the process of transitioning to itsnext generation of products on 32nm process technology, and there could be execution issues associated with these changes,including product defects and errata along with lower than anticipated manufacturing yields. Revenue and the gross marginpercentage are affected by the timing of new Intel product introductions and the demand for and market acceptance of Intel'sproducts; actions taken by Intel's competitors, including product offerings and introductions, marketing programs and pricingpressures and Intel’s response to such actions; defects or disruptions in the supply of materials or resources; and Intel’s ability torespond quickly to technological developments and to incorporate new features into its products. The gross margin percentage couldvary significantly from expectations based on changes in revenue levels; product mix and pricing; start-up costs, including costsassociated with the new 32nm process technology; variations in inventory valuation, including variations related to the timing ofqualifying products for sale; excess or obsolete inventory; manufacturing yields; changes in unit costs; impairments of long-livedassets, including manufacturing, assembly/test and intangible assets; the timing and execution of the manufacturing ramp andassociated costs; and capacity utilization. Expenses, particularly certain marketing and compensation expenses, as well asrestructuring and asset impairment charges, vary depending on the level of demand for Intel's products and the level of revenue andprofits. The majority of our non-marketable equity investment portfolio balance is concentrated in the flash memory market segment,and declines in this market segment or changes in management’s plans with respect to our investment in this market segment couldresult in significant impairment charges, impacting restructuring charges as well as gains/losses on equity investments and interestand other. Intel's results could be impacted by adverse economic, social, political and physical/infrastructure conditions in countrieswhere Intel, its customers or its suppliers operate, including military conflict and other security risks, natural disasters, infrastructuredisruptions, health concerns and fluctuations in currency exchange rates. Intel’s results could be affected by the timing of closing ofacquisitions and divestitures. Intel's results could be affected by adverse effects associated with product defects and errata(deviations from published specifications), and by litigation or regulatory matters involving intellectual property, stockholder,consumer, antitrust and other issues, such as the litigation and regulatory matters described in Intel's SEC reports. An unfavorableruling could include monetary damages or an injunction prohibiting us from manufacturing or selling one or more products,precluding particular business practices, impacting our ability to design our products, or requiring other remedies such as compulsorylicensing of intellectual property. A detailed discussion of these and other factors that could affect Intel’s results is included in Intel’sSEC filings, including the report on Form 10-Q for the quarter ended March 27, 2010.Rev. 5/7/1027


28Backup Slides


LTR Semantics for Reads and WritesLTR = 100usecEPLTR = 100usecRCEPRC≤100us5us≤100us≤100us29ReadsWrites• Latency values are applicable only to leadoff cycles– Defined as the first memory transaction of potentially multiple memory transactionsthat will occur in quick (


Example: WLAN DeviceLTR_Active_IdleLTR_Active LTR_Idle LTR_ActiveClient AwakeClient DozingBeacon with TIM Data PS-Poll ACKLatency information with Wi-Fi Power SaveUse of device PM states to give Latency guidance30


Device Buffering and OBFF1008060402006.211 6.212 6.213 6.214 6.215 6.216 6.217 6.218 6.219 6.22 6.221Bytes120100806040200Bytes1206.211 6.2111 6.2112 6.2113 6.2114 6.2115 6.2116 6.2117EP Initiated Traffic RC Initiated Traffic INTA AssertedTimestamp (seconds)• Trace shows ATSC receiverflushing data to hostmemory every ~300usec• Data is consumed by hostprocessor every ~10msec(Interrupt)• At ~20mbps, need only~2.5KB of memory for1msec buffering. Will havepositive impact on power• Implement sufficient device buffering to maximize energyefficiency– Will reduce frequent host memory accesses and allow for OBFF activity alignment– Allow for a minimum of ~300usec of inactivity between bursts. Recommend ~1msec forgreater energy efficiency when performance permits• Classify device-initiated transactions: critical vs. deferrable– Perform critical transactions as necessary– Align deferrable transactions to platform activity• No deferrable accesses in Idle Window• Memory accesses in OBFF Window• Interrupts and Memory accesses in Active WindowSource: Intel Corporation31

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