SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA8 Debug architectureD R A FTSuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0
PRELIMINARY DATASystemorganization2.1 IntroductionD R A FT2The SH-5 system architecture is modular. An SH-5 implementation consists of anumber of modules which communicate using one or more interconnects. Theinterconnect to which the CPU core is connected provides the main path to externalmemory. This interconnect provides a memory-mapped packet routing mechanismbetween modules. It is known as the SuperHyway and forms the backplane of highlyintegrated systems which use the SH-5. The SuperHyway specifies a protocol whichdefines how packets are represented and propagated. The name SuperHyway isgiven to the family of implementations of this protocol on SH-5 chips.A typical SH-5 implementation is a single chip which contains one or more CPUcores, one or more product-specific SH-5 modules, an interconnect, a peripheralsubsystem, an external memory interface and a module dedicated to supportingdebug of the core and system.2.2 SuperHyway architectureThe SuperHyway architecture provides the ‘glue’ that binds together a set of SH-5modules. A connection between the SuperHyway and an SH-5 module is called aport (sometimes referred to as a p-port). A SuperHyway port supports abi-directional flow of packets between the interconnect and an SH-5 module.The distinction between the SuperHyway architecture and implementation isimportant. This section, SuperHyway architecture, defines the abstractions that areused to build implementations containing a SuperHyway interconnect. Thearchitecture includes an abstract view of the packets, the SuperHyway, the port, aSH-5 module and the protocol.05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System
Page 1 and 2: PRELIMINARY DATASuperH TM (SH)64-Bi
Page 3 and 4: PRELIMINARY DATAContentsPrefacexi1
Page 5 and 6: PRELIMINARY DATAv3 SH-5 CPU 533.1 I
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PRELIMINARY DATAOperation 654.3 Ope
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PRELIMINARY DATAOperation 67In the
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PRELIMINARY DATAOperation 69On-Chip
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PRELIMINARY DATAFunctionality 955.2
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PRELIMINARY DATAOperation 99Ports 5
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PRELIMINARY DATAOperation 105PERIPH
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PRELIMINARY DATAInterruptcontroller
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PRELIMINARY DATAFeatures 1096.1.2 P
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PRELIMINARY DATAInterrupt sources 1
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PRELIMINARY DATAOverview 1397.1.3 P
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PRELIMINARY DATAOperation 167flag s
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PRELIMINARY DATAInterrupts 1697.4 I
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PRELIMINARY DATATimer unit(TMU)8.1
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PRELIMINARY DATAOverview 1738.1.3 P
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PRELIMINARY DATAOperation 1873 When
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PRELIMINARY DATAInterrupts 1918.4 I
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PRELIMINARY DATASerial commsinterfa
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PRELIMINARY DATAOverview 1959.1.2 B
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PRELIMINARY DATAOperation 241Bit 0
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PRELIMINARY DATAOperation 243SCIF.S
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PRELIMINARY DATAOperation 245ClockE
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PRELIMINARY DATAOperation 247Serial
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PRELIMINARY DATAOperation 2491Seria
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PRELIMINARY DATAOperation 251NoNoNo
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PRELIMINARY DATAPower down 255Inter
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PRELIMINARY DATAUsage notes 257Send
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PRELIMINARY DATAClock, powerand res
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PRELIMINARY DATAWatchdog timer 2791
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PRELIMINARY DATAWatchdog timer 281C
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PRELIMINARY DATAWatchdog timer 283C
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PRELIMINARY DATAWatchdog timer 285N
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PRELIMINARY DATADebug and power man
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PRELIMINARY DATAReset controller 31
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PRELIMINARY DATAIndexAAddress 1-2,
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PRELIMINARY DATA325Endian 43, 58Bi-
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PRELIMINARY DATA327Physical memory
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PRELIMINARY DATA329StoreWord 30, 61
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