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  • Page 4: Introduction to Delay Testing教
  • Page 7 and 8: Problems of Delay Testing(Cont.)Hig
  • Page 9 and 10: The Current ApproachFunctional test
  • Page 11 and 12: Test Application SchemesHow to appl
  • Page 13 and 14: Test Scheme for SequentialCircuitsT
  • Page 15 and 16: Standard Scan TestingAll v1 and onl
  • Page 17 and 18: Slow-fastfast-slow slow Clock Testi
  • Page 19 and 20: At-speed TestingThe fault is initia
  • Page 21 and 22: Example of Variable DelayLogic21
  • Page 23 and 24: Non-Scan designs with latchedPI/PO
  • Page 25 and 26: Example: k=325
  • Page 27 and 28: Delay Fault ModelsAssumption- A “
  • Page 29 and 30: Transition Fault Model (Cont.)Two t
  • Page 31 and 32: Gate Delay FaultLong paths through
  • Page 33 and 34: Path Delay FaultAny path in a circu
  • Page 35 and 36: Path Delay Fault StrategiesSelect a
  • Page 37 and 38: Case Studies教 育 部 顧 問 室
  • Page 39 and 40: Case Study 1 (Cont.)Clock=120ns39
  • Page 41 and 42: Case Study 2 (Cont.)Maxwell (HP, 19
  • Page 43 and 44: Case Study 2 (Cont.)Path delay faul
  • Page 45 and 46: Case Study 3 (Cont.)45
  • Page 47 and 48: IntroductionPaths are classified ac
  • Page 49 and 50: ClassificationPath sensitization- S
  • Page 51 and 52: TerminologyControlling value (cv(cv
  • Page 53 and 54:

    Single-pathSensitizable PathDelay F

  • Page 55 and 56:

    Example of Robust TestablePath Dela

  • Page 57 and 58:

    Detailed Illustration of RobustCase

  • Page 59 and 60:

    Non-robust Testable Path DelayFault

  • Page 61 and 62:

    Case 1 both input hasdelay faultDet

  • Page 63 and 64:

    Characteristics of Non-robustTests

  • Page 65 and 66:

    Example: Validatable Non-robustPath

  • Page 67 and 68:

    Example of FunctionalSensitizable P

  • Page 69 and 70:

    FS Sensitization CharacteristicsA F

  • Page 71 and 72:

    Functional (performance)redundant p

  • Page 73 and 74:

    Example: Functional redundantpaths

  • Page 75 and 76:

    Minimum Set of To-bebe-testedFaults

  • Page 77 and 78:

    CriterionFunctional Unsensitizable

  • Page 79 and 80:

    Functional Unsensitizable PathExamp

  • Page 81 and 82:

    Functional Unsensitizable Pathsand

  • Page 83 and 84:

    Identifying FunctionalUnsensitizabl

  • Page 85 and 86:

    Robust Dependent PathsLet D be the

  • Page 87 and 88:

    Identification of RD SetsTheorem- C

  • Page 89 and 90:

    Approx. Theorem forIdentification o

  • Page 91 and 92:

    Input Sort HeuristicCombines the tw

  • Page 93 and 94:

    Singly-testable Path DelayFaultsGha

  • Page 95 and 96:

    Terminologies of Multiple PathDelay

  • Page 97 and 98:

    Example: Multiple Path DelayFaultsA

  • Page 99 and 100:

    The cardinality of a primitivefault

  • Page 101 and 102:

    Example: Primitive Faults (II)Π2={

  • Page 103 and 104:

    Classification for SequentialSequen

  • Page 105 and 106:

    Example circuit of PDFC105

  • Page 107 and 108:

    Example of untestable PDFC_S (2/2)A

  • Page 109 and 110:

    Unexcitable andUnpropagatable109

  • Page 111 and 112:

    Delay Effects of PhysicalDefects an

  • Page 113 and 114:

    DSM Technology Trends (2)109Wire le

  • Page 115 and 116:

    DSM Technology Trends (4)6Supply Vo

  • Page 117 and 118:

    Test Issues of a ComplexSOC教 育

  • Page 119 and 120:

    Mixing of immature IP coresIPs from

  • Page 121 and 122:

    Unexpected Physical Effects教 育

  • Page 123 and 124:

    An Example of Effects fromNeighbori

  • Page 125 and 126:

    Resistive Defect ExampleWaveform sh

  • Page 127 and 128:

    Multiple Sources of NoiseEffects127

  • Page 129 and 130:

    Power Supply Noise------a a RealPow

  • Page 131 and 132:

    Sources of Power Supply NoiseLDI/Dt

  • Page 133 and 134:

    Ineffective Iddq TestingIddq testin

  • Page 135 and 136:

    Burn-In TestingOccurrence of potent

  • Page 137 and 138:

    Temperature VariabilityAs dietemper

  • Page 139 and 140:

    Thermal Issues During TestingTherma

  • Page 141 and 142:

    A New Delay TestingFramework教 育

  • Page 143 and 144:

    DSM Noise and Defect EffectsDSM tec

  • Page 145 and 146:

    OverviewTest evaluation/generationS

  • Page 147 and 148:

    Statistical Timing Analysis Framewo

  • Page 149 and 150:

    Path Selection To Consider Supply N

  • Page 151 and 152:

    Statistical Timing AnalysisStatisti

  • Page 153 and 154:

    Applications of the FrameworkSystem

  • Page 155 and 156:

    Monte Carlo SimulationStartMultiple

  • Page 157 and 158:

    Validation of FrameworkComparing re

  • Page 159 and 160:

    Analysis Results of S344 for thePat

  • Page 161 and 162:

    Static Analysis of S38584Statistica

  • Page 163 and 164:

    Need for New Path Selection Method

  • Page 165 and 166:

    Critical Path Definition UnderStati

  • Page 167 and 168:

    PathPath Search Strategy ExamplePro

  • Page 169 and 170:

    Vector Generation for Causing HighP

  • Page 171 and 172:

    S1After Phase II: Test Pattern Caus

  • Page 173 and 174:

    Path Selection Strategies and Patte

  • Page 175 and 176:

    Number of Paths Selected by Differe

  • Page 177 and 178:

    Maximum Circuit Delays of S9234 ofD

  • Page 179 and 180:

    Statistical Timing AnalysisFramewor

  • Page 181 and 182:

    PurposeDevelop an efficient and sca

  • Page 183 and 184:

    Delay Testing for Crosstalk Induced

  • Page 185 and 186:

    Performance Sensitivity Analysis wr

  • Page 187 and 188:

    An ExampleTarget fault:• path P +

  • Page 189 and 190:

    After Phase II:An Example (Cont.)Fu

  • Page 191 and 192:

    SummaryDSM technologies lead to inc

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