MEMORY DATABOOK - Index of

MEMORYDATABOOK1986

0IC MEMORY UNE-UP ANDMEMORYTYPICAL CHARACTERISTICSDATABOOK1986 nPACKAGINGRELIABILITY INFORMATIONMOSMEMORYHANDLING PRECAUTIONSEPROM WRITINGAND ERASUREMASK ROM CUSTOMERPROGRAM SPECIFICATIONSMASK ROMDEVELOPMENT FLOWCHARTTERMINOLOGYAND SYMBOLSDATA SHEETD0IIn0nnCROSS REFERENCE LIST [[!]APPLICATIONSDI

CONTENTSo IC MEMORY LINE-UP AND TYPICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3• DYNAMIC RAMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5• SIP/SIMM MODULE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6• NMOS STATIC RAMS ............................................................ 7• CMOS STATIC RAMS ............................................................ 7• MASK ROMS .................................................................... 8• EPROMS .. ....... ... ......... ... .... ........... ...... ....... .... ..... .... ... .... 9• E2PROMS ......................................................... ,............. 9D PACKAGING .......................................................................... 13• 16 PIN PLASTIC ................................................................. 15• 16 PIN STACK PLASTIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 16• 18 PIN PLCC .................................................................... 16• 18 PIN PLASTiC ................................................................. 17• 18 PIN SIDE-BRAZED ............................................................ 17• 22 PIN PLCC .................................................................... 18• 22 PIN PLASTIC ................................................................. 18• 24 PIN PLASTIC ................................................................. 19• 24 PIN CERDIP .................................................................. 19• 24 PIN PLASTIC FLAT ............................................................ 20• 26 PIN SOJ ...................................................................... 20• 28 PIN PLASTIC ................................................................. 21• 28 PIN CERDIP .................................................................. 21• 32 PIN PLCC .................................................................... 22• 40 PIN SIDE-BRAZED ............................................................ 22.. RELIABILITY INFORMATION .......................................................... 251. INTRODUCTION ................................................................. 252. QUALITY ASSURANCE SYSTEM AND UNDERLYING CONCEPTS ......... ,........ 253. EXAMPLE OF RELIABILITY TEST RESULTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 274. SEMICONDUCTOR MEMORY FAILURES ................................. , . . . . . . .. 31D MOS MEMORY HANDLING PRECAUTIONS ................................... ,........ 351. STATIC ELECTRICITY COUNTERMEASURES ............................ ,.. . . . ... 352. POWER SUPPLY AND INPUT SIGNAL NOISE ............................. , . . . . . . .. 353. CMOS MEMORY OPERATING PRECAUTIONS ........................... ,........ 35IDI EPROM WRITING AND ERASURE ...................................................... 391. EPROM WRITING ERASURE ..................................................... 392. EPROM HANDLING .............................................................. 40III MASK ROM CUSTOMER PROGRAM SPECIFICATIONS ................................ 431. USABLE MEDIA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 432. MAGNETIC TAPE SPECiFiCATIONS....................... .. ........... .... . . .... 433. EPROM SPECiFiCATiONS ........................................................ 4411.1 MASK ROM DEVELOPMENT FLOWCHART........................ ........... .... . . .... 47

D TERMINOLOGY AND SYMBOLS ....................................................... 511. PIN TERMINOLOGY ............................................................. 512. ABSOLUTE MAXIMUM RATINGS ................................................. 523. RECOMMENDED OPERATION CONDITIONS.. .. . . . . . . .. .. . . .... . . . . .. . . . .. . .. . . .. 534. DC CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 545. AC CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 55D DATASHEET• MOS DYNAMIC RAMSMSM 3732AS/RS 32,768-Word x 1-Bit RAM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . .. 60MSM3764AS/RS 65,536-Word x 1-Bit RAM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . .. 76MSM3764AASI ARS 65,536-Word x 1-Bit RAM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . .. 92MSM41256AS/RS 262,144-Word x 1-Bit RAM (NMOS) < Page Mode> .......... 108MSM41256JS 262,144-Word x 1-Bit RAM (NMOS) < Page Mode> .......... 122MSM41256AAS/RS 262,144-Word x 1-Bit RAM (NMOS) < Page Mode> .......... 132MSM41257AAS/RS 262,144-Word x 1-Bit RAM (NMOS) ......... 147MSM41464RS 65,536-Word x 4-Bit RAM (NMOS) ........................... 163MSM414256RSMSM411000RSMSM411 001 RSMSM511000RSMSM511 001 RSMSM514256RS262,144-Word x 4-Bit RAM (NMOS) ......................... 1781,048,576-Word x 1-Bit RAM (NMOS) ....................... 1911,048,576-Word x 1-Bit RAM (NMOS) ....... 2041,048,576-Word x 1-Bit RAM (NMOS) ......... 2171,048,576-Word x 1-Bit RAM (NMOS) ...... 218262,144-Word x 4-Bit RAM (CMOS) ........... 219MSM514257RS 262,144-Word x 4-Bit RAM (CMOS) ....... 220MSM37S64ARS/37S64RS 131,072-Word x 4-Bit RAM (NMOS) .................. 221MSC2301 YS9/KS9 65,536-Word x 9-Bit RAM (NMOS) ........................... 234MSC2304 YS8/KS8 262,144-Word x 8-Bit RAM (NMOS) ......................... 245MSC2304 YS9/KS9 262,144-Word x 9-Bit RAM (NMOS) .....................•... 256• MOSSTATICRAMSMSM5114RS 4,096-Word x 4-Bit RAM (CMOS) ............................ 268MSM2128RS 2,048-Word x 8-Bit RAM (NMOS) ............................ 273MSM5128RS 2,048-Word x 8-Bit RAM (CMOS) ............................ 278MSM5128-20GSK 2,048-Word x 8-Bit RAM (CMOS) ............................ 283MSM5126RS 2,048-Word x 8-Bit RAM (CMOS) ............................ 289MSM5165RS/JS 8,192-Word x 8-Bit RAM (CMOS) ............................ 294MSM5165LRS/JS 8,192-Word x 8-Bit RAM (CMOS) ............................ 300MSM5188US 16,384-Word x 4-Bit RAM (CMOS) ........................... 307MSM5127RSJJS 32,768-Word x 8-Bit RAM (CMOS) ........................... 312MSM51257LRS/JS 32,768-Word x 8-Bit RAM (CMOS) ........................... 318• MOS MASK ROMSMSM3864RS 8, 192-Word x 8-Bit MASK ROM (NMOS) ..................... 326MSM38128ARS 16,384-Word x 8-Bit MASK ROM (NMOS) .................... 330MSM38256RS 32,768-Word x 8-Bit MASK ROM (NMOS) .................... 334MSM38256ARS 32,768-Word x 8-Bit MASK ROM (NMOS) .................... 338MSM38512RS 65,536-Word x 8-Bit MASK ROM (NMOS) .................... 342MSM28101AAS 1 M Bit MASK ROM (NMOS) .................................. 346ii

MSM28201 AASMSM53256RSMSK531000RS• MOSEPROMS1 M Bit MASK ROM (NMOS) .................................. 35132,768-Word X 8-Bit MASK ROM (CMOS) .................... 356131,072-Word X 8-Bit MASK ROM (CMOS) .................. 360MSM2764AS 8,192-Word X 8-Bit EPROM (NMOS) ......................... 366MSM27128AS 16,384-Word X 8-Bit EPROM (NMOS) ........................ 372MSM27256AS 32,768-Word X 8-Bit EPROM (NMOS) ........................ 378MSM27512AS 65,536-Word X 8-Bit EPROM (NMOS) ........................ 384MSM271000AS 131,072-Word X 8-Bit EPROM (NMOS) ...................... 389MSM271024AS 65,536-Word X 16-Bit EPROM (NMOS) ...................... 395MSM27C64AS 8,192-Word X 8-Bit EPROM (CMOS) ......................... 401MSM27C128AS 16,384-Word X 8-Bit EPROM (CMOS) ........................ 407MSM27C1024AS 65,536-Word X 16-Bit EPROM (CMOS) ...................... 413• MOS E2 PROMSMSM2816ARS 2,048-Word X 8-Bit E2 PROM ................................ 420II!] CROSS REFERENCE LIST1. DYNAMIC RAM ................................... ; .............................. 4312. STATIC RAM .................................................................... 4363. MASK ROM ...................................................................... 4384. EPROM ......................................................................... 4395. E2P ROM ........................................................................ 441m APPLICATIONS64KBIT DYNAMIC RAM APPLICATIONS NOTES ........................................ 4451. MEMORY DRIVER ............................................................... 4452. DECOUPLING CAPACITORS ..................................................... 4463. PRINTED CIRCUIT BOARD ....................................................... 4464. PERIPHERAL CONTROL CiRCUiT ................................................ 4475. NOTES ON MOUNTING 1 MB MEMORY ON A BOARD .............................. 4486. MEMORY SYSTEM RELIABILITY ................................................. 4497. MEMORY COMPARISON STANDARD ............................................. 451CMOS RAM BATTERY BACK-UP ........................................................ 4541. SYSTEM POWER AND BATTERY SWITCHING CIRCUIT ........................... 4542. SWITCHING CIRCUIT MODIFiCATIONS ........................................... 4543. DATA RETENTION MODE ........................................................ 4564. INTERFACING ................................................................... 4575. MISCELLANEOUS ............................................................... 457MASK ROM KANJI GENERATION MEMORY DESCRIPTION .............................. 4571. KANJI GENERATION MEMORIES ................................................. 4582. MSM38256 SERIES ............................................................... 459iii

DD IC MEMORY LINE-UP AND TYPICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . .. . . 3• DYNAMIC RAMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . 5• SIP/SIMM MODULE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6• NMOS STATIC RAMS....................................................... 7• CMOS STATIC RAMS....................................................... 7• MASK ROMS ............................................................... 8• EPROMS .......... ...................................... .............. ..... 9• PPROMS .... ............ ......................... ........................ 9

D.IC MEMORY LINE-UP AND TYPICAL CHARACTERISTICS .1--------* Under development4

---------.IC MEMORY LINE-UP AND TYPICAL CHARACTERISTICS.• DYNAMIC RAMSMem·oryModel NameCapac·ityPowerNum·Consump·ber ofMemoryAccess Cycle tion PowerPinsCircuit Function Configura· Time Time MAXperSupply EquivalenttionMAX MIN (mw) Voltage DevicePack·(ns) (ns) Operating/ (V)ageStandbyDMSM3732H·15150 270 248/2816 Pin Dynamic32k32,768x1 16 +5A7 (Column)=HMSM3732H·20 200 330 248/28MSM3732L·15150 270 248/2816 Pin Dynamic32kA7 (Column)=L32,768x1 16 +5MSM3732L·20 200 330 248/28MSM3764·15 150 270 248/28 TMS4164·1564k 16 Pin Dynamic 65,536x1 16 +5MSM3764·20 200 330 248/28 TMS4164·20MSM3764A·12 120 230 330/28MSM3764A·15 64k 16 Pin Dynamic 65,536x1 16 150 260 330/28 +5MSM3764A·20 200 330 330/28MSM41256·15 150 260 385/28256k 16 Pin Dynamic 262,144x1 16 +5MSM41256·20 200 330 385/28MSM41256A·10 100 200 385/28MSM41256A·12 250k 16 Pin Dynamic 262,144x1 16 120 220 385/28 +5MSM41256A·15 150 260 385/28MSM41257A·10 100 200 385/28MSM41257A·12 256k 16 Pin Dynamic 262,144x1 16 120 220 385/28 +5MSM41257A·15 150 260 385/28MSM41464·10 100 200 385/28MSM41464·12 256k 18 Pin Dynamic 65,536x4 18 120 230 385/28 +5MSM41464·15 150 260 385/28MSM414256·10 100 200 413/28256k 20 Pin Dynamic 262,144x4 20 +5MSM414256·12 120 230 385/28MSM411000·10 100 200 413/281M 18 Pin Dynamic 1,048,576x1 18 +5MSM411000·12 120 230 385/28MSM411001·10 100 200 413/281M 18 Pin Dynamic 1,048,576x1 18 +5MSM411001·12 120 230 385/28MSM511000·10 100 190 385/111M 18 Pin Dynamic 1,048,576x1 18 +5MSM511000·12 120 220 330/11MSM511001·10 100 190 385/111M 18 Pin Dynamic 1,048,576x1 18 +5MSM511001·12 120 220 330/11MSM514256·10 100 190 413/111M 20 Pin Dynamic 262,144x4 20 +5MSM514256·12 120 220 385/115

o.ICMEMORY LINE-UP AND TYPICAL CHARACTERISTICS •• --------PowerConsump-Access Cycle tion PowerTime Time MAX Supply EquivalentMAX MIN (mw) Voltage Device(ns) (ns) Operatingl (V)StandbyMemoryModel NameCapacityNumberofMemoryPinsCircuit Function ConfigurapertionPackageMSM514257-10 100 190 413/111M 20 Pin Dynamic 262.144x4 20 +5MSM514257-12 120 220 385111MSM37S64-15 150 270 360/55128k 16 Pin Dynamic 131,072xl 16 +5MSM37S64-20 200 330 360/55• SIP/SIMM MODULEMSC2301- 120 120 -12YS9/KS930 Pin Socket576k65536x9 30 +5MSC2301- Insertable Module -150 15015YS9/KS9PowerNum-Consump-Mem- ber of Access Cycle tion Powerory Memory Pins Time Time MAX Supply EquivalentModel Name Capac- Circuit Function Configura- per MAX MIN (nw) Voltage Deviceity tion Pack- (ns) (ns) Operatingl (V)ageStandbyMSC2304-120 120 -12YS8/KS830 Pin Socket2M262144x8 30 +5MSC2304- Insertable Module-150 15015YS8/KS8MSC2304-120 120 -12YS9/KS930 Pin Socket2M 262144x9 30MSC2304- Insertable Module -150 15015YS9/KS9+56

---------I.IC MEMORY LINE-UP AND TYPICAL CHARACTERISTICS.• NMOS STATIC RAMSModel NamePowerConsump-Access Cycle tion PowerTime Time MAX Supply EquivalentMAX MIN (mw) Voltage(ns) (ns) Operating/ (V)DeviceStandbyMemoryCapac-ityNumberofMemory PinsCircuit Function Configura- pertion PackageDMSM2128-12 120 120 660/110MSM2185,15MSM2128-2016kStatic, Common I/O 2048x8 24 150 150TMM2016with Power Down550/110 +5M58725Mode200 200 550/110• CMOS STATIC RAMSModel NamePowerNum-ConsumpberofMemoryPinsAccess Cycle tion PowerConfiguraperTime Time MAX Supply EquivalenttionMAX MIN (mw)Pack-Voltage Device(ns) (ns) Operating/ (V)ageStandbyMemoryCapac-ityCircuit FunctionMSM5114-2 200 200 192/0.04MSM5114-3 4kFully Static,Common I/O1024x4 18 300 300 192/0.04 +5MSM5114 450 450 192/0.04MSM5128-12 120 120 330/0.275MSM5128-15 16kFully Static,Common I/O2048x8 24 150 150 300/0.275 +5MSM5128-20 200 200 275/0.275TC5514!,PD444HM6116).IPD446TC5517MSM5126-20 150 150 385/0.165Fully Static 2048x8 24 +5MSM5126-25 16k Common I/O 200 200 385/0.165MSM5165-12 120 120 248/5.5Fully StaticMSM5165-15 64k Common I/O 8192x8 28 150 150 248/5.5 +5MSM5165-20 200 200 248/5.5MSM5165L-12 120 120 248/0.55MSM5165L-1564kFully StaticCommon 1108192x8 28 150 150 248/0.55 +5MSM5165L-20 200 200 248/0.55MSM5188-45 45 45 605/11MSM5188-5564kFully StaticCommon I/O16384x4 22 55 55 605/11 +5MSM5188-70 70 70 605/11MSM51257-85 85 85 385/5.5MSM51257-100 256kFully StaticCommon I/O32768x8 28 100 100 385/5.5 +5MSM51257-120 120 120 385/5.5MSM51257L-85MSM51257L-l00 256kFully StaticCommon I/O85 85385/0.5532768x8 28 100 100 385/0.55 +5MSM51257L-120 120 120 385/0.557

o.ICMEMORY LINE-UP AND TYPICAL CHARACTERISTICS ...--------• MASK ROMSPowerNum·Mem· berofConsump·Access CycleoryMemorytionModel NamePins TimeCircuit Function Configura·TimeCapac·perMAXMAX MINtion(mw)ity Pack· (ns) (ns)ageOperating/StandbyPowerSupplyVoltage(V)EquivalentDevice.MSM3864 64k Fully Static 8192x8 28 250 250 550/165 +5MSM38128A 128k Fully Static 16384x8 . 28 250 250 550/165 +5MSM38256 256k Fully Static 32768x8 28 250 250 660/165 +5MSM38256A 256k Fully Static 32768x8 28 150 150 330/33 +5MSM38512 512k Fully Static 65536x8 28 200 200 - +5MSM28101MSM282011MJIS·Chinese·charactercoding sys-40 Pin MASK RAM tern 0-7,18x16 Chinese·cha-16-473760x16racter font output40 10j.ls 22j.1sx 18893 +5JIS·Chinesecharactercoding sys·. tern 48-87MSM53256 256k Fully Static 32768x8 28 150 150 83/0.6 +5MSM531000 1M Fully Static 131072x8 28 250 250 83/0.6 +58

----------_IC MEMORY LINE-UP AND TYPICAL CHARACTERISTICS _• EPROMSoMem·Model Name ory Circuit FunctionCapac·ityNum·ber ofMemory Pins Access CycleConfigura· per Time Timetion Pack· MAX MINage (ns) (ns)PowerConsump·tionMAX(mw)Operating/StandbyPowerSupplyVoltage(V)EquivalentDeviceMSM2764 64k 28 Pin EPROM 8192x8 28 200 200 790/185 +5 2764MSM27128 128k 28 Pin EPROM 16,384x8 28 250 250 788/184 +5 27128MSM27256 256k 28 Pin EPROM 32,768x8 28 150 150 525/184 +5 27256MSM27512 512k 28 Pin EPROM 65,536x8 28 150 150 525/184 +5 27512MSM271000 1M 32 Pin EPROM 131,072x8 32 120 120 525/184 +5 271000MSM271024 1M 40 Pin EPROM 65,536x16 40 120 120 525/184 +5 271024MSM27C64 64k 28 Pin EPROM 8,192x8 28 200 200 165/0.55 +5 27C64MSM27C128 128k 28 Pin EPROM 16,384x8 28 200 200 165/0.55 +5 27C128MSM27Cl024 1M 40 Pin EPROM 65,536x16 40 100 100 175/0.55 +5 27Cl024• PP ROMSPowerNum·Consump·Mem· ber of Access Cycle tion Powerory Memory Pins Time Time MAX Supply EquivalentModel Name Capac· Circuit Function Configura· per MAX MIN (nw) Voltage Deviceity tion Pack· (ns) (ns) Operating/ (V)ageStandbyMSM2816A·25 250 250 -MSM2816A·3024 Pin 300 300 -16k2048x8 24MSM2816A·35E'P ROM350 350 -MSM2816A·45 450 450 -+5+59

D PACKAGING ..................................................................... 13• 16 PIN PLASTIC ............................................................ 15• 16 PIN STACK PLASTIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 16• 18 PIN PLCC ............................................................... 16• 18 PIN PLASTIC ............................................................ 17• 18 PIN SIDE-BRAZED ....................................................... 17• 22 PIN PLCC ............................................................... 18• 22 PIN PLASTIC ............................................................ 18• 24 PIN PLASTIC ............................................................ 19• 24 PIN CERDIP ............................................................. 19• 24 PIN PLASTIC FLAT... .. . .. ........ . .. ..... . . . ... . . ......... .. . ........... 20• 26 PIN SOJ ...................... .' .......................................... 20• 28 PIN PLASTIC ............................................................ 21• 28 PIN CERDIP ............................................................. 21• 32 PIN PLCC ............................................................... 22• 40 PIN SIDE-BRAZED ....................................................... 22

PACKAGINGPACKAGESNo. RS GS JS US YS KS ASName of PLASTIC PLASTIC PLASTIC PLASTIC MODULE MODULE SIDE-Pins DIP FLAT LCC SKINNY BRAZEDfIM8M3732 16 03764 16 03764A 16 037864 16 037S64A 16 04125616 018 041256A16 018 041257A 16 04146418 022 041100018 026 041100118 026 041425620 026 051100018 026 051100118 026 051425620 026 051425720 026 02128 24 05114 18 05126 24 05128 24 0 0516528 032 05165L28 032 05188 22 65125728 032 051257L28 032 03864 28 038128A 28 038256 28 038256A 28 028101A 40 028201A 40 038512 28 0531000 28 053256 28 02764 28 013

.PACKAGING •• ------------------------------------------------DPACKAGESNo.RS GS JSName of US YS KS ASPins PLASTIC PLASTIC PLASTIC PLASTIC SIDE·DIP FLAT LCC SKINNYMODULE MODULEBRAZED27128 28 027256 28 027512 28 0271000 32 0271024 40 027C64 28 027C128 28 027C1024 40 02816A 24 02301 30 0 02304 30 0 014

------------------------------------------------.PACKAGING •• 16 PIN PLASTIC20.0MAXINDEX MARK7.62±0.30,-______________________ 2WffVm~fI I ~ N2.54±0.25 0.65MAX Seating Plane• 16 PIN PLASTIC\'20.0 MAX~b::;;;;lq~~;;::::;;;;;:::;~!\INDEX MARK'I2 Z,-------------,~ -~-JL0.65 MAX 2.54±0.25~raa~~ ngI!l762 ± 030ozI::; 0.6 MAX;:i;IfN -I- -----15' MAX\Note: All dimensions in millimeters.15

.PACKAGING •• --------------------------------__ ------------__D• 16 PIN STACK PLASTIC20.0 MAXINDEX MARK0.65 MAX 2.54±0.25• 18 PIN PLCC~JL~3 PLACES1.521=;4:2.41® ~:~ *- 563II'0.38 MIN064MIN-+-tt 033;;H~.~~ -1-- j-­·T iIl •t+O: l~~112.370 I :=IO.l:§]12.522 13.20813.588-1 T [~C1618516604T6261 67941d~lj'DilTvp ~ i '-.II + ..... 4 3.645: I 7.290 :' 3.721! ~--7.442 ---j 4.064: 81;'-· -- 4.254f- 8.508:±}-10719~APEX REFAPEX OF LEAOS TO BE&lA¥CIQ38]16

~----------------------------------------------.PACKAGING •• 18 PIN PLASTIC24.5MAX2.54±O.25O.S5MAX• 18 PIN SIDE-BRAZED232MAX)0 lL"\·INDEX MARK7.S2±O.30Zx~ .. --~~~f~5MJ:2.54±O.52 O.SMAX SeatingPlaneNote: All dimensions in millimeters.17

.PACKAGING.I----------------------------------------------• 22 PIN PLCCPIN 1'INDEX MARK@~45oL_-1.22 I I,o@0.50TYP J: ®3 PLACES r-- ~~~ -+-r~ ~:~~ ~. ~FLEAD.S TO BET ~ I ~I!I-W::C ro:38]12.370 13.20812.~22 13.588 ~IQJolI' r $ ,III'I'~ 6.604 1! 6.261 6.794.;t I _ IJ~. ,.[1.27].TYPI I ----;j 3.645Il-~~~ ~~ 3T21I _~4~_, ____ L_ ::~:f--:~~: IT~• 22 PIN PLASTIC27.6 MAXoINDEX MARKSeating Plane27.62±0.30~ rn~r Ir~~~I - 15 0 MAX'0.6 MAX f---~~c-I0.65 MAX 2.54 ± 0.25 9.5 MAX18

--------------------------------------------------.PACKAGING •• 24 PIN PLASTICx«:::;oMz X I 15.24+0.30- «I-~w~v~~~'ji~ ~~~Jill ----rI- _ 150MAX2.54±0.25 0.65MAX SeatingPlane.24 PIN CERDIPx«:::;,...M~ X I 15.24±0.30 ·1~ ~~A··I.I ~- . i z ...I. ;}; I !0.6MAX N -1-+ 02.54±0.25 Seating 15 MAXPlane0.6M~Note: All dimensions in millimeters.19

.PACKAGING •• ------------------------------------------____ __• 24 PIN PLASTIC FLATfJ16.5 MAXL- 13.0 MAX0.45 MAX 1.27±0.13 ~. fB.6±0.3 ~2~ 2~==t1:::=7i) LL~r10° MAX• 26 PIN SOJr--I17,145±O.15f·. M.~~I

------------------.PACKAGING •• 28 PIN PLASTIC38MAX~---------..~x:E«gil~15.24±0.30... ~:EN "L~u ... U:,OMA~0.65 MAX Seati n9 15 MAX• 28 PIN CERDIPr 38.0MAX "I[~~~Q~~~]]Seating Plane~'"I 15.24 ±0.30 II ~ ~[I ~ i ~~L 0.6MAX~~.15°MAXNote: All dimensions in millimeters.21

·PACKAGING.I------------------------------------------------• 32 PIN PLCCAPEX OF LEADS TO BE~$IAIB-Cl Q38J.40 PIN SIDE-BRAZED1-l I51.5 MAX"IIiZx~

oIIIRELIABILITY INFORMATION ..................................................... 251. INTRODUCTION ............................................................ 252. QUALITY ASSURANCE SYSTEM AND UNDERLYING CONCEPTS ............. 253. EXAMPLE OF RELIABILITY TEST RESULTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 274. SEMICONDUCTOR MEMORY FAILURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 31

RELIABILITY INFORMATION1. INTRODUCTIONSemiconductor memories play a leading role in theexplosive progress of semiconductor technology. Theyuse some of the most advanced design and manufacturingtechnology developed to date. With greaterintegration, diversity and reliability, their applicationshave expanded enormously. Their use in· large scalecomputers, control equipment, calculators, electronicgames and in many other fields has increased at a fastrate.A failure in electronic banking or telephone switchingequipment, for example, could have far reaching effectsand can cause incalculable losses. So, the demand, forstable high qual ity memory devices is strong.We, at Oki Electric is fully aware of this demand. Sowe have adopted a comprehensive quality assurancesystem based on the concept of consistency in development,manufacturing and sales.With the increasing demand for improvement in function,capability and reliability, we will expand ourefforts in the future. Our quality assurance system andthe underlying concepts are outlined briefy below.2. QUALITY ASSURANCE SYSTEMAND UNDERLYING CONCEPTSThe quality assurance system employed by Oki Electriccan be divided into 4 major stages: device planning,developmental prototype, production prototype, andmass production. This system is outlined in the followingblock diagram (Fig. 1-1).1 t Device plann ing stageTo manufacture devices that meet the market demandsand satisfy customer needs, we carefully considerfunctional and failure rate requirements, utilizationform, environment and other conditions. Once wedetermine the proper type, material and structure,we check the design and manufacturing techniques andthe line processing capacity. Then we prepare thedevelopment planning and time schedule.2) Developmental prototype stageWe determine circuits, pattern design, process settings,assembly techniques and structural requirements duringthis stage. At the same time, we carry out actual prototypereliability testing.Since device quality is largely determined during thedesigning stage, Oki Electric pays careful attention toquality confirmation during this stage.This is how we do it:(1) After completion of circuit design (or patterndesign), personnel from the design, process technology,production technology, installation' technologyand reliability departments get together fora thorough review to ensure design quality and toanticipate problems that may occur during massproduction. Past experience and know-how guidethese discussions.(2) Since many semiconductor memories involve newconcepts and employ high level manufacturingtechnology, the TEG evaluation test is often usedduring this stage.Note: TEG (Test Element Group) refers to thedevice group designed for stability evaluationof MaS transistors, diodes, resistors,capacitors and other circuit componentelement used in LSI memories.(3) Prototypes are subjected to repeated reliability andother special evaluation tests. In addition, thestabil ity and capacity of the manufactu ring processare checked.3) Production prototype stageDuring this stage, various tests check the reliability andother special features of the production prototype atthe mass production factory level. After confirmingthe quality of device, we prepare the various standardsrequired for mass production, and then start production.Although reliability and other special tests performedon the production prototype are much the same asthose performed on the developmental prototype, thepersonnel, facilities and production site differ for thetwo prototypes, necessitating repeated confirmationtests.4) Mass productionDuring the mass production stage. careful managementof purchased materials, parts and facilities used duringthe manufacturing process, measuring equipment,manufacturing conditions and environment is necessaryto ensure device qual ity first stipulated during thedesigning stages. The manufacturing process (includinginspection of the completed device) is followed by a lotguarantee inspection to check that the specified qualityis maintained under conditions identical to those underwhich a customer would actually use the device. Thislot guarantee inspection is performed in 3 differentforms as shown below.o25

I\JOl~rt-ProcessmentAcceptanceof orderDevelopmentDesignProductionInspectionShipmentDeliveryServiceQuality Assurance& Quality ControlStaff ActivitiesSalesMarketing & Product Planning... Quality--r1 ObjectivesDesig"Production PurchasingEngineer Production EngineerControl (Vendors)...-l Design Review and Tnal Product Review I1II,I Layout Program I ~I Productton rPlannmgI Technical r~ Operahon ~& QualityStandardI Standards ~ ~~t I .1 Production ~I Production• ProcessI I ProcessControlReliabilityEnglneenngProcessSetupI PurchasingGUidelinesIControl..Quality Management and EducationII ..Production Inspectio~ Storaget~~l~ Accept~nceInspectionHIn-ProcessInspection-'-ProductI.H InspectionI~HQualityTesting1StorageControlI1I.auallty and ReliabilityInformation Analysis\ - Quality Evaluation-Failure AnalYSISI~Transportation~paCkag,"g I-YMaintenanceServicerCustomer•::umr:;UJi=:::j-

-------------------. RELIABILITY INFORMATION.Fig. 2Defect Processing FlowchartCustomerFailure report processingRequest fortechnicalimprovementr--------IReport onI results ofI investigationFailure Failure report & improvementdelivery QualityAssuranceDepartmentEngineeringDepartmentDReport onresults of: investigationL _ ~ ~~r~v.:~e~tRequest formanufacturingimprovementManufacturingDepartment11) Group A tests: appearance. labels. dimensionsandelectrical characteristics inspection(2) Group B tests: check of durability under thermaland mechanical environmentalstresses, and operating I ife characteristics(3) Group C tests: performed periodically to checkoperational life etc on long termbasis.Note: Like the reliability tests. the group B tests con·form to the following standards.MIL·STD-883B, JIS C 7022, EIAJ-IC-121Devices which pass these lot guarantee inspections arestored in a warehouse awaiting shipment to customers.Standards are also set up for handling, storage andtransportation during this period, thereby ensuringqual ity prior to delivery.5) At Oki Electric, all devices are subjected to thoroughquality checks. If, by chance, a failure does occur afterdelivery to the customer, defective devices are processedand the problem rectified immediately to minimize theinconvenience to the customer in accordance with thefollowing flowchart.3. EXAMPLE OF RELIABILITY TESTRESULTSWe have outlined the quality assurance system andthe underlying concepts employed by Oki Electric.Now, we will give a few examples of the reliability testsperformed during the developmental and productionprototype stages. All reliability tests performed by OkiElectric conform with the following standards.MIL-STD-883B, JIS C 7022, EIAJ-IC-121Since these reliability tests must determine performanceunder actual working conditions in a short period oftime, they are performed under severe test conditions.For example, the 125"C high temperature continuousoperation test performed for 1000 hours is equivalentto testing device life from 2 to 300 years of use atTa~40°C.By repeating these accelerated reliability tests, devicequality is checked and defects analyzed. The resultinginformation is extremely useful in improving the manufacturingprocesses. Some of the more common defectsin memory LSI elements and their analysis are describedbelow.27

• RELIABILITY INFORMATION •• ------------------~OKI MEMORY LSI LIFE TEST RESULTSDevice name MSM41256-XXRS MSM3764A-XXRS MSM5165-XXRSFunction262144 x 1 bit 65536 x 1 bit 8192 x 8 bitDYNAMIC RAM DYNAMIC RAM STATIC RAMoTestitemStructureTest conditionTa = 125°COperating Vcc = 5.5Vlife test Ta = 150 0 VVcc = 5.5V140°C 85%Temperature Vcc = 5.5Vhumidity test 85°C 85%Vcc = 5.5VPressure 121°C 100%cooker test No biasLow tempera- Ta = _10°Cture life test Vcc = 7.0VSi gate N-MOS Si gate N-MOS Si gate C-MOS16P plastic package 16P plastic package 28P plastic packageSample TestFailures Sample Test Failures Sample Test Failuressize hours Size hours size hours300 2000 0 300 2000 0 88 2000 040 6000 0 50 2000 0 50 2000 0100 100 0 100 100 0 22 100 0100 2000 0 150 2000 0 100 2000 0100 500 0 100 500 0 50 300 022 2000 0 22 2000 0 22 2000 0Temperature _55°C -5005005001000 1000 100cycling test 150°C cycles cycles cycles0Device name MSM27256-AS MSM38256-XXRS MSM531000-XXRSTest itemFunctionStructureTest condition32768 x 8 bit 32768 x 8 bit MSM531000-XXRSUV erasable EP ROM Mask ROM Mask ROMSi gate N-MOS Si gate N-MOS Si gate C-MOS28P cerdip 28P plastic package 28P plastic packageSample TestFailures Sample Test Failures Sample Test Failuressize hours Size hours size hoursTa = 125°COperating Vcc = 5.5Vlife test Ta = 150°CVcc = 5.5V140°C 85%Temperature Vcc = 5.5Vhumidity test 85°C 85%Vcc = 5.5VPressure 121°C 100%cooker test No biasLow tempera- Ta = _10°Ctu re I ife test Vcc = 7.0V88 2000 0 55 2000 0 88 2000 040 2000 022 100 050 1000 0 50 2000 0 25 2000 022 48 0 22 500 0 50 200 022 2000 0 22 2000 0Temperature _55°C -5003001000 50cycling test 150°C cycles cycles0 50 300 028

-------------------. RELIABILITY INFORMATION.~ThermalenvironmentaltestOKI MEMORY LSI ENVIRONMENTAL TEST RESULTSDevice nameTest conditionSoldering 260°Cheat10 secThermalshockTemperaturecyclingVariablefrequencyvibration0°C-100°C5 min 5 min10 cyclesD-55°C-RT-150°C30 min 30min20 cycles100Hz-2000Hz4 min per cycle4 times in X, Y, ZMechanical1500G, 0.5 ms,environmental Shock 5 times in eachtestX,Y,ZConstantacceleration10000G or 20000G1 min in each X, Y, ZMSM41256-XXRS MSM3764A-XXRS MSM5165-XXRSSampleSampleSampleFailuresFailuressize size sizeFailures22 0 22 0 22 022 0 22 0 22 0ElectricalEnvironmental ESD200pF, on, 5 times10 0 10 0 10 0test ±200V~Device name MSM2725-AS MSM38256-XXRS MSM531000-XXRSTest conditionSoldering 260°Cheat10 secSampleSampleSampleFailuresFailuressize size size0°C-100ThermalG C5 min 5 minshock10 cyclesThermalenvironmental 22 0 22 0 22 0test-55°C-RT-150°CTemperature30 min 30 mincycling20 cyclesFailuresMechanicalenvironmentaltestVariablefrequencyvibrationShockConstantacceleration100Hz-2000Hz4 min per cycle4 times in X, Y, Z1500G, 0.5 ms,5 times in eachX,Y,Z10000G or 20000G1 min in each X, Y, Z22 0 22 0 22 0Electricalenvironmental ESD200pF, on, 5 times 10 0 10 0 10 0test ±200V29

• RELIABILITY INFORMATION •• ------------------HIGH TEMPERATURE OPERATING LIFE TESTITa = 125°C, Vee = 5.5V, teyele = 31's)SAMPLE SIZE = 300 pes.MSM41256-12RSDOH 168H 500H 1000H 2000HMAX. 63.54 64.58 64.70 64.86 64.98MIN. 57.92 57.94 57.86 57.90 57.96ICCl mA MEAN 60.700 60.710 60.620 60.700 60.740S.D. 1.339. 1.370 1.376 1.389 1.394DEL. 0.00 1.04 1.16 1.32 1.44MAX. 3.50 3.74 3.62 3.66 3.68MIN. 2.92 2.94 2.92 2.94 2.94ICC2 mA MEAN 3.083 3.097 3.068 3.084 3.084S.D. .113 .144 .119 .119 .120DEL. 0.00 0.68 0.20 0.24 0.26MAX. 112 112 112 112 113MIN. 109 109 109 109 110TRAC ns MEAN 110.9 110.9 111.1 110.9 111.0S.D. .7 .7 .8 .7 .8DEL. 0 -1 1 -1 -1MAX. 52 52 52 52 53MIN. 49 49 49 49 49TCAC ns MEAN 50.8 50.6 51.0 50.6 50.6S.D. .7 .6 .7 .6 .7DEL. 0 -1 1 -1 -1TRACnsns120 60TCAC115 55110 1---f---f---f---i 50 I---i---f---f----i105 45OH 168H 500H 1000H 2000H OH l68H 1000H 2000HmAICClmA70 46560I---f---l---}---I55 2.53.5ICC2I----I---l-l--IOH l68H 500H 1000H 2000H OH l68H 500H 1000H 2000H30

-------------------. RELIABILITY INFORMATION.4. SEMICONDUCTOR MEMORYFAILURESThe life·span characteristics of semiconductor elementsin general (not only semiconduc'or Ie devices) isdescribed by the curve shown in the diagram below.Although semiconductor memory failures are similar tothose of ordinary integrated circuits, the degree ofintegration (miniaturization), manufacturing complexityand other circuit element factors influence theirincidence.2lOJa:< Semiconductor Element Failure Rate Curve>Initial SHIPPINGWear-outfa:.ic.1u=-r"'e'--.'-I----'Random ____...,...:f;::ailurefailure\\\\\\,>.m 1I/General/electronic /devices /___ ~:,1 __ J_//Semiconductorelements--+Time1) Surge DestructionThis is destruction of the input/output stage circuits byexternal surge currents or static electricity. Theaccompanying photograph shows a point of contactbetween aluminum and poly-silicon that has beendissolved by a surge current. A hole has formed in thesubstrate silicon, leading to a short circuit. This kind offailure is traceable in about 30% of defective devicesreturned to the manufacturer. Despite miniaturizationof semiconductor memory component elements (wh ichmeans the elements themselves are less resistant), thesefailures usually occur during assembly and other handlingoperations.At Oki Electric, all devices are subjected to staticelectricity intensity tests (under simulated operationalconditions) in the development stage to reduce this typeof failure. In addition to checking endurance againstsurge currents, special protective circuits are incorporatedin the input and output sections...... AQ)'~' Input sectionAluminurT:~l'1'f7t7R~wire r Poly SiDestructionposition2) Oxide Film Insulation Destruction (Pin Holes)Unlike surge destruction, this kind of failure is causedby manufacturing defects. Local weakened sections areruptured when subjected to external electrical stress.Although this problem is accentuated by the miniaturizationof circuit elements, it can be resolved by maintainingan ultra-clean manufacturing environment andthrough 100% burn-in screening.3) Surface Deterioration due to Ionic ImpuritiesUnder some temperature and electric field conditions,charged ionic impurities moving within the oxide filmpreviously resulted in occasional deterioration of siliconsurfaces. This problem has been eliminated by newsurface stabilization techniques.4) Photolithographic DefectsIntegrated circuits are formed by repeated photographicetching processes. Dust and scratches on the mask(which corresponds to a photographic negative) cancause catastrophic defects. At preseht, componentelements have been reduced in size to the order of 10 .....cm through miniaturization. However, the size of dustand scratches stays the same. At Oki Electric, a highdegree of automation, minimizing human interventionin th& process, and unparalleled cleanliness solves thisproblem.DPhotolithographic DefectExample of surge destruction31

• RELIABILITY INFORMATION .'-------------------D51 Aluminum CorrosionAluminum corrosion is due to electro/ytic reactionscaused by the presence of water and minute impurities.When aluminum dissolves, lines break. This problem isunique to the plastic capsules now used widely to reducecosts. Oki Electric has carefully studied the possiblecause and effect relationship between structureand manufacturing conditions on the one hand, andthe generation of aluminum corrosion on the other.Refinements incorporated in Oki LSls permit superiorendurance to even the most severe high humidityconditions.61 Alpha-Particle Soft FailureThis problem occurs when devices are highly miniaturized,such as in 64-kilobit RAMs. The inversion ofmemory cell data by alpha-particle generated by radioactiveelements like uranium and thorium (present inminute quantities, measured in ppb) in the ceramicpackage material causes defects. Since failure is onlytemporary and normal operation restored quickly, thisis referred to as a "soft" failure. At Oki Electric wehave eliminated the problem by coating the chip surfaceof 64-kilobit RAMs with a resin which effectivelyscreens out these alpha-particle.71 Degradation in Performance Characteristics Due toHot ElectronsWith increased miniaturization of circuit elements,internal electric field strength in the channels increasessince the applied voltage remains the same at 5 V. Asa result, electrons flowing in the channels, as shown inthe accompanying diagram, tend to enter into the oxidefilm near the drain, leading to degradation of performance.Although previous low-temperature operationtests have indicated an increase of this failure, we haveconfirmed by our low-temperature acceleration tests,including checks on test element groups, that no suchproblem exists in Oki LSls.Drain~VD+VG IG~ :SourceHot electronDrainPackage ceramicSubstrate silicon-'-"-----'7"'"""-''-:---'-'--:+--'---:--O''''-'=C-:CC-:- S iii co n ox i de..:,-::,,:,-., =::..:..:.:..:.;o..:...=rF:':"':"--'--"-'-'j-"=-'-'-'- fi I mp/ a-particleIonization alongthe a-particle pathSubstrate siliconCharacteristic deterioration caused by hot electronWith further progress in the miniaturization of circuitcomponents, failures related to pin hole oxide filmdestruction and photolithography have increased. Toeliminate these defects during manufacturing, we atOki Electric have been continually improving our productionprocesses based on reliability tests and informationgained from the field. And we subject all devicesto high-temperature burn-in screening for 48 to 96hours to ensure even greater reliability.32

··.·c

D MOS MEMORY HANDLING PRECAUTIONS ....................................... 351. STATIC ELECTRICITY COUNTERMEASURES................................ 352. POWER SUPPLY AND INPUT SIGNAL NOISE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 353. CMOS MEMORY OPERATING PRECAUTIONS ............................... 35

MOS MEMORY HANDLING PRECAUTIONS1. STATIC ELECTRICITY COUNTER·MEASURESSince voltage is generally controlled by means of thetransistor gate oxide film in MOS memories, the inputimpedance is high and the insulation tends to be destroyedmore readily by static electricity.Although Oki MOS memories incorporate built-inprotector circuits to protect all input terminals fromsuch destruction, it is not considered possible to givecomplete protection against heat destruction due toovercurrents and insulation film destruction due toirregular high voltages. It is, therefore, necessary toobserve the following precautionary measures.1) Under no circumstances must voltages or currentsin excess of the specified ratings be applied to anyinput terminal.2) Always use an electrically conductive mat or shippingtubes for storage and transporting purposes.3) Avoid wearing apparel made of synthetic fiberduring operations. The wearing of cottons which donot readily generate static electricity is desirable.Also avoid handling devices with bare hands. Ifhandling with bare hands cannot be avoided, makesure that the body is grounded, and that a 1MOresistor is always connected between the body andground in order to prevent the generation of staticelectricity.4) Maintaining the relative humidity in the operationroom at 50% helps to prevent static electricity.This should be remembered especially during dryseasons.5) When using a soldering iron, the iron should begrounded from the tip. And as far as possible, uselow power soldering irons (12 V or 24 V irons!.2; POWER SUPPLY AND INPUT SIGNALNOISE2.1 Power supply noise absorptionIn dynamic memories, the flow of power supplycurrent differs greatly between accessing and standbymodes.Although very little power is consumed by CMOSmemories during standby mode, considerable currentis drawn for charging and discharging (instantaneouscurrent requirements) during access mode. In order toabsorb the "spike noise" generated by these currentrequirements, the use of relatively large capacitancecapacitors (about one lO",F capacitor for every 8 to10 RAMs) is recommended along with good high fre·quency response capacitors of about O.l",F for eachmemory element. Power line wiring with as little lineimpedance as possible is also desirable.2.2 Input signal noise absorptionOvershooting and undershooting of the input signalshould be kept to a bare minimum. Undershooting inparticular can result in loss of cell data stability withinthe memory. For this reason,(1) Avoid excessive undershooting when using anaddress common bus for memory board RAMs andROMs.(2) Si nce noise can be generated very easily when usingdirect drive for applying memory board RAMaddresses from other driver boards, it is highlyrecommended that these addresses be first receivedby buffer.(3) Methods available for eliminating undershootinggenerated in the address line includea) Clamping of the undershooting by including adiode.b) Connect 10-200 in series with driver outputs.c) Smooth the rising edge and fall ing edge waveforms.3. CMOS MEMORY OPERATINGPRECAUTIONS3.1 Latch-UpIf the CMOS memory input signal level exceeds theVcc power line voltage by +0.3 V, or drops below theground potential by -0.3 V, the latch-up mechanismmay be activated. And once this latch·up mode hasbeen activated, the memory power has to be switchedoff before normal operating mode can be restored.Destruction of the memory element is also possible ifthe power is not switched off.Although Oki CMOS memories have been designedto counter these tendencies, it is still recommended thatinput signal overshooting and undershooting by avoided.3.2 Battery Back-UpTake special note of the following 4 pOints whendesigning battery back-up systems.(1) Do not permit the input signal H level to exceedVee +0.3 V when the memory Vcc power is dropped.To achieve this, it is recommended that a CMOSdriver using a Vcc power common with the CMOSmemory, or an open collector buffer or open drainbuffer pulled-up by a Vcc power common with the·CMOS memory be used for driving purposes.(2) Set the chip select input signal CE to the same Hlevel as the CMOS memory Vcc power line. And inorder to minimize memory power consumption, setthe write enable input WE level, the address inputarid the data input to either ground level or to thesame H level as the CMOS memory Vcc power line.(3) Make sure that the CMOS memory Vcc power line isincreased without "ringing" or temporary breakswhen restoring the battery back-up mode.(4) When using synchronous type CMOS memories(MSM5115, MSM51 04), make sure that accessingoccurs after elapse of the chip enable off time (tcc)prescribed in the catalog after the Vcc power linehas reached the guaranteed operating voltage range.For further details, refer to "CMOS Memory BatteryBack·up" at the end of this manual.35

D EPROM WRITING AND ERASURE ................................................. 391. EPROM WRITING ERASURE ................................................ 392. EPROM HANDLING ......................................................... 40

EPROM WRITING AND ERASURE1. EPROM WRITING ERASURE1.1 EPROM MSM2764 writingWriting in the MSM2764RS involves setting the drainand gate voltages of the floating gate stage to a highvoltage. When the cjrain voltage exceeds 15 V and thegate voltage 20 V, the channel charge (electrons) be·comes highly energized and flow over the oxide filmbarrier into the floating gate. And since the high gatevoltage is positive polarity, electrons will flow into thefloating gate very easily. When electron, build up inthe floating gate, the memory element "thresholdvoltage" is changed, and subsequently stored as memorydata. Once the charge has been built up, the surroundingoxide film (high insulation) prevents escape of electrons.The data is thus stored as "non·volatile" data.Drain1.2 PROM programmerOki Electric employs a system whereby the variousprogrammer available on the market are examined, andagreements reached with different programmer manufacturers.The purpose of this system is to checkcompatibility between programmer manufacturers andOki Electric devices, and making modifications wheneverrequired. Users are thus ensured trouble-free use.In the event of EPROM trouble with Oki devices andapproved programmer, problems will be handled byboth Oki and driver manufacturer except where suchproblems have been caused purposely.1.3 ErasureErasure of data written in the MSM2764RS canbe effected by ultra-violet radiation of the memoryelement. In this case, the charge is discharged into thesubstrate or electrode by the ultra-violet energy, butnote that the following erasure conditions must be met.If a memory which has not been properly erased is used,writing problems and operating failures are likely toarise. Also note that excessively long erasure times (ofseveral hours duration) can also result in failure.Gate0-----11 V!Floating GateCharging,..- Threshold--~~'-----When the MSM2764RS is shipped from the factory,the floating gate is left in discharged status (all bits "1"),i.e. "blank" status. During writing processes, +25 V isapplied to the Vpp terminal and VIH to the OE input.The data to be programmed is applied in parallel to theoutputs (0. -7). After the address and data have beenset up, application of VIH level for 50ms to the CEinput will enable writing of data. Since the +25 Vapplied to Vpp is fairly close to the element's with·standing voltage, make sure that the voltage setting ismaintained strictly within the 25 V ± 1 V range. Applica·tion of voltages in excess of the rated VOltage, andoversh"oting, to the Vpp terminal can result in permanentdamage to the element.Although MSM2764RS rewriting should be checkedabout 100 times by sample testing, in actual practice 5to 10 times is usually the limit. This will not likelyresult in any problem.Exposure timeLengthy exposure to direct sunlight can also resultin loss of bits. Direct exposure of MSM2764 tothe strong summer sun for a single day can result in bitchanges. Although normal fluorescent lights havepractically no effect, light rays beamed onto elementscan cause special changes. I t is therefore recommendedthat the glass face be covered with a screening label.39

• EPROM WRITING AND ERASURE •• ----------------2. EPROM HANDLING2.1 Defects caused by static electricityThe generation of static electricity on the EPROMglass face can result in changes in the memory con·tents. This, however, can be restored by brief exposure(several seconds) to ultra·violet radiation. But thisexposure must be kept short. Exposure for 30 secondsor more can cause changes in the normal bits.2.2 Handling precautions(1) Avoid carpets and clothes etc where static electricityis generated.(2) Make sure the programmer and mounting system aresecurely grounded.(3) Also make sure that any soldering iron employed isproperly grounded. .(4) Always carry in an electrically conductive plasti.cmat.(5) Written ROMs are also to be kept in an electricallyconductive plastic mat.(6) Do not touch the glass seal by hand since th is canresult in deterioration of the ultra·violet permeabilityrequired for erasure, and subsequently lead to poorerasure.2.3 System debugging precautionsDuring system debugging, check operations with avoltage of ±5%' (oscillating).40

IfI MASK ROM CUSTOMER PROGRAM SPECIFICATIONS ........................... 431. USABLE MEDIA.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .. 432. MAGNETIC TAPE SPECiFiCATIONS ......................................... 433. EPROM SPECiFiCATIONS ................................................... 44

MASK ROM CUSTOMER PROGRAMSPECIFICATIONSThe mask ROM custom program codeprogramming method is outlined below.1. USABLE MEDIA(1) Magnetic tape(2) EPROMMagnetic tape and EPROM are used as standard.2. MAGNETIC TAPE SPECiFICATIONS2.1 Use the following types of magnetic tape in mag·netic tape units compatible with IBM magnetic tapeunits.(1) Length: 2400 feet, 1200 feet or 600 feet(2) No label(3) Width: 1/2 feet(4) Channels: 9 channels(5) Bit density:800BPI standard, although 1600BPIcan also be employed.(6) Block size: I nteger multiples of 256 bytespossible with 256 bytes as standard.1 block, 1 record is standard.2.2 Magnetic tape format(1) The data for a single chip should not extend intoseveral tapes. Data for several chips are allowed to beincluded in a single magnetic tape, mUltiple file formatbeing permitted. In this case, include the data of asingle chip in one file.(2) Use tape marks for file partitions when employingmultiple file formats.(3) Denote the completion of a magnetic tape file bytwo successive tape marks.2.3 Magnetic tape data format(1) The data contained in a single file on magnetic tapemust be inserted from the head address (OOOO)hex ofthe device up to the final address in succession for asingle chip.(2) I n this case, the LSB of the data should correspondto Do, and the MSB to 0,.(3) "1" bits in the data denote high device output,while "0" denotes low output.2.4 Magnetic tape examplesMulti·file format (m chips)(B0 1·chip data file 1T *File 2 File m*:tape markH 1+1 1 ~ 1/ - -/ - - -- - - --/ ---Block 1(~I I IIIR R R R RGBlock 2 GBlock 3GGBlock n·1 G Block n43

• MASK ROM CUSTOMER PROGRAM SPECIFICATIONS •• ---------3. EPROM SPECIFICATIONS(1) MSM2764, Intel 2764 or 27128 equivalent devicemay be used,(2) Prepare 2 EPROMs containing identical data,44

DD MASK ROM DEVELOPMENT FLOWCHART.. .. . . ... . . . . . . . .... .... . .. . . .... . .. .... 47

MASK ROM DEVELOPMENT FLOWCHARTUser'sROM dataMask ROMautomaticdesigning programROM datacheck listl ExaminationNo ~y~ApprovalJMask ROMmanufactureoEngineeringTest samplesafTIpling shipment TAT'NoI ~y.Examination Approval..IShipmentIIProduction Ishipment ITAT" IIIMassproductionIUserOki Electric"TURN-AROUND-TIME47

D TERMINOLOGY AND SYMBOLS .................................................. 511. PIN TERMINOLOGY ........................................................ 512. ABSOLUTE MAXIMUM RATINGS ............................................ 523. RECOMMENDED OPERATION CONDITIONS. . . . ... . . . . .. . . ..... . .... . . ... ... 534. DC CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 545. AC CHARACTERISTICS ..................................................... 55

TERMINOLOGY AND SYMBOLS1. PIN TERMINOLOGYTerm EPROM ROM Static RAM Dynamic RAMPower Supply Voltage PinVDD.Vee Vee Vec VDD. VCCVGG,VBBAddress Input Pin Ao ,..... Al2 Ao ..... All Ao ,....., All A. - A,Data Input Pin 01 DINData Output Pin O. - 0, Do ....... DIS DO D OUTData Input/Output Pin I/O, - I/O,Chip Enable Pin CE CE CEOutput Enable Pin OE OE OEAddress Enable PinAEChip Select Pin CS CSWrite Enable Pin WE WE WERow Address Strobe PinRASColumn Address Strobe PinCASProgram Input PinProgram, VppData Valid PinDVClock Input PinTGround Pin VSS VSS VSS VSSVacant Terminal NC NC51

.TERMINOLOGYANDSyMBOLS.--------------------------------___2. ABSOLUTE MAXIMUM RATINGSTerm EPROM ROM Static RAM Dynamic RAMPower supply voltageVoo. Vee Vee Vee Voo. VeeVGG.VBBVSS VSS VSS VSSTerminal voltage VT VT VTInput voltage VI VI VI VIOutput voltage Va Va Va VaInput currentOutput cu rrent 10Output short circuit currentlOSLoad capacitancePower dissipation Po Po Po PoOperating temperature Topr Topr Topr ToprStorage temperature Tstg Tstg Tstg Tstg52

-----------------'.TERMINOLOGY AND SYMBOLS.3. RECOMMENDED OPERATION CONDITIONSTerm EPROM ROM Static RAM Dynamic RAMVDD. VCC VCC VCC VDD. VCCPower Supply Voltage VGG. VBB VBBVSS VSS VSS VSS"H" Clock Input VoltageVIHC"H" Input Voltage VIH VIH VIH VIH"L" Input Voltage VIL VIL VIL VILData Pretention VoltageVCCHLoad Capacitance CL CLFan·out N N NOperating Temperature Topr Topr Topr Topr53

• TERMINOLOGY AND SYMBOLS ... -----------------4. DC CHARACTERISTICSTerm EPROM ROM Static RAM Dynamic RAM"H" output voltage VOH VOH VOH VOH"L" output voltage VOL VOL VOL VOL"H" output current10H"L" output currentInput leakage current III III III IIIOutput leakage current ILO ILO ILO ILOI/O leak cu rrentILOProgram terminal currentIpPl. lpP2Peak power on current IpO IPO.ISBPPower supply current100. ICC ICC.ICCS ICC.ICCA 1001. ICC1. IBBlIBB.ICCl ICCA ICC1. ICC2 1002. ICC2. IBB2ICC2 ICCS.ICCSl IOD3. ICC3. IBB3ISB1004. ICC4. IBB454

-----------------1. TERMINOLOGY AND SYMBOLS.5. AC CHARACTERISTICS(1) Read cycleTermEPROMROM Static RAM Oynamic RAMRead cycle timetC. tRe. tCYC tRC tRCAddress access timetAcetAA. tACCtAo tACotACC. tAAChip select access timetcotcstCO. tACS1.tACS2Chip enable access timetCEtACEtACOutput enable access timetOEtcotOEOutput setting timetLZtex. tLZOutput valid timetOHtOHtOH. tOHAOutput disable timetOFtHZ tOTO. tHZ. tOFFtOFFAddress set-up timeAddress hold timeChip enable off timeChip enable pulse widthPower-up timePower-down timeAddress enable pulse widthOata valid access timeOata valid delay timeClock delay timeClock pule widthClock delay timeOutput delay timeOutput access timeOutput hold timeAddress enable set-up timetAStAHtputpotAEtVAtvotVHtHtLtootOAtOHtAEStAStAHtcctCEtputpo55

_TERMINOLOGY AND SYMBOLS _._----------------(2) Write CycleTerm EPROM ROM Static RAM Dynamic RAMWrite cycle time twc tRCAddress set-up time tAS tAS. tAWWrite pulse width tpw tWo twp twpWrite recovery timetWRData set-up time tos tOS. tow tosData hold time tOH tOH tOHOutput off'time tOF tOTW.twZ tOFFChip select set-up time tcss tewAddress hold time tAH tAH. tWRChip enable off timeChip enable pulse widthWrite enable set-up timeWrite enable read timeWrite enable hold timeAddress/write enable setting timeWrite enable output activationtcctew. tCEtwstWCLtwHtAWtowOutput enable set-up timeOutput enable hold timeProgram read delay timeOutput enable delay ti meChip enable data valid timeProgram pulse rising edge timeProgram pulse falling edge timeVPP restoration timeChip enable hold timetOEStOEHtOPRtOEtovtPRTtpFTtVRtCH56

III DATA SHEET• MOS DYNAMIC RAMSMSM 3732AS/RS 32,768-Word x l-Bit RAM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . .. 60MSM3764AS/RS 65,536-Word X l-Bit RAM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . .. 76MSM3764AASI ARS 65,536-Word X l-Bit RAM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . .. 92MSM41256AS/RS 262,144-Word X l-Bit RAM (NMOS) .......... 108MSM41256JS 262,144-Word X l-Bit RAM (NMOS) < Page Mode> .......... 122MSM41256AAS/RS 262,144-Word X l-Bit RAM (NMOS) .......... 132MSM41257AAS/RS 262,144-Word x l-Bit RAM (NMOS) ......... 147MSM41464RS 65,536-Word x 4-Bit RAM (NMOS) ........................... 163MSM414256RS 262,144-Word x 4-Bit RAM (NMOS) ......................... 178MSM411000RS 1,048,576-Word x l-Bit RAM (NMOS) ....................... 191MSM411 001 RS 1,048,576-Word x l-Bit RAM (NMOS) ....... 204MSM511000RS 1,048,576-Word x l-Bit RAM (NMOS) ......... 217MSM511 001 RS 1,048,576-Word x l-Bit RAM (NMOS) ...... 218MSM514256RS 262,144-Word x 4-Bit RAM (CMOS) ........... 219MSM514257RS 262,144-Word x 4-Bit RAM (CMOS) ....... 220MSM37S64ARS/37S64RS 131,072-Word x 4-Bit RAM (NMOS) .................. 221MSC2301 YS9/KS9 65,536-Word x 9-Bit RAM (NMOS) ........................... 234MSC2304YS8/KS8 262,144-Word x 8-Bit RAM (NMOS) ......................... 245MSC2304YS9/KS9 262,144-Word x 9-Bit RAM (NMOS) ......................... 256• MOS STATIC RAMSMSM5114RSMSM2128RSMSM5128RS4,096-Word x 4-Bit RAM (CMOS) ............................ 2682,048-Word x 8-Bit RAM (NMOS) ............................ 2732,048-Word x 8-Bit RAM (CMOS) ............................ 278MSM5128-20GSK 2,048-Word x 8-Bit RAM (CMOS) ............................ 283MSM5126RS 2,048-Word x 8-Bit RAM (CMOS) ............................ 289MSM5165RS/JS 8,192-Word x 8-Bit RAM (CMOS) ............................ 294MSM5165LRS/JS 8,192-Word x 8-Bit RAM (CMOS) ............................ 300MSM5188US 16,384-Word x 4-Bit RAM (CMOS) ........................... 307MSM5127RS/JS 32,768-Word x 8-Bit RAM (CMOS) ........................... 312MSM51257LRS/JS 32,768-Word x 8-Bit RAM (CMOS) ........................... 318• MOS MASK ROMSMSM3864RSMSM38128ARSMSM38256RSMSM38256ARSMSM38512RSMSM28101AASMSM28201 AASMSM53256RSMSK531000RS• MOSEPROMSMSM2764ASMSM27128ASMSM27256ASMSM27512ASMSM271000ASMSM271024ASMSM27C64ASMSM27C128ASMSM27Cl024AS• MOS E2 PROMSMSM2816ARS8,192-Word x 8-Bit MASK ROM (NMOS) ...................,.32616,384-Word x 8-Bit MASK ROM (NMOS) .................... 33032,768-Word x 8-Bit MASK ROM (NMOS) .................... 33432,768-Word x 8-Bit MASK ROM (NMOS) .................... 33865,536-Word x 8-Bit MASK ROM (NMOS) .................... 3421 M Bit MASK ROM (NMOS) .................................. 3461 M Bit MASK ROM (NMOS) .................................. 35132,768-Word x 8-Bit MASK ROM (CMOS) .................... 356131,072-Word x 8-Bit MASK ROM (CMOS) .................. 3608,192-Word x 8-Bit EPROM (NMOS) ......................... 36616,384-Word x 8-Bit EPROM (NMOS) ........................ 37232,768-Word x 8-Bit EPROM (NMOS) ........................ 37865,536-Word x 8-Bit EPROM (NMOS) ........................ 384131,072-Word x 8-Bit EPROM (NMOS) ...................... 38965,536-Word x 16-Bit EPROM (NMOS) ...................... 3958,192-Word x 8-Bit EPROM (CMOS) ......................... 40116,384-Word x 8-Bit EPROM (CMOS) ........................ 40765,536-Word x 16-Bit EPROM (CMOS) ...................... 41 32,048-Word x 8-Bit E2 PROM ................................ 420

MOSDYNAMICRAMS

OKI semiconductorMSM3732 AS/RS32,768-BIT DYNAMIC RANDOM ACCESS MEMORYGENERAL DESCRIPTIONThe Oki MSM3732H/L is a fully decoded, dynamic NMOS random access memory organized as 32,768 one-bit words.The design is optimized for high-speed, high performance applications such as mainframe memory, buffer memory,peripheral storage and environments where low power dissipation and compact layc;>ut is required.Multiplexed row and column address inputs permit the MSM3732 'to be housed in a standard 16 pin DIP.The MSM3732 is fabricated using silicon gate NMOS and Oki's advanced Double-Layer Polysilicon process. Thisprocess, coupled with single-transistor memory storage cells, permits maximum circuit density and minimum chipsize. Dynamic circuitry is employed in the design, including the sense amplifiers.Clock timing requirements are noncritical, and power supply tolerance is very wide. All inputs and output are TTLcompatible.FEATURES.32,768 x 1 RAM, 16 pin package• Silicon-gate, Double Poly NMOS, single transistor cell• Row access time,150 ns max (MSM3732H/L-15)200 ns max (MSM3732H/L-20)• Cycle time,270 ns min (MSM3732H/L-15)330 ns min (MSM3732H/L-20)• Low power: 248 mW active,28 mW max standby• Single +5V Supply, ±10% tolerance• All inputs TTL compatible, low capacitive load• Three-state TTL compatible output• "Gated"C"AS• 128 refresh cycles/2 ms• Common 1[0 capability using "Early Write"operation• Output unlatched at cycle end allows extended pagebou ndary and two-d imensional ch ip select• Read-Modify-Write, RAS-only refresh, and Page­Mode capability• On-chip latches for Addresses and Data-in• On-chip substrate bias generator for highperformanceDNCWEA.'A,'A,'PIN CONFIGURATIONVssPin NamesFunctionDout A o.....,A 7 Address InputsRASRow Address StrobeA,'CASColumn Address StrobeA' ,WfWrite EnableDinData InputA,' Oout Data OutputVCCPower Supply (+5V)A' ,VSS Ground (OV)VeeA,• Refresh Address60

----------------... DYNAMIC RAM· MSM3732AS/RS •FuNcTIONAL BLOCK DIAGRAMI----WEBuffersAo-A,OoutVeeWordDriversOn chip VBBVSS-RowAddressBuffersyMemoryCellsI-----OinABSOLUTE MAXIMUM RATINGS (See NotelRating Symbol Value UriitVoltage on any pin relative to VSS VIN, VOUT -1 to +7 VVoltage on Vee supply relative to VSS Vee -1 to +7 VOperating temperature Topr o to 70 °eStorage temperatu re Tstg -55 to +150 °ePower dissipation PD 1.0 WShort circuit output current 50 rnANote: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operationshould be restricted to the conditions as detailed in the operational sections of this data sheet. Exposureto absolute maximum rating conditions for extended periods may affect device reliability.RECOMMENDED OPERATING CONDITIONS(Referenced to VSSIParameterSymbol Min. Typ. Max. UnitSupply VoltageVee 4.5 5.0 5.5 VVSS 0 0 0 VInput High Voltage, all inputs VIH 2.46.5 VInput Low Voltage, all inputs VIL -1.0 0.8 VOperatingTemperatureooe to +70oe61

• DYNAMIC RAM . MSM3732AS/RS •• ----------------DC CHARACTERISTICS(Recommended operating conditions unless otherwise noted.)Parameter Symbol Min. Max. Unit NotesOperating Current"Average power supply current ICCl 45 mA(RAS, CAS cycling; tRC = min.)Standby CurrentPower supply current ICC2 5.0 mA(RAS = CAS = VIH)Refresh Current"Average power supply current ICC3 35 mA(RAS cycling, CAS = VIH; tRC = min.)Page Mode Current"Average power supply current ICC4 42 mA(RAS = VI l, CAS cycling; tpc = min.)Input Leakage CurrentI nput leakage current, any input(OV:;:; VIN :;:; 5·.5V, all other pins notunder test = OV)III -10 10 IJ.AOutput leakage Current(Data out is disabled, IlO -10 10 IJ.AOV :;:; VOUT :;:; 5.5V)Output levelsOutput high voltage (tOH = -5 mAl VOH 2.4 VOutput low voltage (tOl = 4.2 mAl VOL 0.4 VNote*: ICC is dependent on output loading and cycle rates. Specified values are obtained with the output open.CAPACITANCEITa = 25°C, f = 1 MHz)Parameter Symbol Typ. Max. UnitInput Capacitance (Ao - A" DIN) CINl 4.5 5 pFInput Capacitance (RAS, CAS, WE) CIN2 7 10 pFOutput Capacitance (DOUT) COUT 5 7 pFCapacitance measured with Boonton Meter.62

----------------.... DYNAMIC RAM . MSM3732AS/RS •AC CHARACTERISTICS(Recommended operating conditions unless otherwise noted.) Note 1,2,3MSM3732-15 MSM3732-20Parameter Symbol Units NoteMin. Max. Min. Max.Refresh period tREF ms 2 2Random read or write cycle time tRC ns 270 330Read-write cycle time tRWC ns 270 330Page mode cycle time tpc ns 170 225Access time from RAS tRAC ns 150 200 4,6Access time from CAS tCAC ns 100 135 5,6Output buffer turn-off delay tOFF ns 0 40 0 50Transition time tT ns 3 35 3 50RAS precharge time tRP ns 100 120RAS pulse width tRAS ns 150 10,000 200 10,000RAS hold time tRSH ns 100 135CAS precharge time tcp ns 60 80CAS pulse width tCAS ns 100 10,000 135 10,000CAS hold time tCSH ns 150 200RAS to CAS delay time tRCD ns 25 50 30 65 7~to RAS precharge time tCRP ns 0 0Row Address set-up time tASR ns 0 0Row Address hold time tRAH ns 15 20Column Address set-up time tASC ns 0 0Column Address hold time tCAH ns 45 55Column Address hold timereferenced to R AStAR ns 95 120Read command set-up time tRCS ns 0 0Read command hold time-tRCH ns 0 0Write command set-up time twcs ns -10 -10 8Write command hold time twCH ns 45 55Write command hold timereferenced to RAStWCR ns 95 120Write command pulse width twp ns 45 55Write command to RAS lead time tRWL ns 45 55Write command to CAS lead time tCWL ns 45 55Data-in set-up time tDS ns 0 0Data-in hold time tDH ns 45 55Data-in hold time referencedto RAStDHRns95 120CAS to WE delay tCWD ns 60 80 8RAS to WE delay tRWD ns 110 145 8Read command hold timereferenced to R AStRRH ns 20 2563

• DYNAMIC RAM· MSM3732AS/RS .11-----------------NOTES: 1)2)3)4)5)6)7)8)An initial pause of 1001's is required after power-up followed by any 8 RAS cycles (Examples; RASonly) before proper device operation is achieved.AC measurements assume tT = 5 ns.VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals. Also, transitiontimes are measured between VI H and VI L.Assumes that tRCD < tRCD (max.).If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase bythe amount that tRCDexceeds the value shown.Assumes that tRCD < tRCo (max.)Measured with a load circuit equivalent to 2 TTL loads and 100pF.Operation within the tRCD (max.) limit insures that tRAC (max.! can be met. tRCD (max.) is specifiedas a reference point only; if tRCD is greater than the specified tRCD (max.! limit, then accesstime is controlled exclusively by tCAC.twcs, tCWD and tRWD are not restrictive operating parameters. They are included in the data sheetas electrical characteristics only; if twcs ~ twcs (min.), the cycle is an early write cycle and the dataout pin will remain open circuit (high impedance) throughout the entire cycle; if tCWD ~ tCWD(min.! and tRWD > tRWD (min.) the cycle is read-write cycle and the data out will contain data readfrom the selected cell; if neither of the above sets of conditions is satisfied the condition of the dataout (at access time) is indeterminate.READ CYCLE TIMING~-------------------tRC------------------~~RASVIH -VIL -~------------tRAS------------~------,I ~-------tAR------~.~1 ~------~CASVIH -VIL --------'-''--------u.---.. 1-~-t-tCAS----~., r-'-+------,.DAddresses VIH-VIL -WEVIH-VIL -I----tCAC~----------tRAC----------~JtOFFDOUTVOH-VOL-OPENValid Data~ "H", "L" = Don't Care64

----------------.... DYNAMIC RAM· MSM3732AS/RS •WRITE CYCLE TIMING(EARLY WRITE)Addresses V I H - ~VIL - /,,ijV I H - rTTJ'17T,'777:7777mb77?\VIL-~~~~~~~ __ -r __ ~ __ ~~~~~~~~~~~~~~~~VIH-IV I L - ,,"".i.U.l.Cf.I.I..~""'I'4UJ...

• DYNAMIC RAM' MSM3732AS/RS .1-----------------RAS ONLY REFRESH TIMING(CAS: VIH,W£" & DIN: Don't care)-- VIH­RAS VIL-~RAH~Addresses ~:~_~ Row AddresstASRVOH -DOUT ___________ ~VOL -OPEN~ "H", "L" ~ Don't CarePAGE MODE READ CYCLE~---------tRAS-----------'""VIH­Adresses V I L -DOUTVOH--------IItOFFI~~~~------~~------~irj----~~--tR-~-H~~~~~ .. H","L"=Don't CarE66

----------------__ DYNAMIC RAM· MSM3732AS/RS _PAGE MODE WRITE CYCLE~-----------------tRAS------------------~Addresses ~ I H - '/!>tIRD!\IV;;VCIL-~1~~~'uF~~~~~~~l~~'~~~~~"H", "L" = Don't CarePAGE MODE, READ-MODIFY-WRITE CYCLERASCASVIHVILVIHVILAddresses VIHVILWEVIHVILDINDOUTVIHVILVOHVOL~~, 1;/0 ~~tCAC--j ~F-l--tcAchOPEN~~~ "H" , "L" = Don't Care67

• DYNAMIC RAM· MSM3732AS/RS •• ----------------HIDDEN REFRI;SHRASVIHVILCASVIHVILAddressesVIHVILWEDOUTVIHVIL~----_----~f'j1!7~.~Valid Data 5-~ "H", "L" = Don't CareDESCRIPTIONAddress Inputs:A total of fifteen binary input address bits are requiredto decode any 1 of 32,768 storage cell locations withinthe MSM3732. Eight row-address bits are established onthe input pins (Ao -A,) and latched with the RowAddress Strobe (RAS)' The seven column-address bits(Ao through A.) are established on the input pins andlatched with the Column Address Strobe (CAS). Allinput addresses mU!l.t be stable on or before the fallingedge of RAS. CAS is internally inhibited (or "gated")by RAS to permit triggering of CAS as soon as the RowAddress Hold Time ItRAH) specification has beensatisfied and the address inputs have been changed fromrow-addresses to column-addresses.One Column Address (A,) has to be fixed at logic "0"(low level) for MSM3732L, and at logic "1" (high level)for MSM3732H.Write Enable:The read mode or write mode is selected with the WEinput. A logic high (1) on WE dictates read mode;logic low (0) dictates write mode. Data input is dis·abled when read mode is selected.Data Input:Data is written into the MSM3732 during a write orread-write cycle. The last falling edge of WE or CAS isa strobe for the Data In (DIN) register. In a writecycle, if WE is brought low (write mode) before CAS,DIN is strobed by CAS, and the set-up and hold timesare referenced to CAS. I n a read-write cycle, WE willbe delayed until CAS has made its negative transistion.Thus DIN is strobed by WE, and set-up and hold timesare referenced to WE.Data Output:The output buffer is three-state TTL compatible witha fan-out of two standard TTL loads. Data-out is thesame polarity as data-in. The output is in a high impedancestate until CAS is brought low. In a read cycle,or read-write cycle, the output is valid after tRAC fromtransition of RAS when tRCD (max.) is satisfied, orafter tCAC from transition of (!AS when the transitionoccurs after tRCD (max.). Data remain valid until CASis returned to a high level. In a write cycle the identicalsequence occurs, but data is not valid.Page Mode:Page-mode operation permits strobing the row·addressinto the MSM3732 while maintaining RAS at a logiclow (0) throughout all successive memory operations inwhich the row-address doesn't change. Thus the powerdissipated by the negative going edge of RAS is saved.Further, access and cycle times are decreased becausethe time normally required to strobe a new row-addressis eliminated.Refresh:Refresh of the dynamic memory cells is accomplishedby performing a memory cycle at each of the 128 rowaddresses(Ao -A.) at least every two milliseconds.During refresh, either VIL or VIH is permitted for A,.RAS only refresh avoids any output during refreshbecause the output buffer is in the high impedancestate unless CAS is brought low. Strobing each of 128row-addresses with RAS will cause all bits in each rwoto be refreshed. Further RAS-only refresh results in asubstantial reduction in power dissipation.Hidden Refresh:RAS ONLY REFRESH CYCLE may take place whilemaintaining valid output data. This feature is referredto as Hidden Refresh.Hidden Refresh is performed by holding CAS as VILfrom a previous memory read cycle.68

________________... DYNAMIC RAM . MSM3732AS/RS •TYPICAL CHARACTERISTICS>"0Iti"u>UU

• DYNAMIC RAM· MSM3732AS/RS .-----------------ICCl (tRP: Constant)v.s. Vee50,----,----.----,---,Ta = 25°CtRP = 100 ns~ 40~--~----~--~4.0 4.5 5.0Vee [V]5.56.05.0~E% 4.0-6c:co!1 3.0NUu2.0VIH: max.ICC2 v.s. Vee-25°C-C75°C :;:::;;:;-:fa = aOC--~4.0 4.5 5.0 5.5 6.0Vee [VIICCl (tRP: Constant)v.s. Cycle rateIf ::C2 v.s. Ta~!C0.~" ~QU!:?50Ta= 25 CItRP = 100 ns5.0V4.5Vveb = 5.5\1.5.0VIH: max.~E>- 4.0.0-6c:co!1 3.0Nu!:? 2.0...............~ r---.......... r--.2 3 4Cycle Rate (lltRc) [MHzI5o 25 50 75ICCl (tRP: Constant)v.s. Ta50.-,----,----.----,-.Vee = 5.5VtRP = 100'ns40~+--_+----+---~~o 7570

----------------... DYNAMIC RAM· MSM3732AS/RS •u-5i~'"!5Mu!:?40302010ICC3 hRP: Constant)v.s. TaVee = 5.5VItRP = 100 ns1--~tRc ~ 240 Os~-I--- - .:-g~:-!2!~~--1o 25 50 75Ta rOC]71

• DYNAMIC RAM· MSM3732AS/RS .-----------------ICC4 (tCAS: Constant)v.s. VeeICC4 (tcp: Constant!v.s. VeeTa ~ 25°CtCAS ~ 100 ns

----------------... DYNAMIC RAM· MSM3732AS/RS •Address Inputv.s VeeAddress Inputv.s. TaTa = 25°CVIHminIIVee = 5.0V>" 2.0VIH min-_~" 5 1.~::>C.c:1.0VIL max4.0 4.5 5.05.5 6.0o25 5075Vee [V]Ta rOC]Ta = 25°CData Inputv.s. VeeData Inputv.s. TaT J.Vee = 5.0V>" 2.0>"Oi~2.01.5VIH min~::>C.c:1.0VI~ maxVee [V]o25 50Ta rOC]75Clock Inputv.s. VeeClock Inputv.s. TaTa=25°CI J.Vee = 5.0V>"Oi~~::>C..E2.0>"Oi~~::>C..E2.01.51.0VIHminVIL maxo 25 5075Vee [V]Ta rOc]73

• DYNAMIC RAM· MSM3732AS/RS .----------------RAS/CAS CYCLE LONG RAS/CAS CYCLE RAS ONLY CYCLE PAGE MODE CYCLE'- -f..l r-r-r- \- I \~ I\. _1 ""\.....~-8060ICC[mAl 4020Ift ~ ~ ~ A(\.1 \J lJ ~ r\ \ \ i\ l 11\ I J'"1\ V'\J rv \ J rv 1"- ~ "1\ '1/50 ns/dlv74

_________________ • DYNAMIC RAM· MSM3732AS/RS •MSM3732 Bit MAP (Physical-Decimal)191~~g 25563 62255 25563 62254 254191 190254 254191 190253 25363 62253 25363 62252 252191 190252 252191 190251 251MSM3732H BIT MAP[A7 column - "H"j192 193255 255 255 255129 128 ,......1 0re-64 65255 255 255 25564 65254 254 254 2541 0f--e-129 128 ~ 192 193254 254 254 254129 128192 193253 253 ~ 253 2531 064 65253 253 ~ 253 2531 064 65252 252 ~ 252 252129 128192 193252 252 ~ 252 252129 128~ 192 193251 251 251 251254 255255 255~;~127255126 127254 254254 255254 254254 255253 253126 127253 253126 127252 252254 255252 252254 255251 251191 190127 12763 62127 12763 62126126191 190126126191 19012512563 6212512563 62124124191 190124124191 190123 123MSM3732L BIT MAP[A7column="L"j OPIN16 \129 128127 127 r-11 0 ,-e-127 1271 0 ....126 126129 128 l

OKI semiconductorMSM3764 AS/RS65,536-BIT DYNAMIC RANDOM ACCESS MEMORYGENERAL DESCRIPTIONThe Oki MSM3764 is a fully decoded, dynamic NMOS random access memory organized as 65536 one-bit words.The design is optimized for high-speed, high performance applications such as mainframe memory, buffer memory,peripheral storage and environments where low power dissipation and compact layout is required.Multiplexed row and column address inputs permit the MSM3764 tb be housed in a standard 16 pin DIP. Pin-outsconform to the JEDEC approved pin out.The MSM3764 is fabricated using silicon gate NMOS and Oki's advanced Double-Layer Polysilicon process. Thisprocess, coupled with single-transistor memory storage cells, permits maximum circuit density and minimum chipsize. Dynamic circuitry is employed in the design, including the sense amplifiers.Clock timing requirements are noncritical, and power supply tolerance is very wide. All inputs and output are TTLcompatible.FEATURES.65,536 x 1 RAM, 16 pin package.Silicon-gate, Double Poly NMOS, single transistor cell• Row access time,150 ns max (MSM3764-15)200 ns max (MSM3764-20)• Cycle time,270 ns min (MSM3764-15)330 ns min (MSM3764-20)• Low power: 248 mWactive,28 mW max standby• Single +5V Supply, ±10% tolerance• All inputs TTL compatible, low capacitive load• Three-state TTL compatible output• "Gated" "CAS• 128 refresh cycles/2 ms• Common I/O capability using "Early Write"operation• Output unlatched at cycle end allows extended pageboundary and two-dimensional chip select• Read-Modify-Write, RAS-only refresh, and Page­Mode capability• On-chip latches for Addresses and Data-in• On-chip substrate bias generator for highperformanceIJNCDinWERASA,A,'A,'PIN CONFIGURATIONv"CASPin NamesFunctionDout Ao,.....,A? Address InputsRASRow Address StrobeA,' CAS Column Address StrObeA,'WEWrite EnableDinData" InputA,' Dout Data OutputVCC,Power Supply (+5V)A,'VSSGround (OV)VeeA,• Refresh Address76

--------------------11. DYNAMIC RAM· MSM3764AS/RS •FUNCTIONAL BLOCK DIAGRAMRASeAS--~=;~~~~~~L-)------lL-------T-~1-------- WEDout1--------DinABSOLUTE MAXiMUM RATINGS (See Note)Rating Symbol Value UnitVoltage on any pin relative to vss VIN, VOUT -1 to +7 VVoltage on Vee supply relative to VSS Vee -1 to +7 VOperating temperature Topr o to 70 °eStorage temperature T stg -55 to +150 °ePower dissipation PD 1.0 WShort circuit output current 50 mANote: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operationshould be restricted to the conditions as detailed in the operational sections of this data sheet. Exposureto absolute maximum rating conditions for extended periods may affect device reliability.RECOMMENDED OPERATING CONDITIONS(Referenced to Vss)Parameter Symbol Min. Typ. Max. UnitSupply VoltageVee 4.5 5.0 5.5 VVSS 0 0 0 VInput High Voltage, all inputs VIH 2.46.5 VInput Low Voltage, all inputs VIL -1.0 0.8 VOperatingT emperatu reoOe to +70 o e77

• DYNAMIC RAM' MSM3764AS/RS .1-----------------DC CHARACTERISTICS(Recommended operating conditions unless otherwise noted.1Parameter Symbol Min. Max. Unit NotesOperating Current*Average power supply current ICCl 45 mA(RAS, CAS cycling; tRC = min.1Standby CurrentPower supply current ICC2 5.0 mA(RAS = CAS = VIHIRefresh Current"Average power supply current ICC3 35 mA(RAS cycling, CAS = VIH; tRC = min.!Page Mode Current"Average power supply current ICc4 42 mA(RAS = Vll, CAS cycling; tpc = min.1Input leakage CurrentInput leakage current, any input(OV ::; VIN ::; 5.5V, all other pins notunder test = OVIIII -10 10 jJ.AOutput leakage Current(Data out is disabled, IlO -10 10 jJ.AOV ::; VOUT::; 5.5VIOutput levelsOutput high voltage (tOH = -5 mAl VOH 2.4 VOutput low voltage (tOl = 4.2 mAl VOL 0.4 VNote*: ICC is dependent on output loading and cycle rates. Specified values are obtained with the output open.CAPACITANCE(T a = 25° C, f = 1 MHzlParameterInput Capacitance (Ao - A 7 , DINIInput Capacitance (RAS, CAS, WEIOutput Capacitance (DOUTICapacitance measured with Boonton Meter.SymbolCINlCIN2COUTTyp. Max. Unit4.5 5 pF7 10 pF5 7 pF78

----------------... DYNAMIC RAM . MSM3764AS/RS •AC CHARACTERISTICS(Recommended operating conditions unless otherwise noted.) Note 1,2,3MSM3764-15 MSM3764-20Parameter Symbol Units NoteMin. Max. Min. Max.Refresh period tREF ms 2 2Random read or write cycle time tRC ns 270 330Read-write cycle time tRWC ns 270 330Page mode cycle time tpc ns 170 225Access time from RAS tRAC ns 150 200 4,6Ac~ess time from CAS tCAC ns 100 135 5,6Output buffer turn-off delay tOFF ns 0 40 0 50Transition time tT ns 3 35 3 50RAS precharge time tRP ns 100 120RAS pulse width tRAS ns 150 10,000 200 10,000RAS hold time tRSH ns 100 135CAS precharge time tcp ns 60 80CAS pulse width tCAS ns 100 10,000 135 10,000CAS hold time tCSH ns 150 200~ to CAS delay time tRCD ns 25 50 30 65 7CAS" to RAS precharge time tCRP ns 0 0Row Address set-up time tASR ns 0 0Row Address hold time tRAH ns 15 20Column Address set-up time tASC ns 0 0Column Address hold time tCAH ns 45 55Column Address hold timereferenced to R AStARns95 120Read command set·up time tRCS ns 0 0Read command hold time tRCH ns 0 0Write command set-up time twcs ns -10 -10 8Write command hold time tWCH ns 45 55Write command hold timereferenced to R AStWCRns95 120Write command pulse width twp ns 45 55Write command to RAS lead time tRWL ns 45 55Write command to CAS lead time tCWL ns 45 55Data·in set-up time tDS ns 0 0Data·in hold time tDH ns 45 55Data-in hold time referencedto RAStDHR ns 95 120CAS to WE delay tCWD ns 60 80 8RAS to WE delay tRWD ns 110 145 8Read command hold timereferenced to R AStRRHns 20 2579

• DYNAMIC RAM· MSM3764AS/RS .-----------------NOTES: 1)2)3)4)5)6)7)8)An initial pause of 100ILs is required after power-up followed by any 8 RAS cycles (Examples; RASonly) before proper device operation is achieved.AC measurements assume tT = 5 ns.VIH (Min.) and VI L (Max.) are reference levels for measuring timing of input signals. Also, transitiontimes are measured between VIH and VIL.Assumes that tRCD < tRCD (max.).If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase bythe amount that tRCD exceeds the value shown.Assumes that tRCD < tRCD (max.)Measured with a load circuit equivalent to 2 TTL loads and 100pF.Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specifiedas a reference point only; if tRCD is greater than the specified tRCD (max.) limit, then accesstime is controlled exclusively by tCAC.twcs, tCWD and tRWD are not restrictive operating parameters. They are included in the data sheetas electrical characteristics only; if twcs ~ twcs (min.), the cycle is an early write cycle and the aataout pin will remain open circuit (high impedance) throughout the entire cycle; if tCWD ~ tCWD(min.) and tRWD > tRWD (min.) the cycle is read-write cycle and the data out will contain data readfrom the selected cell; if neither of the above sets of conditions is satisfied the condition of the dataout (at access time) is indeterminate.READ CYCLE TIMINGtRCRASVIH-VIL -tARCASVIH -VIL-11VIH-Addresses VIL -WEDOUTtRACVOH-VOL-OPENI---tCACVIH-VIL-JValid DatatOFF~"H", "L" = Don't Care80

----------------__• DYNAMIC RAM' MSM3764AS/RS •WRITE CYCLE TIMING(EARLY WRITE)RASCASvIH-VILtRSH___---l.~=~~:::::T~-tCAS--- r---lr--=.:..::....--'-_____VIH --VIL-Addresses Vvi H - 1)IL -1,'lV I H - 7T17",",",",",",""",,""VIL-,~~""""~~~-~-7_-~~""""""~~~""""~~~""~~VIH-;::VI L - '-I.I..t.~~~"4'""~~DOUT VOH- _______ ---iVOL-READ-WRITE/READ-MODIFY-WRITE CYCLEAddresses VV IH -IL -LVIH-~""""~~"*-------------~VI L - "-'-'-1..I.I.I.'fL'-""lU.4tCACDOUT ~ ~~ ::: OPEN r-------

-------------------tl. DYNAMIC RAM· MSM3764AS/RS •PAGE MODE WRITE CYCLE~------------------tRAS------------------~Addresses vV I H - '/l>.1Hooi'V/',v'CIL- ~~~~~~~~r~~~~4~~~"H", "L" = Don't CarePAGE MODE, READ-MODIFY-WRITE CYCLEAddresses V I HVILDOUT VOHVOL----OPEN-----

• DYNAMIC RAM . MSM3764AS/RS .1----------------HIDDEN REFRESHRASVIHVILCASVIHVILAddressesWEDOUTVIHVIL_----____ ~av~~/,0Valid Data 5-~ "H", "L" = Don't CareDESCRIPTIONAddress Inputs:A total of sixteen binary input address bits are requiredto decode any 1 of 65536 storage cell locations withinthe MSM3764. Eight row-address bits are established onthe input pins (Ao-A 7 ) and latched with the RowAddress Strobe (FiAS). The eight column-addressbits are establ ished on the input pins and latched withthe Column Address Strobe (CASI. All input addressesmust be stable on or before the falling edge of RAS.CAS is internally inhibited (or "gated") by RAS topermit triggering of CAS as soon as the Row AddressHold Time (tRAH) specification has been satisfied andthe address inputs have been changed from row-addressesto column-addresses.Write Enable:The read mode or write mode is selected with the WEinput. A logic high (1) on WE dictates read mode;logic low (0) dictates write mode. Data input is disabledwhen read mode is selected.Data Input:Data is written into the MSM3764 during a write orread-write cycle. The last falling edge of WE or CAS isa strobe for the Data In (DIN) register. In a writecycle, if WE is brought low (write mode) before CAS,·01 N is strobed by CAS, and the set-up and hold timesare referenced to CAS. In a read-write cycle, WE willbe delayed until CAS has made its negative transistion.Thus DIN is strobed by WE, and set-up and hold timesare referenced to WE.Data Output:The output buffer is three-state TTL compatible witha fan-out of two standard TTL loads. Data-out is thesame polarity as data-in. The output is in a high impedancestate until CAS is brought low. In a read cycle,or read-write cycle, the output is valid after tRAC fromtransition of RAS when tRCD (max.) is satisfied, orafter tCAC from transition of ~ when the transitionoccurs after tRCD (max.1. Data remain valid until CASis returned to a high level. In a write cycle the identicalsequence occurs, but data is not valid.Page Mode:Page-mode operation permits strobing the row-addressinto the MSM3764 while maintaining RAS at a logiclow (0) throughout .. all successive memory operations inwhich the row-address doesn't change. Thus the powerdissipated by the negative going edge of RAS is saved.Further, access and cycle times are decreased becausethe time normally required to strobe a new row-addressis eliminated.Refresh:Refresh of the dynamic memory cells is accomplishedby performing a memory cycle at each of the 128 rowaddresses(Ao -A.) at least every two milliseconds.During refresh, either VIL or VIH is permitted for A 7 •RAS only refresh avoids any output during refreshbecause the output buffer is in the high impedancestate unless CAS is brought low. Strobing each of 128row-addresses with RAS will cause all bits in each rwoto be refreshed. Further RAS-only refresh results in asubstantial reduction in power dissipation.Hidden Refresh:RAS ONLY REFRESH CYCLE may take place whilemaintaining valid output data. This feature is referredto as Hidden Refresh.Hidden Refresh is performed bV holding CAS as VILfrom a previous memory read cycle.84

------------------11. DYNAMIC RAM· MSM3764AS/RS •TYPICAL CHARACTERISTICSAccess time from RAS(Relative value! v.s. VeeICCI hRAS: Constant!v.s. Vee> otti" 1.1II>u~ 1.0.g:11> 0.9U~!fTa = 25°C"- '",~ I'--4.0 4.5 5.0Vee[V]5.56.0co.;:..~Q4.04.5 5.0Vee [V]looo ns5.5 6.0u° It)N"..~U~a:.t:co~U~g:1.11.00.9Access time from RAS(Relative value! v.s. TaVee' = 5.0"~VVo 25 50 75l,-co.~CoQUtJICCI (tRAS: Constant!v.s. Cycle rate50r----r----~--~----,Ta = 25°CItRAS = 140 ns Voo = 5.5VCycle Rate (l/tRcI [MHz]5.0V4.5V5;;0ttiu>U~tJ.t:11~tJ~81.11.00.94.0Access tlme from CAS(Relative value) v.s. VeeVee [V]

• DYNAMIC RAM· MSM3764AS/RS •• ----------------ICCl (tRP: Constant)v.s. Vee50r----r----r----r---,Ta = 25°CtRP = ioo ns~ 401----+-,.-+_:;{Eco.~" c.SUu4.0 4.5 5.0Vee [V]5.56.0ICCl (tRP: Constant)v.s. Cycle rate50r----r----r----r----,4.5VICC2 v.s. VeeVIH: max.5.0:;{E% 4.0 --I-.-6c:co:fa = O°C~ 3.0N25°CUU -- 2.07'5° C ~4.0 4.5 - 5.0 5.5 6.0Vee [V]ICC2 v.s. TaVee = 5.5\l5.0:;{ VIH: max.E>- 4.0.c-6c:co ..§ 3.0NU~ 2.0........ i'...... .....................2 3 4Cycle Rate (litRe) [MHz]'5o 25 50 75Ta [OC]ICCl (tRp: Constant)v.s. Ta:;{Eco.':::~" c.SUu50r-~--~----,---~--,Vee = 5.5VtRP = 100'ns40I-F-...... =--o 25 50 7586

-----------------. DYNAMIC RAM· MSM3764AS/RS •';i'EQ;ICC3 (tRAS: Constant)v.s Vee40r----r----,----r--~Ta = 25°CtRAS = 140 ns30f----+-----hu>u~Q).::Q) 000 ns: 10~--~--~~~~==~u';i'EQ;u>uMU::;ICC3 (tRp: Constant)v.s. Vee40~--~----~----~--~Ta = 25°CtRP = 100 ns301----1------1-4.0 4.5 5.0Vee [V]5.56.04.0 4.5 5.0Vee [V]5.5 6.0';i'EICC3 (tRAS: Constant)v.s. Cycle rate40,----r----,----.----,Ta = 25°CtRAS = 140 ns30~--_+----1---~~~~';i'EQ;U>u~~Q)!SMu::;403010ICC3 (tRp: Constant)v.s. Cycle rateTa = 25°CtRP = 100 ns5.0V4.5V2 3 4Cycle rate (lltRd [MHz]52 3 4Cycle rate (1/tpC) [MHz]5';i'EQ;U>U;;;;~Q)!SMUU40302010ICC3 (tRAS: Constant)v.s. TaVe~ = 5.5VItRAS = 140 ns;:-- ~Ons'-- 330 nsI-t--500 ns---.;.;.1000 nso 25 50 75:tEQ;U>U~~Q)!SMu::;40302010ICC3 (tRP: Constant)v.s. TaVee = 5.5V!tRP = 100 ns----~~ns1'-3~"- 500 ns100~ --.....o 25 50~7587

• DYNAMIC RAM· MSM3764AS/RS •• ----------------ICC4 (tCAS: Constant)v.s. VeeTa = 25°CtCAS = 100 ns"

----------------... DYNAMIC RAM· MSM3764AS/RS •Address Inputv.s VeeAddress Inputv.s. Ta5'OJ!;0..:2.01.51.0Vl=5.0JVIH minVIL max4.0 4.5 5.0Vee [V]5.5 6.0o25 50Ta rOC]75Data Inputv.s. VeeData Inputv.s. Ta~OJ>.2!~::l0..:2.0Ta = 25°C5'OJ!~::l0..:2.01.51.0v~e = 5.0'VVIH minVIL maxTo25 5075Vee [V]Ta rOC]Clock Inputv.s. VeeClock Inputv.s. Tav~e =5.dv5'OJ!~::l0..:5'OJ!~::l0..:2.01.51.0VIHminVIL max4.0 4.5 5.05.5 6.0o 25 5075Vee [V]89

• DYNAMIC RAM· MSM3764AS/RS •• -------------___ _RAS/CAS CYCLE LONG RAS/CAS CYCLE RAS ONLY CYCLE PAGE MODE CYCLE'-- ..J \ \:-:-r-1\- I \1- I\. _1 ""\..... I--8060ICC[mAl 4020"'".I~ ~ ~ ~ i A~ ~\ ~ \ i\ 1\ ~\J 11\ Ui\ 'V~I V U\j IV \lJ rv '" ~50 ns/dlv~II 'I\. ..90

________________ --11. DYNAMIC RAM· MSM3764AS/RS •MSM3764 Bit MAP (Physical-Decimal)[A7 column = "H"][A7 column = "L"] OPIN 16 \191 190255 25563 62255 25563 62254 254191 190254 254191 190253 25363 62253 25363 62252 252191 190252 252191 190251 251129 128~255 2551 0255 2551 0254 254129 128254 254129 128253 2531 0253 2531 0252 252129 128252 252129 128251 251r&-......~~f---&-l-

OKI semiconductorMSM3764 AAS/RS65,536-BIT DYNAMIC RANDOM ACCESS MEMORY (E3-S-004-321GENERAL DESCRIPTIONThe Oki MSM3764A is a fully decoded, dynamic NMOS random access memory organized as 65536 one-bit words.The design is optimized for high·speed, high performance applications such as mainframe memory, buffer memory,peripheral storage and environments where low power dissipation and compact layout is required.Multiplexed row and column address inputs permit the MSM3764A to be housed in a standard 16 pin DIP. Pin-outsconform to the JEDEC approved pin out.The MSM3764A is fabricated using silicon gate NMOS and Oki's advanced Double·Layer Polysilicon process. Thisprocess, coupled with single·transistor memory storage cells, permits maximum circuit density and minimum chipsize. Dynamic circuitry is employed in the design, including the sense amplifiers.Clock timing requirements are noncritical, and power supply tolerance is very wide. All inputs and output are TTLcompatible.FEATURES.65,536 x 1 RAM, 16 pin package• Silicon·gate, Double Poly NMOS, single transistor cell• Row access time,120 ns max (MSM3764A·12)150 ns max (MSM3764A·15)200 ns max (MSM3764A·20)• Cycle time,230 ns min (MSM3764A·12)260 ns min (MSM3764A·15)330 ns min (MSM3764A·20)• Low power: 330 mWactive,28 mW max standby.Single +5V Supply, ±10% tolerance• All inputs TTL compatible, low capacitive load• Three-state TTL compatible output• "Gated" CAS• 128 refresh cycles/2 ms• Common I/O capability using "Early Write"operation• Output unlatched at cycle end allows extended pageboundary and two-dimensional chip select• Read·Modify·Write, RAS·only refresh, and Page·Mode capability• On-chip latches for Addresses and Data·in• On-chip substrate bias generator for highperformance~NCWEAo'A,'A,'PIN CONFIGURATIONPin NamesFunctionDout Ao ....... A, Address InputsRASRow Address StrobeA,' CAS Column Address StrobeA,'.~ Write EnableDinData InputA, Oout Data OutputVccPower Supply (+5V)A,'VSSGround (OV)VeeA,• Refresh Address92

---------------____ DYNAMIC RAM· MSM3764AAS/RS _FUNCTIONAL BLOCK DIAGRAMI----WEBuffersAo-A,DoutVeeWordDriversOn chip VBBVSS-RowAddressBuffersyMemoryCellsI-----DinABSOLUTE MAXIMUM RATINGS (See Note)Rating Symbol Value UnitVoltage on any pin relative to VSS VIN, VOUT -1 to +7 VVoltage on Vee supply relative to Vss Vee -1 to +7 VOperating temperature Topr o to 70 °eStorage temperature Tstg -55 to +150 °ePower dissipation PD 1.0 WShort circuit output current 50 mANote: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operationshould be restricted to the conditions as detailed in the operational sections of this data sheet. Exposureto absolute maximum rating conditions for extended periods may affect device reliability.RECOMMENDED OPERATING CONDITIONS(Referenced to VSS)Parameter Symbol Min. Typ. Max. UnitSupply VoltageVee 4.5 5.0 5.5 VVSS 0 0 0 VInput High Voltage, all inputs VIH 2.46.5 VInput Low Voltage, all inputs VIL -1.0 0.8 VOperatingTemperatureoOe to + 70 0 e93

• DYNAMIC RAM· MSM3764AAS/RS •• ----------------DC CHARACTERISTICSI Recommended operating conditions unless otherwise noted.)Operating Current"Parameter Symbol Min. Max. Unit NotesAverage power supply current ICCl 60 mAIRAS, CAS cycling; tRC = min,)Standby CurrentPower supply current ICC2 5.0 mAIRAS = CAS = VIH)Refresh Current"Average power supply current ICC3 40 mAIRAS cycling, CAS = VIH; tRC = min.)Page Mode Current"Average power supply current ICC4 60 mAIRAS = VI L, CAS cycling; tpc = min.)Input Leakage CurrentInput leakage current, any input(OV S; VIN S; 5.5V, all other pins notunder test = OV)III -10 10 /lAOutput Leakage Current(Data out is disabled, ILO -10 10 /lAOV S; VOUT S; 5.5V)Output LevelsOutput high voltage IIOH = -5 mAl VOH 2.4 VOutput low voltage IIOL = 4.2 mAl VOL 0.4 VNote": ICC is dependent on output loading and cycle rates. Specified values are obtained with the output open.CAPACITANCEITa= 25°C, f= 1 MHz)ParameterInput Capacitance lAo - A" DIN)I nput Capacitance IRAS, CAS, WE)Output Capacitance IDOUT)SymbolCINlCIN2COUTTyp. Max. Unit- 5 pF- 8 pF- 7 pFCapacitance measured with Boonton Meter.94

----------------.... DYNAMIC RAM· MSM3764AAS/RS •AC CHARACTERISTICS(Recommended operating conditions unless otherwise noted. I Note 1,2,3MSM3764A-12 MSM3764A-15 MSM3764A-20Parameter Symbol Units NoteMin. Max. Min. Max. Min. Max.Refresh period tREF ms 2 2 2Random read or write cycle time tRC ns 220 260 330Read-write cycle time tRWC ns 245 280 345Page mode cycle time tpc ns 120 145 190Access time from R AS tRAC ns 120 150 200 4,6Access time from CAS tCAC ns 60 75 100 5,6Output buffer turn-off delay tOFF ns a 35 a 40 a 50Transition time tT ns 3 35 3 35 3 50RAS precharge time tRP ns 90 100 120RAS pulse width tRAS ns 120 10,000 150 10,000 200 10,000RAS hold time tRSH ns 60 75 100CAS precharge time (Page cyclel tcP ns 50 60 80CAS pulse width tCAS ns 60 10,000 75 10,000 100 10,000CAS hold time tCSH ns 120 150 200RAS to CAS delay time tRCD ns 25 60 25 75 30 100 7CAS to RAS precharge time tCRP ns a 0 0Row Address set-up time tASR ns 0 0 0Row Address hold time tRAH ns 15 15 20Column Address set-up time tASC ns 0 0 0Column Address hold time tCAH ns 20 20 25Column Address hold timereferenced to R AStARns80 95 125Read command set-up time tRCS ns 0 0 aRead command hold time tRCH ns 0 0 aWrite command set-up time twcs ns -10 -10 -10 8Write command hold time tWCH ns 40 45 55Write command hold timereferenced to RAStWCRns100 120 155Write command pulse width twp ns 40 45 55Write command to RAS lead time tRWL ns 40 45 55Write command to CAS lead time tCWL ns 40 45 55Data-in set-up time tDS ns 0 a 0Data-in hold time tDH ns 40 45 55Data-in hold time referencedto RAstDHRns100 120 155CAS to WE delay tCWD ns 40 45 55 8RAS to WE delay tRWD ns 100 120 155 8Read command hold timereferenced to RAStRRHnsa 0 aCAS precharge time tCPN ns 30 35 4595

• DYNAMIC RAM· MSM3764AAS/RS •• ----------------NOTES: 1)2)3)4)5)6)7)8)An initial pause of 100jts is required after power-up followed by any 8 RAS cycles (Examples; RA!lonly) before proper device operation is achieved.AC measurements assume tT = 5 ns.VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals. Also, transitiontimes are measured between VIH and VIL.Assumes that tRCD < tRCD (max.).If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase bythe amount that tRCD exceeds the value shown.Assumes that tRCD < tRCD (max.)Measured with a load circuit equivalent to 2 TTL loads and 100pF.Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specifiedas a reference point only; if tRCD is greater than the specified tRCD (max.) limit, then accesstime is controlled exclusively by tCAC.twcs, tCWD and tRWD are not restrictive operating parameters. They are included in the data sheetas electrical characteristics only; if twcs ~ twcs (min.), the cycle is an early write cycle and the oataout pin will remain open circuit (high impedance) throughout the entire cycle; if tCWD ~ tCWD(min.) and tRWD > tRWD (min.) the cycle is read-write cycle and the data out will contain data readfrom the selected cell; if neither of the above sets of conditions is satisfied the condition of the dataout (at access time) is indeterminate.READ CYCLE TIMING~-----------------tRC------------------~RASCASVIH-VIL -VIH -VIL-~------------tRAS----------~~-----.... 1 !-....... ----tAR -I Ir----.j~----r--tRSH------~----'-'-----v--....I----+-tCAS-------! ;'--+------,1'----~Addresses VIH-VIL -WEDOUTVIH-VIL-VOH-VOL-I-----tCAC~----------tRAC----------~OPENI----I.r-----iValid DatatOFF~"H", "L" = Don't Care.96

----------------..... DYNAMIC RAM· MSM3764AAS/RS •WRITE CYCLE TIMING(EARLY WRITE)VIH-RAS VIL -CASVIH --VIL -tARtRCtRAStRSHtCASWEVIH-VIL -DINDOUTVOH-VOL -OPENREAD·WRITE/READ·MODIFY·WRITE CYCLEV'"--t;RAS ~I'A'CASVIL -VIH-VIL -tRCD'RWCtRAStRSHtCASDOUT VOH - OPEN Valid DataVOL-~,,~}-VIH- /Addresses V IL -~WEVIH-VIL -LtCACDIN~~~~tOFF~:~=~valisa;wa~ "H", "L" = Don't Care97

• DYNAMIC RAM· MSM3764AAS/RS •• ----------------RAS ONLY REFRESH TIMING(CAS: VIH,WE & DIN: Don't care)Addresses~RAH~tASR~:~ _~ Row AddressDOUTVOH -VOLOPEN~ "H", "L" = Don't CarePAGE MODE READ CYCLE~~~~~~--~~-tRAS~~~~~~~~~~~CASVIH­Adres,es V I L -DOUT VOH-___ _m=~~~--~~~--~s)r--~~-t-R~-H-~~==~ .. H .. ,"L .. = Don't Care98

----------------..... DYNAMIC RAM· MSM3764AAS/RS •PAGE MODE WRITE CYCLE~----------tRAS----------~Addresses vVIH- ,/N11O/v"W"-T1IL-~~·~~~~·~~r~~~~4~~WEV I H - ,7777 Im'77"J':mIllVIL-~~~~~~~~""~~~I'"'rn>~~~~~~~~~""~~~~""~~"H", "L" = Don't CarePAGE MODE, READ·MODIFY·WRITE CYCLEAddresses V I HVIL---OPEN---

• DYNAMIC RAM· MSM3764AAS/RS •• ----------------HIDDEN REFRESHAddressesDOUTv::W~.RA~~ ______ ---T'I@'I(,'lIAVOL---OPEN ~ Valid Data 5-~ "H", "L" = Don't CareDESCRIPTIONAddress Inputs:A total of sixteen binary input address bits are requiredto decode any 1 of 65536 storage cell locations withinthe MSM3764A. Eight row·address bits are establ ishedon the input pins (AD ~A,) and latched with the RowAddress Strobe (FiASl. The eight column-addressbits are established on the input pins and latched withthe Column Address Strobe (CAS). All input addressesmust be stable on or before the falling edge of RAS.CAS is internally inhibited (or "gated") by RAS topermit triggering of CAS as soon as the Row AddressHold Time (tRAH) specification has been satisfied andthe address inputs have been changed from row-addressesto column-addresses.Write Enable:The read mode or write mode is selected with the WEinput. A logic high (1) on WE dictates read mode;logic low (0) dictates write mode. Data input is disabledwhen read mode is selected.Data Input:Data is written into the MSM3764A during a write orread-write cycle. The last falling edge of WE or CAS isa strobe for the Data In (DIN) register. In a writecycle, if WE is brought low (write mode) before CAS,DIN is strobed by CAS, and the set-up and hold timesare referenced to CAS. I n a read-write cycle, WE willbe delayed until CAS has made its negative transistion.Thus DIN is strobed by WE, and set-up and hold timesare referenced to WE.Data Output:The output buffer is three-state TTL compatible witha fan-out of two standard TTL loads. Data-out is thesame polarity as data-in. The output is in a high impedancestate until CAS is brought low. In a read cycle,or read-write cycle, the output is valid after tRAC fromtransition of RAS when tRCD (max.) is satisfied, orafter tCAC from transition of CAS when the transitionoccurs after tRCD (max.l. Data remain valid until CASis returned to a high level. In a write cycle the identicalsequence occurs, but data is not valid.Page Mode:Page-mode operation permits strobing the row-addressinto the MSM3764A while maintaining RAS at a logiclow (0) throughout all successive memory operations inwhich the row-address doesn't change. Thus the powerdissipated by the negative going edge of RAS is saved.Further, access and cycle times are decreased becausethe time normally required to strobe a new row-addressis eliminated.Refresh:Refresh of the dynamic memory cells is accompl ishedby performing a memory cycle at each of the 128 rowaddresses(Ao -A.) at least every two milliseconds.During refresh, either VIL or VIH is permitted for A,.RAS only refresh avoids any output during refreshbecause the output buffer is in the high impedancestate unless CAS is brought low. Strobing each of 128row-addresses with RAS will cause all bits in each rwoto be refreshed. Further RAS-only refresh results in asubstantial reduction in power dissipation.Hidden Refresh:RAS ONLY REFRESH CYCLE may take place whilemaintaining valid output data. This feature is referredto as Hidden Refresh.Hidden Refresh is performed by holding CAS as V I Lfrom a previous memory read cycle.100

----------------..... DYNAMIC RAM· MSM3764AAS/RS •TYPICAL CHARACTERISTICSAccess time from RAS:> (Relative value) v.s. VCCo 1.4lriIIt5 1.2>uc3 1.0~U~ 0.8u«yTa; 25°CtRCO: min"- ~""' r-.....4.0 4.5 5.0 5.5 6.0VCC [V]«ICCl (tRAS: Constant)50 V.s. VCC~--~~.----r---.JS 40r---+---~~~~~L __ L __ ~~~~~tR~C ; 1000 ns4.0 4.5 5.0 5.5 6.0VCC[V]U 1.4°U1NII 1.2t::. '"u« 1.0..a:......Ciit::. 0.8u«Access fime from RAS(Relative value) v.s. TaVCC; 5.0VtRCO: min./ VV"..a:o 75ICCl (tRAS: Constant)O v.s. Cycle rate5 r--~-.--.--,Ta; 25°C«E 40r---+----r---.~ru345Cycle Rate (l/tRC) [MHz]Access time from CAS:> (Relative value) v.s. VCC0 1.4lritRCO: maxIIu 1.2~u«a: 1.0...... ..Ta; 50°CU Ta; 25°Cu 0.8Ta ; O°C>u«..a:4.0 4.5 5.0 5.5 6.0VCC [V]«JSC0''::;EQ)a.0u50403020ICCl (tRAS: Constant)v.s. TaVCC - 5.5V ;1tRAS; 120 ns-tR C; 220 flSItR C; 260 nstRo 75'1tR C; 330 nsItR C; 500 nsIC; 1000 ns101

• DYNAMIC RAM· MSM3764AAS/RS .----------------50 ICCl (tRP: Constant) v.s. VCCTa = 25°C~ tRC = 220 ns..§.. 40 tRC = 260 ns~--+---~~~~ I§ tRC = 330 ns.;:::; I~ 30~-"='_b"",..'9'---:::;a,.-tRC = 500 ns8. IS? tRC = 1000 nsU 20~~ .. ~=r--~--~u5.0

_______________ --11. DYNAMIC RAM· MSM3764AAS/RS •ICC3 (tRAS: Constant) v.s. VCC40~oS30a.>13>u.CJ!!' 10MUU04.0 4.5 5.0 5.5VCC[V]ICC3 (tRP: Constant) v.s. VCC40~ Ta = 25°CtRC = 220 nsoS~=260nsa; 30tRC = 330 ns13> tRG = 500 nsutR = 1000 ns. 30 I--'-'-'--T---+--c:::II"""""-:::VCC = 5.0V~ VCC = 4.5V~ 20~~~~~~--+---~'"~'ta: 10 I---+----t-----/----iMUUO~ __ ~ __ ~ ____ ~ __ ~1 2 3 4 5Cycle Rate (1/tRC) [MHz]~ 40«E~a; 3013>U'"...-~a.>a: 10MUUoICC3 (tRAS: Constant) v.s. TaVCC - 5.5VtRAS= 120ns-otRI C = 220 nsItR C = 260 nsItR C = 330 nsIt~C = 500 nstR C = 1000 ns75'1~40E..a.> 3013>u.a: 10MUUoICC3 (tRP: Constant) V.5. TaVCC - 5.5VtRP = 90 ns!~-tFi!R!RtR'- -o 25 50Ta rC]75C = 220 nsC = 260 nsC = 330 nsC = 500 nsC = 1000 ns103

• DYNAMIC RAM· MSM3764AAS/RS .-----------------:?E~t3 '">()'" Cle:. '"ICC4 (tcp: Constant) v.s. Ta50c; 30 r-.... ;;;:::±---+--=T-IClrf.

----------------...... DYNAMIC RAM· MSM3764AAS/RS •Address Input v.s. VccAddress Input v.s. Ta:> 2.0Q;>~ 1.5....~Co.=1.02:Q;>~....~Coc:vdc= 5.bvVIH mi~IVIL max4.0 4.5 5.0 5.5 6.0VCC[V]o 25 50 75Ta [0C]Data Input v.s. VCCData Input v.s. Ta:> 2.0~~ 1.5 f---::;;oo'l!5~-t--+---I....~Coc: 1.0 f---t---t--+---i:> 2.0OJ>~ 1.5....~Coc:1.0VJc= 5.bvVIH mi~VIL max4.0 4.5 5.0 5.5 6.0VCC[V]o 25 50 75Ta rOC]Clock Input v.s. VCCClock Input v.s. Ta2: 2.0Q;>~ 1.5.....~Co.=1.0Ta = 25°C:> 2.0> '"~ 1.5....~Coc:1.0vbc = 5.6v~IH mi~tVIL max~ ..4.0 5.0 5.5 6.0VCC [V]o 25 50 75Ta rOC]105

• DYNAMIC RAM· MSM3764AAS/RS •• ----------------VCC = 5.5VTa = 25°C50 ns/div. .RAS/CAS CYCLE LONG RAS/CAS CYCLE RASONL Y CYCLE PAGE MODE CYCLERASCAS140ICC 120[rnA]100~-~ ~iJ I\-~ ~--~iJ ~IJ ,-f\'ri"\..~-806040200R11~ -~ ~\I II'\I ~'I'"~ ~106

---------------______ DYNAMIC RAM· MSM3764AAS/RS _MSM3764A Bit MAP (Physical·Decimal)[A7 column - "H"][A7 column - "L"]OPIN 16 \63 62255 255191 190255 25563 62254 254191 190254 25463 62253 253191 190253 25363 62252 252191 190252 25263 62251 251I 0255 255129 128255 2551 0254 254129 128254 254I 0253 253129 128253 2531 0252 252129 128252 252I 0251 251r---r-~~f-e-f-e-f-e-~~64 65255 255192 193255 25564 65254 254192 193254 25464 65253 253192 193253 25364 65252 252192 193252 25264 65251 251126 127255 255254 25525! 255126 127254 254254 255254 254126 127253 253254 255253 253126 127252 252254 255252 252126 127251 25163 62~ ~ 191 190~ ~63 62126 126191 190126 12663 62125 125191 190125 12563 62124 124191 190124 12463 62~ ~1 0127 127129 128127 1271 0126 126129 128126 1261 0125 125129 128125 1251 0124 124129 128124 1241 0123 123r--r"r-~~r~~~64 65~ ~ 192 193127 12764 65126 126192 193126 12664 65~ 125192 i93~ ~64 65~ ~192 193124 12464 65123 123126 127127 127254 255127 127126 127126 126254 255126 126126 127125 125254 255125 125126 127124 124254 255124 124126 127123 123(Column)191 190132 13263 62~~~~63 62130130191 19013013063 62~~191 190129129129 128132 1321 0131 131129128131 1311 01301301291281301301 0129 12912912812912919219313213264 65·131 131192 1!i3131 13164 6513013019219313013064 65129 129192 19312912964 65128128254 255132132126127131 131254 255131 131126 127130130254 255130130126 127129 129254255129129126 127128128254• Refresh Address?IUefreSh Addrcss_(63~O) I 11\ (64-127) ~D I L-.LIn 02 01 01 02 Din(Poso!lve) 0 (Negative)1~ 1~~ 12~ 12g f-ef;g;"700129 128 ~ 192 193OJ me ll,1J1-+-191190~~63 62~~191 190~~63 62~2191'1902 2~~1 11291284 4o31291283 312o2129 1282 2o11921934 464 653 31921933 364 652 21921932 264 651 1254 2554 4126 1273 3254 2552 3126 1272 2\:Pin 8(Row)Cell: : ~~~~~~~Sr!~(~:-jl~al)B Sub Amp (C = Number of 8us Line)Word DriverSense Amp107

OKI semiconductorMSM41256AS/RS262144-BIT DYNAMIC RANDOM ACCESS MEMORY < Page Mode Type>GENERAL DESCRIPTIONThe Oki MSM41256 is a fully decoded, dynamic NMOS random access memory organizad as 262144 one-bit words.The design is optimized for high-speed, high performance applications such as mainframe memory, buffer memory,peripheral storage and environments where low power dissipation and compact layout is required.Multiplexad row and column address inputs permit the MSM41256 to be housed in a standard 16-pin DIP, Pin-outsconform to the JEDEC approved pin out.The MSM41256 is fabricated using silicon gate NMOS and Oki's advanced Double-Layer Polysilicon process. Thisprocess, coupled with single-transistor memory storage cells, permits maximum circuit density and minimal chipsize. Dynamic circuitry is employad in the design, including the sense amplifiers.Clock timing requirements are noncritical, and power supply tolerance is very wide. All inputs and output are TTLcompatible.FEATURES.262144 x 1 RAM, 16-pin package.• Silicon·gate, Double Poly NMOS, single transistor cell• Row access time,120 ns max. (MSM41256-12AS/RS)150 ns max. (MSM41256-15AS/RS)200 ns max. (MSM41256-20AS/RS)• Cycle time,230 ns min. (MSM41256-12AS/RS)260 ns min. (MSM41256-15AS/RS)330 ns min. (MSM41256-20AS/RS)• Low power:385 mW active (MSM41256-12AS/RS)360 mWactive (MSM41256-15AS/RS)305 mWactive (MSM41256-20AS/RS)28 mW max. standby• Single +5V Supply, ±10% tolerance• All inputs TTL compatible, low capacitive load• Three-state TTL compatible output• "Gated" 'CAS• 4 ms/256 refresh cycles• Common I/O capability using "Early Write"operatiori• Output unlatchad at cycle and allows extendad pageboundary and two-dimensional chip select• Read-Modify-Write, RAS-only refresh, and PageMode capability• On-

---------------_____ DYNAMIC RAM· MSM41256AS/RS _FUNCTIONAL BLOCK DIAGRAMColumnAddressBuffersWEAo .... A,DoutVCCVSS-RowAddressBuffersyWordDriversOn chip VBBMemoryCellsDinABSOLUTE MAXIMUM RATINGS (See Note)Rating Symbol Value UnitVoltage on any pin relative to VSS VIN, VOUT -1 to +7 VVoltage on VCC supply relative to VSS Vee -1 to +7 VOperating temperature Topr o to 70 °eStorage temperature T stg -55 to +150 °ePower dissipation Po 1.0 WShort circuit output current 50 mANote: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operationshould be restricted to the conditions as detailed in the operational sections of this data sheet. Exposureto absolute maximum rating conditions for extended periods may affect device reliability.RECOMMENDED OPERATING CONDITIONS(Respect to VSS)Parameter Symbol Min. Typ. Max. UnitSupply VoltageVr:r: 4.5 5.0 5.5 VVSS 0 0 0 VInput High Voltage, all inputs VIH 2.4 6.5 VInput Low Voltage, all inputs VIL -1.0 0.8 VOperatingTemperatureoOe to +70 o e109

• DYNAMIC RAM· MSM41256AS/RS •• ----------------DC CHARACTERISTICS(Recommended operating conditions unless otherwise noted.)Parameter Symbol Min. Max. UnitOPERATING CURRENT" MSM41256·12 70Average power supply current MSM41256·15 ICCl 65 mA(RAS, CAS cycling; tRC = min.) MSM41256·20 60STANDBY CURRENTPower supply current ICC2 5.0 mA(RAS = CAS = VIH)REFRESH CURRENT MSM41256·12 60Average power supply current MSM41256·15 ICC3 55 mA(RAS cycling, CAS = VIH; tRC = min.) MSM41256·20 50PAGE MODE CURRENT" MSM41256·12 60Average power supply current MSM41256·15 ICC4 55 mA(RAS = VIL, CAS cycling; tpc = min.) MSM41256·20 50INPUT LEAKAGE CURRENTInput leakage current, any input(OV ~ VIN ~ 5.5V, all other pins notunder test = OV)III -10 10 J.

--------------...:.--..... DYNAMIC RAM· MSM41256AS/RS •AC CHARACTERISTICSNotes 1, 2, 3Under RecommendedOperating conditionsParameter Symbol UnitsRefresh period tREF msRandom read or write cycle time tRC nsRead-write cycle time tRWC nsPage mode cycle time tpc nsAccess time from RAS tRAC nsAccess time from CAS tCAC nsOutput buffer turn-off delay tOFF nsTransition time tT nsRAS precharge time tRP nsRAS pulse width tRAS nsRAS hold time tRSH nsCAS precharge time tcp nsCAS pulse width tCAS nsCAS hold time tCSH nsRAS to CAS delay time tRCD ns~to RAS precharge time tCRP nsRow Address set-up time tASR nsRow Address hold time tRAH nsColumn Address set-up time tASC nsColumn Address hold time tCAH nsColumn Address hold timereferenced to R AStARRead command set-up time tRCS nsRead command hold time tRCH nsWrite command set-up time twcs nsWrote command hold time tWCH nsWrite command hold timereferenced to RAStwCRWrite command pulse width twp nsWrite command to RAS lead time tRWL nsWrite command to CAS lead time tCWL nsData-in set-up time tDS nsData-in hold time tDH nsData-in hold time referencedto'RAStDHRCAS to WE delay tCWD nsRAS to WE delay tRWD nsRead command hold timereferenced to RAStRRHnsnsnsnsMSM41256-12 MSM41256-15 MSM41 256-20Min. Max. Min. Max. Min. Max.4 4 4230 260 330255 325 410130 145 190120 150 20060 75 1000 40 0 40 0 503· 50 3 50 3 50100 100 120120 10,000 150 10,000 200 10,00060 75 10060 60 8060 10,000 75 10,000 100 10,000120 150 20025 60 25 75 30 1000 0 00 0 020 20 250 0 035 45 5595 120 1550 0 00 0 00 0 040 45 55100 120 15540 45 5540 60 8040 60 800 0 040 45 55100 120 15540 75 100100 150 20020 20 25Note4,65,67888111

• DYNAMIC RAM· MSM41256AS/RS .----------------NOTES: 1)2)3)4)5)6)7)8)An initial pause of 100 J.LS is required after power-up followed by any 8 RAS cycles (Examples; RASonly) before proper device operation is achieved.AC measurements assume tT = 5 ns.VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals. Also, transitiontimes are measured between VIH and VIL.Assumes that tRCD < tRCD (max.).If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase bythe amount that tRCD exceeds the values shown.Assumes that tReD < tRCD (max.)Measured with a load circuit equ ivalent to 2 TTL loads and 100 pF.Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specifiedas a reference point only; if tRCD is greater than the specified tRCD (max.) limit, then accesstime is controlled exclusively by tCAC.twcs, tCWD and tRWD are not restrictive operating parameters. They are included in the data sheetas electrical characteristics only; if twcs ~ twcs (min.), the cycle is an early write cycle and the aataout pin will remain open circuit (high impedance) throughout the entire cycle; if tCWD ~ tCWD(min.) and tRWD > tRWD (min.) the cycle is read-write cycle and the data out will contain data readfrom the selected cell; if neither of the above sets of conditions is satisfied the condition of the dataout (at access time) is indeterminate.READ CYCLE TIMING~-------------------tRC--------------------~~-------------tRAS------------~~VIH _ ---,I f-o------tAR .1 Ir--------iVIL -~Addresses VIH-VIL -I tRcsHVIH-~WEVIL-!---tCACtRAC1-VOH-DOUTOPENVOL-J tOFFValid Data~"H", "L" = Don't Care112

----------------...... DYNAMIC RAM· MSM41256AS/RS •WRITE CYCLE TIMING(EARLY WRITE)RAS vlH -VIL -CAS VIH -VIL -tRSH______ ~~==~~==~--r---tCAS----~k_~----~~AddressesVIH -VIL -WEVIH - /jVIL -DINVIH -VIL -DOUTVOH-VOL-~------tDHR------~OPEN~ "H", "L" = Don't CareREAD·WRITE/READ·MODIFY·WRITE CYCLE~ "H", "L" = Don't Care113

• DYNAMIC RAM· MSM41256AS/RS .1----------------RAS ONLY REFRESH TIMING(CAS: VIH,WE' & DIN: Don't care)-- VIH­RAS VIL-~RAH~Addresses ~:~_~ RowAddresstASRDOUTVOH -VOL -OPEN~"H", "L" = Don't CarePAGE MODE READ CYCLE~---------tRAS-----------..,VIH­Adresses V I L -~"H","L"=Don't Care114

___________________ DYNAMIC RAM· MSM41256AS/RS _PAGE MODE WRITE CYCLERASVIH -VIL -CASAddressesWEvlH -VIL -DIN VIH -VIL -~ "H", "L" = Don't CarePAGE MODE, READ-MODIFY-WRITE CYCLECAS VIH - --+-4----.1-.VIL -AddressesDINVIH­V I L -""""~;":"':''''""''''J.f~ "H", "L" = Don't Care115

• DYNAMIC RAM· MSM41256AS/RS .----------------HIDDEN REFRESHAddressesDOUTVIH-///,vlL -""//.

----------------..... DYNAMIC RAM· MSM41256AS/RS •>L!)IIUu2:u«IEUu2:u«!F>L!)IIu2:u«~Uu2:u«i:?1.41.2K1.00.80.64.01.41.2 t-...1.00.8Access time from RAS(Relative value) vs. VCCTa = 25°C'"~r---4.5 5.0 5.5VCC [V]Access time from CAS(Relative value) vs. VCCTa = 25°CtRCD; max.'" ~ 6.0'-...r---G 1.2'inNt: '" 1 .1u«5 1.0t.u« 0.9!F0.8G 1.2'inNt:'"1.1u«~ 1.0cct:u« i:? 0.90.8Access time from RAS(Relative value) vs. TaVCC = 5.0V./Vo/Access time from CAS(Relative value) vs. TaVCC = 5.0VtRCD; max.1/V~VV/,,/70/" V0.64.04.5 5.0 5.5 6.0VCC [V]0 25 50Ta rOc]70';{Ec:.,.0:;; '"c..sU!:l40ICCl vs. VCC';{.s..,06050c:40~Q)c..s 30U!:lTa = 25°CtRAS = 160 nSICCl vs. Cycle rateVCC = 5.5VI= 5.0VI= 4.5VD4.5 5.0 5.5 6.0VCC [V]102 3 4 5Cycle Rate (l/tRC) [MHz]117

• DYNAMIC RAM· MSM41256AS/RS .----------------60:t 55Sc:.;; o., e! 50Co..£.tl 4540VCC = 5.5VtRC = 260 nS......r--r--ICCl vs. Tao 704.0:t 3.5S>:-9"0c: 3.0~NU!:? 2.5Ta = 25°CVIH; max.2.0---VICC2 vs. VCC/'/4.0 4.5 5.0 5.5 6.0VCC [V]4.0:t 3.5S>:-9"0c:co3.0ENU9 2.5VCC = 5.5VVIH; maxICC2 vs. Ta~'"........ ~ ~ .......ICC3 vs. VCC60Ta = 25°CtRC = 260 nS:t 50S0;U> 40u-&~ 30~ VMU!:?20... //./2.0o 704.0 4.5 5.0 5.5 6.0VCC [V]D50:t45S0;u> u-& 40~!Mu!:?35VCC = 5.5VtRC = 260 nSICC3 vs. Tar-r-----:--60:t50S0; 40U> u.,'" co 302-

___________________ DYNAMIC RAM· MSM41256AS/RS _~.s5045(i;u>-"40enEo '"".u35!:?VCC = 5.5Vtpc = 145 nSICC4 vs. TaI"-..~..............r-- t-30o 25 50 70Ta lOC]2.5Address, Data Input vs. TaVCC = 4.5V2.5Address, Data Input vs. TaVCC = 5.5V~a;>--'~:JC.c2.0 2.01.5VIH min.~a;> 1.5--':;c.cVIL max.1.0 1.0VIH min.VIL max.T""""0.5 0.50 25 50 70 0 25 50 70Ta lOC]Ta lOC]Clock I ntJut vs. TaClock Input vs. Ta2.5 2.5VCC = 4.5V VCC = 5.5V2.0 2.0~ ~a;VIH min. a;>>1.51.5--'--':;:;c.c.cc1.0VIL1max.-f- 1.0VIH min.VIL max.0.50.5o 25 50 70 o 25 50 70Ta lOC]Ta lOC]119

• DYNAMIC RAM· MSM41256AS/RS .-....:.-----------___ _2.5Address, Data Input vs. V ccITa = 25°CClock Input vs. VCC2.5.---....... --..,--....:...0--...,2.02.01---+--+----1---1Ga;>Q)oJ...::>c..:1.51.0VIHm~-- ~ ~10- VIL max .a;j1.5 I--:::;.,..jo~~+----I---I1.0F---+--4.0 4.5 5.05.5 6.04.0 4.5 5.05.5 6.0VCC [V]VCC [V]~.su9TYPICAL CURRENT WAVEFORMSVCC =5.5VTa = 25°CRAS/CAS CYCLE LONG RAS/CAS CYCLE RAS ONLY CYCLE PAGE MODE CYCLERAS l- n ,\1-I.....CAS ... ....\1-lr I- I-1-1200150100500~I--~ ... IA 1 1& n ~, Aj,- ~ Iv I--In: 1-1" l"-I-' u- 1\ ..... r\. t- ...... 1---1 I\... l- \. P tor ~ r--- \~A100 nS/Div120

________ --:.. __________ DYNAMIC RAM ·MSM41256AS/RS _/[A8 column· "L"I/255 254 '129Ua 0 1 126 127255 255 255 255 255 255 255 256511 510 385 384 258 257 382 383255 255 255255 255511 510 ~ ~ ~258 ~ 382 383254 254 254 254~ ~ 254 254255 254 ~ ~ 0 1 126 127254 254 254 254 254 254 254 254255 254 129 128 0 1 126 127253 253 253 253 253 253 253 253511 510 t-;2e rm 258 257 382 383253 253 253 253 253 253 253~511 51Ci ~ 384 258 257 382 383252 252 252 252 252 252 252 252255 254 129 128 0 1 126 127252 252252 252 252 252~ ~255 254 129 128 0 1 126 127251 251 251 251 251 251 251 251MSM41256 Bit Map (Physical-Decimal)I\\ 0 Pin 16/[A8 column' "H"I\255 254 '129i2a 0 1 Us 1"127511 511 511 511 511 611~ ~385 384 258 257 382 383511 510511 511 511 511 511 511 511 511511 510 385 384 258 257 382 383510 510 510 510 510 510 510 510255 254 129 128 0 1 126 127510 510255 254510 510 510 510509 509 508 509 509 509 509 509129 129 0 1 ~*509 509 509 509511 510 385 384 258 257 382 383509 509511 510 385 384 258 257~~ 382508 508 508 508 508 508 508 5082s5 2s4 129 128 0 1 126 127~ ~ 509 508 508 509 508 508255 254 129 128 0 1 126 127~ 2!!Z507 507 507 507 507 507(Column)255 254 t-;2e rm 0 1 126 1274 4 44 4 4 4255 254 I;2e ~0 1 126 1273 3 3 33 3 3 3511 510 ~ ~258 257 382 3833 3 3 3 3 3r2-r2-511 510 385 384 258 257 382 3832 2 2 2 2 2r--2 ~255 254 129 1280 1 126 1272 2 2 22 2 2 2255 254 t-;2e ~o 1 126 1271 1 1 1 1 1 1 1511 510 385384 256 257 382 38351: 51~ ~~ 2~ 25~ 38~ 38~o 0 ~r---.!!. 0 0 0 0255 254 129 128 0 1 126 1270000 0000nlTIJ -®-I I I~ Address ---J / "'- Refresh Addres: I'(255-1281;/' ,\ (O~ 1271Din 012 012 r5rn(Positive)(Negative)255 254 129 129 0 1 126 127260 260 260 260 260 260 260 260255 254 129 128 0 1 126 127259 259 259 259 259 259 259 259511 510 385 384 258 257 382 383259 259 259 259 259 259 259 259511 510 385 384 258 257 382 383258 258 258 258 258 258 258 258255 254 129 128 0 1 126 127258 258 258 258 258 258 258 258255 254 129 128 0 1 126 127~ ~257 257 257 257 257 257511 510 385 384 n 258 257 382 383257 257 257 257 257 257 257 257511 510 385 384 258 257 382 383258 258 256 256 258 256 256 258255 254 129 128 0 1 126 127258 258 258 258 258 256 258 258[IT LD 4} I I I r:::=:JRefresh Address -; \ Refresh Addre ..(255-1281 (O~ 1271Din D. 0;; rnn(Positive)(Negative)A8~: Sense Amp.~ : Sub Amp.121

OKI semiconductorMSM41256JS262144-BIT DYNAMIC RANDOM ACCESS MEMORY < Page Mode Type>GENERAL DESCRIPTIONThe Oki MSM41256 is a fully decoded, dynamic NMOS random access memory organized as 262144 one-bit words.The design is optimized for high-speed, high performance applications such as mainframe memory, buffer memory,peripheral storage and environments where low power dissipation and compact layout is required.Multiplexed row and column address inputs permit the MSM41256 to be housed in a standard 18·pin PLCC, Pin·outsconform to the JEDEC approved pin out.The MSM41256 is fabricated using silicon gate NMOS and Oki's advanced Double-Layer Polysilicon process. Thisprocess, coupled with single·transistor memory storage cells, permits maximum circuit density and minimal chipsize. Dynamic circuitry is employed in the design, including the sense amplifiers.Clock timing requirements are noncritical, and power supply tolerance is very wide. All inputs and output are TTLcompatible.FEATURES.262144 x 1 RAM, 18-pin PLCCpackage • All inputs TTL compatible, low capacitive load• Silicon-gate, Double Poly NMOS, single transistor cell • Three-state TTL compatible output• Row access time,120 nsmax. (MSM41256-12JS)150 ns max. (MSM41256-15JS)• Cycle time,230 ns min. (MSM41256-12JS)260 ns min. (MSM41256·15JS)• Low power: 385 mW/360 mW active28 mW max. standby• Single +5V Supply, ± 1 0% tolerance• "Gated" CAS• 4 ms/256 refresh cycles• Common 110 capabil ity using "Early Write"operatio,;• Output unlatched at cycle and allows extended pageboundary and two-dimensional chip select• Read-Modify-Write, RAS-only refresh, and PageMode capability• On-chip latches for Addresses and Data-in• On-chip substrate bias generator for highperformancePIN CONFIGURATIONDin A, VSS CASWERASNC2 1 1817Pin NamesFunctionDout Ao - A" Address InputsRASRow Addr.s. StrobeA~CASColumn Addres. StrobeNCWE"Write EnableA~ Din Data InputA: Dout Data OutputVCCPower (+5V)VSSGround (OV)NCNo ConnectionA* A* A*1Vee 7 5 • Refresh Addr.ss122

-----------------_____ DYNAMIC RAM· MSM41256JS _FUNCTIONAL BLOCK DIAGRAMeolumnAddressBuffersWEAo -A,DoutVeeVSS-RowAddressButiersyWordDriv·ersOn chip VBBMemoryCellsDinABSOLUTE MAXIMUM RATINGS (See NotelRating Symbol Value UnitVoltage on any pin relative to VSS VIN. VOUT -1 to +7 VVoltage on Vee supply relative to VSS Vee -1 to +7 VOperating temperature Topr o to 70 °eStorage temperatu re T stg -55 to +150 °ePower dissipation Po 1.0 WShort circuit output current 50 mANote: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional opera·tion should be restricted to the conditions as detailed in the operational sections of this data sloeet. Exposureto absolute maximum rating conditions for extended periods may affect device reliability.RECOMMENDED OPERATING CONDITIONS(Respect to VSSIParameterSymbol Min. Typ. Max. UnitSupply VoltageVee 4.5 5.0 5.5 VVSS 0 0 0 VInput High Voltage. all inputs VIH 2.46.5 VInput Low Voltage, all inputs VIL -1.0 0.8 VOperatingTemperatu reooe to +70 o e123

• DYNAMIC RAM·MSM41256JS •• -----------------DC CHARACTERISTICS(Recommended operating conditions unless otherwise noted.)Parameter Symbol Min. Max. UnitOPERATING CURRENT"MSM41256-12 70Average power supply currentICC1(RAS, CAS cycling; tRC = min.) MSM41256-15 65 mASTANDBY CURRENTPower supply current ICC2 5.0 mA(RAS = CAS = VIH)REFRESH CURRENT MSM41256-12 60Average power supply current ICC3 mA(RAS cycling, CAS = VIH; tRC = min.! MSM41256-15 55PAGE MODE CURRENT" MSM41256-12 60Average power supply current ICC4 mA(RAS = VIL, CAS cycling; tpc = min.) MSM41256-15 55INPUT lEAKAGE CURRENTInput leakage current, any input(OV ~ V IN ~ 5.5V, all other pins notunder test = OV)III -10 10 jlAOUTPUT lEAKAGECURRENT(Data out is disabled, ILO -10 10 jlA(OV ~ VOUT ~ 5.5V)OUTPUT LEVELSOutput high voltage (tOH = -5 mAlOutput low voltage (tOl = 4.2 mAlVOH 2.4 VVOL 0.4 VNote": ICC is dependent on output loading and cycle rates. Specified values are obtained with the output open.CAPACITANCE(T a = 25° C, f = 1 MHz)ParameterInput Capacitance (Ao - AI' DIN)Input Capacitance (RAS, CAS, WE)Output Capacitance (DOUT)Note: Capacitance measured with Boonton Meter.SymbolCIN1CIN2COUTMax.Unit6 pF7 pF7 pF124

-----------------_____ DYNAMIC RAM· MSM41256JS _AC CHARACTERISTICSNotes 1, 2, 3Under RecommendedOperating conditionsParameter Symbol UnitsRefresh period tREF msRandom read or write cycle time tRC nsRead-write cycle time tRWC nsPage mode cycle time tpc nsAccess time from RAS tRAC nsAccess time from CAS tCAC nsOutput buffer turn-off delay tOFF nsTransition time tT nsRAS precharge time tRP ns~~RAS pulse width tRAS-nsRAS hold time tRSH ns-~f---=----CAS precharge time tcp nsCAS pulse width tCAS nsCAS hold time tCSH nsRAS to CAS delay time tRCD nsCAS to RAS precharge time tCRP nsRow Address set-up time tASR nsRow Address hold time tRAH nsColumn Address set-up time tASC nsColumn Address hold time tCAH nsColumn Address hold timereferenced to R AStARRead command set-up time tRCS nsRead command hold time tRCH nsWrite command set-up time twcs nsWrite command hold tIme tWCH nsWrite command hold timereferenced to RAStWCRWrite command pulse width twp nsWrite command to RAS lead time tRWL nsWrite command to CAS lead time tCWL nsData-in set-up time tDS nsData-in hold time tDH nsData-in hold time referencedto RAStDHRCAS to WE delay tCWD nsRAS to WE delay tRWD nsRead command hold timereferenced to R AStRRHnsnsnsnsMSM41256-12 MSM41256-15NoteMin. Max. Min. Max.4 4230 260255 325130 145120 150 4,660 75 5,60 40 0 403 50 3 50100 100120 10,000 150 10,00060 7560 6060 10,000 75 10,000120 15025 60 25 75 70 00 020 200 035 4595 1200 00 00 0 840 45100 12040 4540 6040 600 040 45100 12040 75 8100 150 820 20125

_ DYNAMIC RAM· MSM41256JS _...._-----------------NOTES: 1121314151617181An initial pause of 1001's is required after power-up followed by any 8 RAS" cycles (Examples; RASonly I before proper device operation is achieved_AC measurements assume tT = 5 ns.VIH (Min-l and VIL (Max.1 are reference levels for measuring timing of input signals. Also, transitiontimes are measured between VIH and VIL.Assumes that tRCD < tRCD (max.1.If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase bythe amount that tRCD exceads the values shown.Assumes that tRCD < tRCD (max-lMeasured with a load circuit equivalent to 2 TTL loads and 100pF.Operation within the tRCD (max-l limit insures that tRAC (max-l can be met. tRCD (max-l is specifiedas a reference point only; if tRCD is greater than the specified tRCD (max-l limit, then accesstime is controlled exclusively by tCAC.twcs, tCWD and tRWD are not restrictive operating parameters. They are included in the data sheetas electrical characteristics only; if twcs ~ twcs (min-l, the cycle is an early write cycle and the oataout pin will remain open circuit (high impedance I throughout the entire cycle; if tCWD ~ tCWD(min-l and tRWD > tRWD (min-l the cycle is read-write cycle and the data out will contain data readfrom the selected cell; if neither of the above sets of conditions is satisfied the condition of the dataout (at access timel is indeterminate.READ CYCLE TIMINGtRCVIH-AAS VIL -tARtRAS--"\CASVIH -VIL -tRSHtCAStCSH-VIH­Addresses VI L -DOUTI tRCS~VIH-~VIL - !---tCAC1~·~---------tRAC--~------~ J tOFFVOH- OPEN r-V-a-lid-D-a-ta-i>------VOL-~"H", "L" = Don't Care126

-----------------__ DYNAMIC RAM 'MSM41256JS _WRITE CYCLE TIMING(EARLY WRITE)RASVIH -VIL -CAS VIH -VIL -tRSH___ --4-1==~~f=~-I-tCAS------i -+--+ __ -'-__.AddressesVIH -VIL -WEVIH - :0VIL -DINVIH -VIL -DOUTVOH-VOLr------tDHR------~OPEN~ "H", "L" = Don't CareREAD·WRITE/READ·MODIFY-WRITE CYCLE~ "H", "L" = Don't Care127

• DYNAMIC RAM ·MSM41256JS .I-------------~---RAS ONLY REFRESH TIMING(CAS: VIH,VlE" & DIN: Don't care)-- VIHRAS VILt~AH~Addresses ~:~_~ RowAddresstASRDOUTVOH -VOL -OPEN~ "H", "L" = Don't CarePAGE MODE READ CYCLE~-----------tRAS-----------~~"H","L"= Don't Care128

---------------------DYNAMIC RAM, MSM41256JS _PAGE MODE WRITE CYCLE~ "H", "L" = Don't CarePAGE MODE, READ-MODIFY-WRITE CYCLERASVIH­VIL -CAS VIH - --H---.

• DYNAMIC RAM· MSM41256JS •• ------------------HIDDEN REFRESHAddressesDOUT~ "H", "L" = Don't CareDESCRIPTIONAddress Inputs:A total of eighteen binary input address bits are requiredto decode any 1 of 262144 storage cell locationswith in the MSM41256 Nine row-address bits are establishedon the input pins (Ao - A,) and latched withthe Row Address Strobe (RAS). The Nine columnaddressbits are established on the input pins andlatched with the Column Address Strobe (CAS). Allinput addresses must be stable on or before the fallingedge of RAS, CAS is internally inhibited (or "gated")by RAS to permit triggering of CAS as soon as the RowAddress Hold Time (tRAH) specification has beensatisfied and the address inputs have been changedfrom row-addresses to column-addresses.Write Enable:The read mode or write mode is selected with the WEinput. A logic high (1) on WE dictates read mode;logic low (0) dictates write mode. Data input is disabledwhen read mode is selected.Data Input:Data is written into the MSM41256 during a write orread-write cycle. The last falling edge of WE or CAS isa strobe for the Data In (DIN) register. In a writecycle, if WE is brought low (write mode) before CAS,DIN is strobed by CAS, and the set-up and hold timesare referenced to CAS. I n a read-write cycle, WE willbe delayed until CAS has made its negative transition.Thus DIN is strobed by WE, and set-up and hold timesare referenced to WE.Data Output:The output buffer is three-state TTL compatible witha fan-out of two standard TTL loads. Data-out is thesame polarity as data-in. T/1e output is in a high impedancestate until CAS is brought low. In a read cycle,Or read-write cycle, the output is valid after tRAC fromtransition of RAS when tRCD (max.) is satisfied, orafter tCAC from transition of CAS when the transitionoccurs after tRCD (max.). Data remain valid until CASis returned to a high level. In a write cycle the identicalsequence occurs, but data is not valid.Page Mode:Page-mode operation permits strobing the row-addressinto the MSM41256 while maintaining RAS at a logiclow (0) throughout all successive memory operations inwhich the row-address doesn't change. Thus the powerdissipated by the negative gOing edge of RAS is saved.Further, access and cycle times are decreased becausethe time normally required to strobe a new row-addressis eliminated.Refresh:Refresh of the dynamic memory cells is accompl ishedby performing a memory cycle at each of the 256 rowaddresses(Ao - A,) at least every four milliseconds.During refresh, either VIL or VIH is permitted for A,.FfAS only refresh avoids any' output during refreshbecause the output buffer is in the high impedancestate unless CAS is brought low. Strobing each of 256row-addresses with FfAS will cause all bits in each rowto be refreshed. Further RAS·only refresh results in asubstantial reduction in power dissipation.Hidden Refresh:FfAS ONLY REFRESH CYCLE may take place whilemaintaining valid output data. This feature is referredto as Hidden Refresh.Hidden Refresh is performed by holding CAS as VILfrom a previous memory read cycle.130

------------------11. DYNAMIC RAM ·MSM41256JS •q;IP-=J4}\\MSM41256 Bit Map (Physical-Decimal)I\//[A8 column' "L")[AB column -\"Hill/ \I Refresh Address255 254 129 128 0 1 126 127 255 254 129 1280 1 126 127255 255 255 255 255 255 255 255 511 511211.511 511 511 511~511 510 385 384 256 257 382 383 511 510 385 384256 257 382 383255 255 255 255255 255 511 511 511 511511 511 511 511511 510 385 384 ~ ~ 382 383 511 510 385 384256 257 382 383254 254 254 254~ ~ 254 254 510 510 510 510510 510 510 510255 254 129 128 0 1 126 127 255 254 129 1280 1 126 127254 254 254 254 254 254 254 254 510 510 510 510510 510 510 510255 254 129 128 0 1 126 127 255 254 129 1280 1 126 127253 253 253 253 253 253 253 253 509 509 509 509509 509 509 509511 510 129 128 ~ 257 382 383 511 510 385 384256 257 382 383253 253 253 253 253 253 253 253 509 509 509 509509 509 509 509511 510 385 384 256 257 382 383 511 510 385 384256 257 382 383252 252 252 252 252 252 252 252 508 508 508 508508 508 508 508255 254 129 128 0 1 126 127 255 254 129 1280 1 126 127252 252 252 252 252 252 252 252 508 508 508 508508 508 508 508255 254 129 128 0 1 126 127 255 254 129 1280 1 126 127251 251 251 251 251 251 251 251~ ~507 507507 507 507 507255 254 129 128 0 1 126 127 255 254 129 1280 I 126 1274 4 4 4 4 4 4 4 260 260 260 260260 260 260 260255 254 129 ~ 0 1 126 127 255 254 129 1280 1 126 1273 3 3 3 3 3 3 3 259 259 259 259259 259 259 259511 510 385 384 256 257 382 383 511 510 385 384256 257 382 3833 3~ .2. 3 3 3 3 259 259 259 259259 259 259 259511 510 384 256 257 382 383 511 510 385 384256 257 382 3832 2 2 2 2 2 2 2 258 258 258 258258 258 258 258255 254 129 128 0 1 126 127 255 254 129 1280 1 126 1272 2 2 2 2 2 2 2 258 258 258 258258 258 258 258255 254 129 128 0 1 126 127 255 254 129 1280 1 126 1271 1 I 1 1 1 1 1 257 257 257 257257 257 257 257511 510 385 384 256 257 382 383 511 510 385 384256 257 382 383£i1 1 1 1 1 1 1 1 257 257 257 257257 257 257 257511 510 385 384 256 257 382 383 511 510 385 384256 257 382 3830 0 0 0 0 0 0 0 256 256 256 256256 256 256 256255 254 129 128 0 1 126 127 255 254 129 1280 1 126 1270 0 0 0 0 0 0 0 256 256 256 256256 256 1§§. 1§!!I o::::rilJI IRefresh Addres:1255~ 1281 10-1271Din(Positive)- -D" 012 Din(Negative)1255~ 1281Din(Positive)D"--0- I I I L::J~ Refresh Address(0-1271- 0 34 '[)I'i1(Negative)(Column)ABCellA '" Row Address (Decimal)B '" Column Address (Decimal)~: Sense Amp.~ Sub Amp.131

OKI semiconductorMSM41 256AAS/RS262,144-BIT DYNAMIC RANDOM ACCESS MEMORY GENERAL DESCRIPTIONThe Oki MSM41256A is a fully decoded, dynamic NMOS random access memory organized as262144 one-bit words. The design is optimized for high-speed, high performance applications suchas mainframe memory, buffer memory, peripheral storage and environments where low power.dissipationand compact layout is required.Multiplexed row and column address inputs permit the MSM41256A to be housed in a standard16 pin DIP. Pin-outs conform to the JEDEC approved pin out. Additionally, the MSM41256A offersnew functional enhancements that make it more versatile than previous dynamic RAMs."CAS-before-RAS" refresh provides an on-Chip refresh capability.The MSM41256A is fabricated using silicon gate NMOS and Oki's advanced VLSI Polysiliconprocess. This process, coupled with single-transistor memory storage cells, permits maximum circuitdensity and minimum chip size. Dynamic circuitry is employed in the design, including the senseamplifiers.Clock timing requirements are noncritical, and power supply tolerance is very wide. All inputs andoutput are TTL compatible.FEATURES• 262,144 x 1 RAM, 16 pin package• Silicon-gate, Double Poly NMOS, singletransistor cell• Row access time:100 ns max (MSM41256A-1 OASIRS)120 ns max (MSM41256A-12AS/RS)150 ns max (MSM41256A-15AS/RS)• Cycle time:200 ns min (MSM41256A-1 OAS/RS)220 ns min (MSM41256A-12AS/RS)260 ns min (MSM41256A-15AS/RS)• Low power:385 mW active, 28 mW max standby• Single +5V Supply, ± 10% tolerance• All inputs TTL compatible, low capacitive load• Three-state TTL compatible output• "Gated" CAS• 256 refresh cycles/4 ms• Common I/O capability using "Early Write"operation• Output unlatched at cycle end allowsextended page boundary andtwo-dimensional chip select• Read-Modify-Write, RAS-only refresh,capability• On-chip latches for Addresses and Data-in• On-Chip substrate bias generator for highperformance• CAS-before-RAS refresh capability• "Page Mode" capabilityPIN CONFIGURATION (TOP VIEW)As VSS Pin Names FunctionDIN CAS AD-A. Address InputsWEDourRAS Row Address StrobeCAS Col umn Address StrobeRASA,'WEWrite EnableAo'A,'DINData InputA,'A,'DOUT Data OutputA,'Vec PowerSupply (+5V)A,' VSS Ground (OV), Refresh Address132

----------------. DYNAMIC RAM· MSM41256AAS/RS •FUNCTIONAL BLOCK DIAGRAMAo-As~:~ -------------~~~- L.1 ____________-"~ OnchipVSBELECTRICAL CHARACTERISTICSABSOLUTE MAXIMUM RATINGS (See Note)RatingSymbolValueUnitVoltage on any pin relative to VSSVoltage on Vee supply relative to VSSOperating temperatureStorage temperaturePower dissipationShort circuit output currentVIN. VOUTVeeToprTstgPD-1 to +7 V-1 to +7 VOto 70 °e-55 to +150 °e1.0 W50 mANote: Parmanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.Functional operation should be restricted to the conditions as detailed in the operational sectionsof this data sheet. Exposure to absolute maximum rating conditions for extended periodsmay affect device reliability.133

• DYNAMIC RAM· MSM41256AAS/RS .----------------RECOMMENDED OPERATING CONDITIONS(Referenced to VSS)Parameter Symbol Min.Typ.Max.UnitOperatingTemperatureVce 4.5Supply VoltageVSS 0Input High Voltage, all inputs VIH 2.4Input Low Voltage, all inputs VIL -1.05.005.5 V0 V O°C to +70°C6.5 V0.8 VDC CHARACTERISTICS(Recommended operating conditions unless otherwise noted.)ParameterOPERATING CURRENT·Average power supply current(RAS, CAS cycling; tRC = min.)STANDBY CURRENTPower supply current(RAS =CAS =VIH)REFRESH CURRENT 1·Average power supply current(RAS cycling, CAS = VIH; tRC = min.)PAGE MODE CURRENT·Average power supply current(RAS = VIL, CAS cycling; tpc = min.)REFRESH CURRENT 2·Average power supply current(CAS before RAS; tRC = min.)INPUT LEAKAGE CURRENTInput leakage current, any input(OV :0:::: VIN :0:::: 5.5V, all other pins notunder test = OV)OUTPUT LEAKAGE CURRENT(Data out is disabled, OV :0:::: VOUT :0:::: 5.5V)SymbolICC1ICC2ICC3ICC4ICC5IIIILOMin. Max. Unit Notes70 rnA5.0 rnA60 rnA40 rnA65 rnA-10 10 ,..A-10 10 ,..AOUTPUT LEVELSOutput high voltage UOH = -5 rnA)Output low voltage UOL = 4.2 rnA).VOHVOL2.4 V0.4 VNote*: ICC is dependent on output loading and cycle rates. Specified values are obtained with theoutput open.134

________---..:.._______ 1. DYNAMIC RAM· MSM41256AAS/RS •CAPACITANCE(Ta = 25°C, f = 1 MHz)Parameter Symbol Typ. Max. UnitInput capacitance (Ao - As, DIN) CIN1 - 7 pFInput capacitance (RAS, CAS, WE) CIN2 - 10 pFOutput capacitance (DOUT) COUT - 7 pFCapacitance measured with Boonton Meter.135

• DYNAMIC RAM· MSM41256AAS/RS .---------------AC CHARACTERISTICS(Recommended operating conditions unless otherwise noted.) Note 1,2,3Parameter Symbol UnitMSM41256A- MSM41256A- MSM41256A-10 12 15Min. Max. Min. Max. Min. Max.NotesRefresh period tREF ms 4 4 4Random read or writecycle timetRC ns 200 220 260Read-write cycle time tRWC ns 200 220 260Access time from RAS tRAC ns 100 120 150 4,6Access time from CAS tCAC ns 50 60 75 5,6Output buffer turn-offdelaytOFF ns 0 30 0 30 0 30Transition time tT ns 3 50 3 50 3 50RAS precharge time tRP ns 85 90 100RAS pulse width tRAS ns 105 1 OILS 120 1 OILS 150 1 OILSRAS hold time tRSH ns 55 60 75CAS pulse width tCAS ns 55 1 OILS 60 1 OILS 75 1 OILSCAS hold time tCSH ns 105 120 150RAS to CAS delay time tRCD ns 25 50 25 60 25 75 7CAS to RAS set-up time tCRS ns 20 20 20Row address set-uptimetASR ns 0 0 0Row address hold time tRAH ns 15 15 15Column address set-uptimeColumn address holdtimeRead command set-uptimeRead command holdtime referenced to CASRead command holdtime referenced to RASWrite command set-uptimetASC ns 0 0 0tCAH ns 20 20 25tRCS ns 0 0 0tRCH ns 0 0 0tRRH ns 20 20 20twcs ns 0 0 0 8136

________________ • DYNAMIC RAM· MSM41256AAS/RS •AC CHARACTERISTICS (Continued)(Recommended operating conditions unless otherwise noted.)Parameter Symbol UnitMSM41256A- MSM41256A- MSM41256A-10 12 15Min. Max. Min. Max. Min. Max.NotesWrite command pulsewidthtwp ns 1520 25Write command holdtime tWCH ns 15 20 25Write command toRAS lead time tRWL ns 35 40 45Write command toCAS lead time tCWL ns 35 40 45Data-in set-up time tos ns 0 0 0Data-in hold time tOH ns 20 20 25CAS to WE delay time tcwo ns 15 20 25 8Refresh set-up time forCAS referenced to RAStFCS ns 2025 30Refresh hold time forCAS referenced to RAS tFCH ns 20 25 30CAS precharge time(C before R cycle)RAS precharge toCAS active timePage mode cycletimetCPR ns 2025 30tRPC ns 2020 20tpc ns 100120 150 9Page mode readwrite cycle timetPRWCns 100 120 150 9Page mode CASprecharge timetcp ns 4050 65 9Refresh counter testcycle time tRTC ns 340 375 430 10Refresh counter testRAS pulse width tTRAS ns 230 1 OILS 265 1 OIL 320 1 OILS 10Refresh counter testCAS precharge time tCPT ns 50 60 70 10137

• DYNAMIC RAM· MSM41256AAS/RS .---------------Notes:12345678An initial pause of 100 JJ.s is required after power-up followed by any 8 RAS cycles(Example: RAS only) before proper device operation is achieved.The AC measurements assume tT = 5 nsVIH (Min.) and VIL (Max.) are reference levels for measuring of input signals. Also transitiontimes are measured between VIH and VIL.Assumes that tRCD ~ tRCD (Max.). If tRCD is greater than the maximum recommendedvalue shown in this table, tRAC will increase by the amount that tRCD exceeds the valueshown.Assumes that tRCD ~ tRCD (Max.).Measured with a load circuit equivalent to 2TTL loads and 100 pF.Operation within the tRCD (Max.) limit insures that tRAC (Max.) can be met. tRCD (Max.)is specified as a reference point only; if tRCD is greater than the specified tRCD (Max.)limit, then access time is controlled exclusively by tCAC.twcs and tCWD are not restrictive operating parameters. They are included in the datasheet as electrical charcteristics only; if twcs ~ twcs (min.), the cycle is an early writecycle and the data out pin will remain open circuit (high impedance) throughout theentire cycle; if tCWD ~ tCWD (min.), the cycle is read-write cycle and the data out willcontain data read from the selected cell; if neither of the above sets of conditions issatisfied the condition of the data out (at access time) is indeterminate.9 Page mode cycle.10 CAS before RAS Refresh Counter Test Cycle only.138

---------------. DYNAMIC RAM· MSM41256AAS/RS •READ CYCLERASCASAddressesWEDOUT~ Don't CareWRITE CYCLE (EARLY WRITE)RASVIH-VIL-VIH-VIL-vIH-VIL-VIH-VIL-VOH-VOL-VIH-CASAddressesmVIH-VIL-vIL-VIH-VIL-WEVIH-VIL-DINvIH-VIL-DOUTVOH-VOL-I OPENI~ Don'tCare139

• DYNAMIC RAM· MSM41256AAS/RS .1---------------READ/WRITE/READ-MODIFY -WRITE CYCLE~---------------------tRWC--------------------~~ Don'tearsPAGE MODE READ CYCLE~-----------------tRAS--------------------~VIH­Adresses VI L - ,///~"1.",~ .. It\{/4I'"~"H"."L"~Don·t CarE140

----------------. DYNAMIC RAM· MSM41256AAS/RS •PAGE MODE WRITE CYCLERASVIH­VIL -~----------------tRAS----------------~Addresses Vv I H - 'lAJ'ROiv'U;',\JIL- '~~~'~~¥"Ul~~~~~~~~~"H", "L" = Don't CarePAGE MODE, READ-MODIFY-WRITE CYCLERASCASVIH_VIL_VIH_VIL_DOUT VOH- ___ __VOLtRAS--------------~--~11~'RSH=J L""1 '--V I H- .,..,..,.,'7t"n777'l""""'''''VIL_ """'"'"'-f"-'-"'-'-'-'-'-'-'-'-'~ "H" , "L" = Don't Care141

• DYNAMIC RAM· MSM41256AAS/RS .,---------------RAS ONLY REFRESH CYCLENOTE: CAS = VIH, WE, DIN = Don't careDOUTVOH-___________ -11 OPEN~ Don't CareCAS-BEFORE-RAS REFRESH CYCLENOTE: Address, WE, DIN = Don't careDRASCASDOUTVIH -VIL -f~"VOH-VOL-VOL-VIH-VIL-~--------~I OPEN ~I ----------~ Don'tCare142

________________ • DYNAMIC RAM· MSM41256AAS/RS •HIDDEN REFRESH CYCLEVIH _ ----..L I----t.,""---_ J..---.,J ,..>---- t"Ae'------lVIL -V I H -VIL -='777'm......-!-i---'II""\.AddressesWE (Read)DOUTWE V I H - 7T>777,..,..,.,,.,..,.,....,,.,777do-------..!(Read-Write) VIL -...... ""''"'''"''''''''~~ Don't CareCAS-BEFORE-RAS REFRESH COUNTER TEST CYCLEtRTeRASVOH- __________ 4-~----~--------~~~~---------1~----VOL-VIH-VIL -CASAddressesVIH-VIL-VIH-VIL-DOUT- vIH-WE (Read) VIL-VOH-vOL-DINWE (Write) VIH-VIL-VIH-VIL -~ Don't Care143

• DYNAMIC RAM· MSM41256AAS/RS .1---------------FUNCTIONAL DESCRIPTIONSimple Timing Requirements:The MSM41256A has the circuit considerationsfor easy operational timing requirementsfor high speed access time operations. TheMSM41256A can operate under the condition oftRCD (max) = tCAC which provides an optimaltime space for address multiplexing. In addition,the MSM41 256A has the minimal hold time ofAddress (tCAH), WE (tWCH) and DIN (tDH). Andthe MSM41256A can commit better memorysystem through-put during operations in an inter~leaved system. Furthermore, Oki has madetiming requirements referenced to RAS nonrestrictiveand deleted from the data sheet,which includes tAR, tWCR, tDHR and tRWD·Therefore, the hold times of the Column AddressDIN and WE as well as tCWD (CAS to WE Delay)are not restricted by tRCD.Fast Read- While-Write Cycle:The MSM41 256A has the fast read whilewrite cycle which is achieved by excellent controlof the three-state output buffer in additionto the simplified timings described in the previoussection. The output buffer is controlled~the state of WE when CAS goes low. WhenWE is low during CAS transition to low, theMSM41256A goes to early write mode wherethe output becomes floating and common liDbus can be used on the system level. Whereas,when WE goes low after tCWD following CAStransition to low, the MSM41256A goes todelayed write mode where the Gutput containsthe data from the cell selected and the data fromDIN is written into the cell selected. Therefore,very fast read write cycle becomes available.Address Inputs:A total of eighteen binary input address bitsare required to decode any 1 of 262,144 storagecell location within the MSM41256A. Nine rowaddressbits are established on the input pins(Ao through AS> and latched with the Row AddressStrobe (RAS). Then nine column addressbits are established on the input pins andlatched with the Column Address Strobe (CAS).All input addresses must be stable on or beforethe falling edge of RAS. CAS is internally inhibited(or "gated") by RAS to permit triggering ofCAS as soon as the Row Address Hold Time(tRAH) specification has been satisfied and theaddress inputs have been changed from rowaddressesto column-addresses.Write Enable:The read or write mode is selected with theWE input. A logic "high" oli WE dictates readmode, logiC "low" dictates write mode. Data inputis disabled when read mode is selected.Data Input:Data is written into the MSM41256A during awrite or read-write cycle. The last falling edge ofWE or CAS is a strobe for the Data in (DIN)register. In a write cycle, if WE is brought "low"(write mode) before CAS, DIN is strobed by CAS,and the set-up and hold times are referenced toCAS.~ read-write cycle, WE will be delayeduntil CAS has made its negative transition. ThusDIN is strobed by WE, and set-up and hold timesare referenced to WE.Data Output:The output buffer is three-state TTL compatiblewith a fan-out of two standard TTL loads.Data out is the same polarity as data in. Theoutput is in a high impedance state until CAS isbrought "low". In a read cycle, or a read-writecycle, the output is valid after tRAC from transitionof RAS when tRCD (max) is satisfied, or aftertCAC from transition of CAS when the transitionoccurs after tRCD (max). Data remain valid untilCAS is returned to "high". In a write cycle, theidentical sequence occurs, but data is not valid.Page Mode:Page-mode operation permits strobing therow-address while maintaining RAS at a logiclow (0) throughout all successive memory operationsin which the row-address doesn't change.Thus the power dissipated by the negative goingedge of RAS is saved. Further, access and cycletimes are decreased because the time normallyrequired to strobe a new row-address is eliminated.144

----------------. DYNAMIC RAM· MSM41256AAS/RS •RAS Only Refresh:Refresh of the dynamic memory cells is accomplishedby performing a memory cycle ateach of the 256 row-addresses (Ao to A 7) at leastevery 4 milliseconds. RAS only refresh avoidsany output during refresh because the outputbuffer is in the high impedance state unless CASis brought low. Strobing each of the 256 rowaddresses(Ao to A7) with RAS will cause all bitsin each row to be refreshed. Further RAS only refreshresults in a substantial reduction in powerdissipation.CAS Before RAS Refresh:CAS before RAS refreshing available on theMSM41256A offers an alternate refresh method.If CAS is held on low for the specified period(tFCS) before RAS goes to low, on chip refreshcontrol clock generators and the refresh addresscounter are enabled, and an internal refresh operationtakes place. After the refresh operation isperformed, the refresh address counter is automaticallyincremented in preparation for the nextCAS before RAS refresh operation.Hidden Refresh:Hidden refresh cycle may take place whilemaintaining latest valid data at the output by extendingCAS active time from the previousmemory read cycle. In MSM41 256A hidden refreshmeans CAS before RAS refresh and the internalrefresh addresses from the counter areused to refresh addresses, because CAS isalways low when RAS goes to low in this mode.CAS Before RAS Refresh Counter Test Cycle:A special timing sequence using CAS beforeRAS counter test cycle provides a convenientmethod of verifying the functionality of CASbefore RAS refresh activated circuitry. As shownin CAS before RAS Counter Test Cycle, if CASgoes to high and goes to low again while RAS isheld low, the read and write operation areenabled. A memory cell address, consisting of arow address (9 bits) and a column address (9bits), to be acceded can be defined as follows:• A ROW ADDRESS- Bits Aothrough A7 are defined by the refreshcounter. The other bit As is set "high"internally.• A COLUMN ADDRESSAll the bits Ao through As are defined bylatching levels on Ao through As at thesecond falling edge of CAS.Suggested CAS before RAS Counter TestProcedure:The timing, as shown in CAS before RASCounter Test Cycle, is used for all the operationsdescribed as follows:(1) Initialize the internal refresh counter. Forthis operaton, 8 cycles are required.(2) Write a test pattern of lows into memorycells at a single column address and 256row addresses.(3) By using read-modify-write cycle, read thelow written at the last operation (Step (2))and write a new high in the same cycle. Thiscycle is repeated 256 times, and highs arewritten into the 256 memory cells.(4) Read the high written at the last operation(Step (3)).(5) Complement the test pattern and repeat thesteps (2), (3) and (4).145

• DYNAMIC RAM· MSM41256AAS/RS .---------------MSM41256A Bit Map (Physical-Decimal)OPin16252 2530 0254 255 3 20 0 0 01r--0 2560 0 02570258 259 511 5100 0 0 0509 5080 0252 253256 256254 255 3 2256 256 256 2561 0 256256 256 256257256258 259 511 510256 256 256 256509 508256 256252 253·1 1252 253257 257252 253126 126254 255 3 21 1 1 1254 255 3 2257 257 257 257254 255 3 2126 126 126 1261 0 2561 1 1II:1 0 w 256Cl257 257 0 257()WClZ~~..J1 0 0 256126 126()1262571257257257126258 259 511 5101 1 1 1258 259 511 510257 257 257 257258 259 511 510126 126 126 126509 5081 1509 508257 257509 508126 126252 253382 382254 255 3 2382 382 382 3821 0 256382 382 382257382258 259 511 510382 382 382 382509 508382 382252 253127 127254 255 3 2127 127 127 1271 0 256127 127 127257127258 259 511 510127 127 127 127509 508127 127252 253383 383254 255 3 2383 383 383 3831 0 256383 383-383257383258 259 511 510383 383 383 383509 508383 383ROW DECODERROW DECODER252 253511 511254 255 3 2511 511 511 511-1 0 256511 511 511257511258 259 511 510511 511 511 511509 508511 511252 253255 255254 255 3 2255 255 255 2551 0 256255 255 255257255258 259 511 510255 255 255 255509 508255 255252 253510 510254 255 3 2510 510 510 5101 0 256510 510 510257510258 259 511 510510 510 510 510509 508510 510252 253254 254252 253385 385252 253129 129254 255 3 2254 254 254 254254 255 3 2385 385 385 385254 255 3 2129 129 129 1291 0 II: 256W254 254 Cl 2540()wClz~~1 0 ..J 256385 3850() 3851 0 256129 129 129257254-257385257129258 259 511 510254 254 254 254258 259 511 510385 385 385 385258 259 511 510129 129 129 129509 508254 254509 508385 385509 508129 129252 253384 384254 255 3 2384 384 384 3841 0 256384 384 384257384258 259 511 510384 384 384 384509 508384 384252 253128 128254 -255 3 2128 128 128 1281 0 256128 128 128-257128258 259 511 510128 128 128 128509 508128 128A8 ROW ="L"REFRESH ADDRESSA8ROW="H"REFRESH ADDRESS(0-255)oPin8A = ROW ADDRESS (DECIMAL)CELLB =COLUMNADDRESS (DECIMAL)(0-255)146

OKI semiconductorMSM41 257 AAS/RS262, 144-BIT DYNAMIC RANDOM ACCESS MEMORY < Nibble Mode Type>GENERAL DESCRIPTIONThe Oki MSM41257A is a fully decoded, dynamic NMOS random access memory organized as262144 one-bit words. The design is optimized for high-speed, high performance applications suchas mainframe memory, buffer memory, peripheral storage and environments where low power dissipationand compact layout is required.Multiplexed row and column address inputs permit the MSM41257A to be housed in a standard16 pin DIP. Pin-outs conform to the JEDEC approved pin out. Additionally, the MSM41257 A offersnew functional enhancements that make it more versatile than previous dynamic RAMs. "CASbefore-RAS"refresh provides an on-chip refresh capability, also features "nibble mode" which allowshigh speed serial access to up to 4 bits of data.The MSM41257 A is fabricated using silicon gate NMOS and Oki's advanced VLSI Polysiliconprocess. This process, coupled with single-transistor memory storage cells, permits maximum circuitdensity and minimum chip size. DynamiC circuitry is employed in the design, including the senseamplifiers.Clock timing requirements are noncritical, and power supply tolerance is very wide. All inputs andoutput are TTL compatible.FEATURES• 262,144 x 1 RAM, 16 pin package• Silicon-gate, Double Poly NMOS, singletransistor cell• Row access time:100 ns max (MSM41257 A-1 OAS/RS)120 ns max (MSM41257 A-12AS/RS)150 ns max (MSM41257 A-15AS/RS)• Cycle time:200 ns min (MSM41257A-1 OAS/RS)220 ns min (MSM41257 A-12AS/RS)260 ns min (MSM41257 A-15AS/RS)• Low power:385 mW active, 28 mW max standby• Single +5V Supply, ±1 0% tolerance• All inputs TTL compatible, low capacitive load• Three-state TTL compatible output• "Gated"CAS• 256 refresh cycles/4 ms• Common 1/0 capability using "Early Write"operation• Output unlatched at cycle end allowsextended page boundary andtwo-dimensional chip select• Read-Modify-Write, RAS-only refresh,capability• On-chip latches for Addresses and Data-in• On-chip substrate bias generator for highperformance• CAS-before-RAS refresh capability• "Nibble Mode" capabilityPIN CONFIGURATION (TOP VIEW)A. VSS Pin Names FunctionDIN CAS AD-A. Address InputsWEDOUTRASRow Address StrobeRASA,'CAS Column Address StrobeWEWrite EnableAo'A,'DINData InputA,' A ..DOUT Data OutputA,'A,'VCC Power Supply (+5V)vCCA,'VSSGround (OV)* Refresh Address147

.DYNAMICRAM·MSM41257AAS/RS.------------------------------FUNCTIONAL BLOCK DIAGRAMI-----WEAo-As1----- DIN~~~ -----~r>----

_______________ • DYNAMIC RAM ·MSM41257AAS/RS •RECOMMENDED OPERATING CONDITIONS(Referenced to VSS)Parameter Symbol Min.Typ.Max.UnitOperatingTemperatureVCC 4.5Supply VoltageVSS 0Input High Voltage, all inputs VIH 2.4Input Low Voltage, all inputs VIL -1.05.005.5 V0 V O°C to +70°C6.5 V0.8 VDC CHARACTERISTICS(Recommended operating conditions unless otherwise noted.)ParameterOPERATING CURRENT·Average power supply current(RAS, CAS cycling; tRC = min.)STANDBY CURRENTPower supply current(RAS = CAS = VIH)REFRESH CURRENT 1Average power supply current(RAS cycling, CAS = VIH; tRC = min.)NIBBLE MODE CURRENT·Average power supply current(RAS = VIL, CAS cycling; tNC = min:)REFRESH CURRENT 2Average power supply current(CAS before RAS; tRC = min.)INPUT LEAKAGE CURRENTInput leakage current, any input(OV :s VIN :s 5.5V, all other pins notunder test = OV)OUTPUT LEAKAGE CURRENT(Data out is disabled, OV :s VOUT :s 5.5V)OUTPUT LEVELSOutput high voltage (lOH = -5 mAlOutput low voltage (lOL = 4.2 mAlSymbolICC1ICC2ICC3ICC4ICC5IIIILOVOHVOLMin. Max. Unit Notes70 mA5.0 mA60 mA30 mA65 mA-10 10 /l-A-10 10 /l-A2.4 V0.4 VNote*: ICC is dependent on output loading and cycle rates. Specified values are obtained with theoutput open.149

• DYNAMIC RAM· MSM41257 AAS/RS .----------------CAPACITANCE(Ta = 25°C, f = 1 MHz)Parameter Symbol Typ. Max. UnitInput capacitance (Ao - As, DIN) CIN1 - 7 pFInput capacitance (RAS, CAS, WE) CIN2 - 10 pFOutput capacitance (DOUT) COUT - 7 pFCapacitance measured with Boonton Meter.150

----------------. DYNAMIC RAM· MSM41257AAS/RS •AC CHARACTERISTICS(Recommended operating conditions unless otherwise noted.) Note 1,2,3Parameter Symbol UnitMSM41257A- MSM41257A- MSM41257A-10 12 15Min. Max. Min. Max. Min. Max.NotesRefresh period tREF ms 4 4 4Random read or writecycle timetRC ns 200 220 260Read-write cycle time tRWC ns 200 220 260Access time from RAS tRAC ns 100 120 150 4,6Access time from CAS tCAC ns 50 60 75 5,6Output buffer turn-offdelaytOFF ns 0 30 0 30 0 30Transition time tT ns 3 50 3 50 3 50RAS precharge time tRP ns 85 90 100RAS pulse width tRAS ns 105 1 OILS 120 1 OILS 150 1 OILSRAS hold time tRSH ns 55 60 75CAS pulse width tCAS ns 55 1 OILS 60 1 OILS 75 1 OILSCAS hold time tCSH ns 105 120 150RAS to CAS delay time tRCD ns 25 50 25 60 25 75 7CAS to RAS set-up time tCRS ns 20 20 20Row address set-uptimetASR ns 0 0 0Row address hold time tRAH ns 15 15 15Column address set-uptimeColumn address holdtimeRead command set-uptimeRead command holdtime referenced to CASRead command holdtime referenced to RASWrite command set-uptimetASC ns 0 0 0tCAH ns 20 20 25tRCS ns 0 0 0tRCH ns 0 0 0tRRH ns 20 20 20twcs ns 0 0 0 8151

• DYNAMIC RAM ·MSM41257AAS/RS .----------------AC CHARACTERISTICS (Continued)(Recommended operating conditions unless otherwise noted.)Parameter Symbol UnitMSM41257A- MSM41257A- MSM41257A-10 12 15Min. Max. Min. Max. Min. Max.NotesWrite command pulsewidthtwpns 15 20 25Write command holdtime tWCH ns 15 20 25Write command toRAS lead time tRWL ns 35 40 45Write command toCAS lead time tCWL ns 35 40 45Data-in set-up time tDS ns 0 0 0Data-in hold time tDH ns 20 20 25CAS to WE delay time tCWD ns 15 20 25 8Refresh set-up time forCAS referenced to RAStFCS ns 2025 30Refresh hold time forCAS referenced to RAS tFCH ns 20 25 30CAS precharge time(C before R cycle)RAS precharge toCAS active timetCPR ns 2025 30tRPC ns 2020 20Nibble mode read/writecycle time tNC ns 55 60 70 9Nibble mode read-writecycle time tNRWC ns 55 60 70 9Nibble mode accesstimetNCACns 25 30 35 9Nibble mode CASpulse width tNCAS ns 25 30 35 9Nibble mode CASprecharge time tNCP ns 20 25 30 9Nibble mode readRAS hold time tNRRS~ ns 25 30 40 9Nibble mode writeRAS hold time tNWRSH ns 45 50 60 9Nibble mode CAS holdtime referenced to RAS tRNH ns 20 20 20 9152

----------------. DYNAMIC RAM ·MSM41257AAS/RS •AC CHARACTERISTICS (Continued)(Recommended operating conditions unless otherwise noted.)Parameter Symbol UnitMSM41257A- MSM41257A- MSM41257A-10 12 15Min. Max. Min. Max. Min. Max.NotesRefresh counter testcycle time tRTC ns340 375 430 10Refresh counter testRAS pulse widthtTRAS ns 230 10fLS 265 10fLS 320 10fLS 10Refresh counter testCAS precharge time tCPT ns50 60 70 10Notes:2345678An initial pause of 100 fLs is required after power-up followed by any 8 RAS cycles(Example: RAS only) before proper device operation is achieved.The AC characteristics assume at tT = 5 nsVIH (Min.) and VIL (Max.) are reference levels for measuring of input signals. Also transitiontimes are measured between VIH and VIL.Assumes that tRCD ~ tRCD (Max.). If tRCD is greater than the maximum recommendedvalue shown in this table, tRAC will increase by the amount that tRCD exceeds the valueshown.Assumes that tRCD ~ tRCD (Max.).Measured with a load circuit equivalent to 2TTL loads and 100 pF.Operation within the tRCD (Max.) limit insures that tRAC (Max.) can be met. tRCD (Max.)is specified as a reference point only; if tRCD is greater than the specified tRCD (Max.)limit, then access time is controlled exclusively by tCAC.twcs and tCWD are not restrictive operating parameters. They are included in the datasheet as electrical charcteristics only; if twcs ~ twcs (min.), the cycle is an early writecycle and the data out pin will remain open circuit (high impedance) throughout theentire cycle; if tCWD ~ tCWD (min.), the cycle is read-write cycle and the data out willcontain data read from the selected cell; if neither of the above sets of conditions issatisfied the condition of the data out (at access time) is indeterminate.9 Nibble mode cycle.10 CAS before RAS Refresh Counter Test Cycle only.153

• DYNAMIC RAM· MSM41257 AAS/RS .----------------READ CYCLEtRAStRCRASVIH-VIL-CAStRSHVIH-VIL-tCASAddressesWEDOUTVIH-VIL-VIH-VIL -VOH-VOL-I ..~tCAC :1tRACI OPEN I ~~tRCH~RRHvJ f'O"Oata~Don't CareWRITE CYCLE (EARLY WRITE)1RASCASAddressesVIH-vIL-VIH-VIL-VIH-VIL-WEDINVIH-VIL-VIH-VIL-DOUTVOH-VOL-I OPENI~ Don'tCare154

----------------. DYNAMIC RAM· MSM41257AAS/RS •READ-WRITE/READ-MODIFY -WRITE CYCLE~----------------------tRWC----------------------~V I H- ----4.....-:-::-----.1--..VIL -VIH-Addresses V I L -'(;d~~!!!:'.;)DOUTNIBBLE MODE READ CYCLEVOH-VOLtRPRASVIH-VIL -CASAddresses ~IH-IL -111WEDOUTVIH-VIL-~ Don't Care155

• DYNAMIC RAM ·MSM41257AAS/RS .----------------NIBBLE MODE WRITE CYCLEtRPRASCASVIH-VIL-VIH-VIL -Addresses VIH-VIL-WEVIH-VIL-DINVIH-VIL -DOUTVOH-VOL-Open~Don't CareNIBBLE MODE READ-WRITE CYCLERASVIL -CASVIH-vIH-VIL -~Addresses VIH-VIL -WEVIL -DOUTDINVIH-VOH-VOL-VIH-VIL -~ Don't Care156

----------------. DYNAMIC RAM· MSM41257AAS/RS •FfAS ONLY REFRESH CYCLENOTE: CAS = VIH, WE, DIN = Don't careDOUTVOH-____________ 1 OPEN~ Don't CareCAS-BEFORE-RAS REFRESH CYCLENOTE: Address, WE, DIN = Don't careRASVIH -VIL -CASVOL-VIH-VIL -DOUTVOH-VOL- ----------~I OPEN~ Don'tCare157

• DYNAMIC RAM· MSM41257AAS/RS .----------------HIDDEN REFRESH CYCLERASVIH-VIL -CASVIH -VIL -AddressesVIH -VIL -WE (Read)DOUTVOL -WEVOH-v1H-(Read-Write) V IL-~ Don't CareCAS-BEFORE-RAS REFRESH COUNTER TEST CYCLERASVIH-VIL -CASAddressesVIH-VIL -VIH-VIL -- VIH-WE (R ead) V I L _ .,"",,",,,,,,",,""",,,",",,,,,,",,""",,,",",,~DOUTVIH- ~~7n~~~7n~~~7n~~~V I L -.:..:.;."""=""""'"""""""="""=""""'""'"'~ lI'--____ Jr "'''"'''''"'''"''=''"''="~ Don't Care158

_______________ • DYNAMIC RAM· MSM41257AAS/RS •FUNCTIONAL DESCRIPTIONSimple Timing Requirements:The MSM41257 A has the circuit considerationsfor easy operational timing requirementsfor high speed access time operations. TheMSM41257 A can operate under the condition oftRCD (max) = tCAC which provides an optimaltime space for address multiplexing. In addition,the MSM41257A has the minimal hold time ofAddress (tCAH), WE (tWCH) and DIN (tDH). Andthe MSM41257 A can commit better memorysystem through-put during operations in an interleavedsystem. Furthermore, Oki has madetiming requirements referenced to RAS nonrestrictiveand deleted from the data sheet,which includes tAR, tWCR, tDHR and tRWD·Therefore, the hold times of the Column AddressDIN and WE as well as tCWD (CAS to WE Delay)are not restricted by tRCD.Fast Read- While-Write Cycle:The MSM41 257 A has the fast read whilewrite cycle which is achieved by excellent controlof the three-state output buffer in additionto the Simplified timings described in the previoussection. The output buffer is controlledby the state of WE when CAS goes low. WhenWE is low during CAS transition to low, theMSM41257 A goes to early write mode wherethe output becomes floating and common liDbus can be used on the system level. Whereas,when WE goes low after tCWD following CAStransition to low, the MSM41257 A goes todelayed write mode where the output containsthe data from the cell selected and the data fromDIN is written into the cell selected. Therefore,very fast read write cycle .becomes available.Address Inputs:A total of eighteen binary input address bitsare required to decode any 1 of 262,144 storagecell location within the MSM41257 A. Nine rowaddressbits are established on the input pins(Ao through ABJ and latched with the Row AddressStrobe (RAS). Then nine column addressbits are established on the input pins andlatched with the Column Address Strobe (CAS).All input addresses must be stable on or beforethe falling edge of RAS. CAS is internally inhibited(or "gated") by RAS to permit triggering ofCAS as soon as the Row Address Hold Time(tRAH) specification has been satisfied and theaddress inputs have been changed from rowaddressesto column-addresses.Write Enable:The read or write mode is selected with theWE input. A logic "high" on WE dictates readmode, logic "low" dictates write mode. Data inputis disabled when read mode is selected.Data Input:Data is written into the MSM41 257 A during awrite or read-write cycle. The last falling edge ofWE or CAS is a strobe for the Data in (DIN)register. In a write cycle, if WE is brought "low"(write mode) before CAS, DIN is strobed by CAS,and the set-up and hold times are referenced toCAS. In a read-write cycle, WE will be delayeduntil CAS has made its negative transition. ThusDIN is strobed by WE, and set-up and hold timesare referenced to WE.Data Output:The output buffer is three-state TTL compatiblewith a fan-out of two standard TTL loads.Data out is the same polarity as data in. Theoutput is in a high impedance state until CAS isbrought "low". In a read cycle, or a read-writecycle, the output is valid after tRAC from transitionof RAS when tRCD (max) is satisfied, or aftertCAC from transition of CAS when the transitionoccurs after tRCD (max). Data remain valid untilCAS is returned to "high". In a write cycle, theidentical sequence occurs, but data is not valid.Nibble Mode:Nibble mode allows high speed serial read,write or read-modify-write access of 2, 3 or 4bits of data. The bits of data that may be accessedduring nibble mode are determined bythe 8 row addresses and the 8 column addresses.The 2 bits of addresses (CJ\a RAa) are usedto select 1 of the 4 nibble bits for initial access.After the first bit is accessed by normal mode,the remaining nibble bits may be accessed byCAS "high" then "low" while RAS remains "low".Toggling CAS causes RAa and CAa to be incrementedinternally while all other address bits areheld constant and makes the next nibble bitavailable for access. (See Table 1 )If more than 4 bits are accessed duringnibble mode, the address sequence will begin torepeat. If any bit is written during nibble mode,the new data will be read on any subsequentaccess. If the write operation may be executedagain on subsequent access, the new data willbe written into the selected cell location.In nibble mode, the three-state control ofDOUT Pin is determined by the first normal accesscycle.The data output is controlled by only WEstate referenced at CAS negative transition ofthe normal cycle (first Nibble bit). That is, whentwcs > twcs (min) is met, the data output willremain open circuit throughout the succeedingNibble cycle regardless of WE state. Whereas,when tCWD > tCWD (min) is met, the dataoutput will contain data from the cell selectedduring the succeeding nibble cycle regardless ofWE state. The write operation is done during theperiod where WE and CAS clocks are low.Therefore, write operation can be done bit by bitduring each nibble operation at any timing conditionsof WE (twcs and tCWD) at the normalcycle (first Nibble bit). 159

• DYNAMIC RAM ·MSM41257AAS/RS .----------------Table 1NIBBLE MODE ADDRESS SEQUENCE EXAMPLENIBBLE ROW COLUMNSEQUENCE BIT RAa ADDRESS CAa ADDRESSRAS/CAS (normal mode) 0 10101010 0 10101010 ... input addressestoggle CAS (nibble mode) 2 1 10101010 0 10101010toggle CAS (nibble mode) 3 0 10101010 10101010 generated intertoggleCAS (nibble mode) 4 1 10101010 1 10101010 repeatsnally sequencetoggle CAS (nibble mode) 0 10101010 0 101010101RAS Only Refresh:Refresh of the dynamic memory cells is accomplishedby performing a memory cycle ateach of the 256 row-addresses (AD to A 7) at leastevery 4 milliseconds. RAS only refresh avoidsany output during refresh because the outputbuffer is in the high impedance state unless CASis brought low. Strobing each of the 256 rowaddresses(AD to A7) with RAS will cause all bitsin each row to be refreshed. Further RAS only refreshresults in a substantial reduction in powerdissipation.CAS Before RAS Refresh:CAS before RAS refreshing available on theMSM41 257 A offers an alternate refresh method.If CAS is held on low for the specified period(tFCS) before RAS goes to low, on chip refreshcontrol clock generators and the refresh addresscounter are enabled, and an internal refresh operationtakes place. After the refresh operation isperformed, the refresh address counter is automaticallyincremented in preparation for the nextCAS before RAS refresh operation.Hidden Refresh:Hidden refresh cycle may take place whilemaintaining latest valid data at the output by extendingCAS active time from the previousmemory read cycle. In MSM41257 A hidden refreshmeans CAS before RAS refresh and the internalrefresh addresses from the counter areused to refresh addresses, because CAS isalways low when RAS goes to low in this mode.CAS Before RAS Refresh Counter Test Cycle:A special timing sequence using CAS beforeRAS counter test cycle provides a convenientmethod of verifying the functionality of CASbefore RAS refresh activated circuitry. As shownin CAS before RAS Counter Test Cycle, if CASgoes to high and goes to low again while RAS isheld low, the read and write operation areenabled. A memory cell address, consisting of arow address (9 bits) and a column address (9bits), to be acceded can be defined as follows:• A ROW ADDRESS- Bits AD through A7 are defined by the refreshcounter. The other bit Aa is set "high"internally.• A COLUMN ADDRESS- All the bits Ao through Aa are defined bylatching levels on Ao through Aa at thesecond falling edge of CAS.Suggested CAS before RAS Counter TestProcedure:The timing, as shown in CAS before RASCounter Test Cycle, is used for all the operationsdescribed as follows:(1) Initialize the internal refresh counter. Forthis operaton, 8 cycles are required.(2) Write a test pattern of lows into memorycells at a single column address and 256row addresses.(3) By using read-modify-write cycle, read thelow written at the last operation (Step (2))and write a new high in the same cycle. Thiscycle is repeated 256 times, and highs arewritten into the 256 memory cells.(4) Read the high written at the last operation(Step (3)).(5) Complement the test pattern and repeat thesteps (2), (3) and (4).160

----------------. DYNAMIC RAM ·MSM41257AAS/RS •NIBBLE MODE1) The case of first nibble cycle is Early write~~ __________________________ ~r--~ / \ /----~~---------~-------DOUT :==)>-_____________ Hi9h-Z _______________~EarlY Write~NO ope.~.~I ... --Write~~Write~(Add Increment)~: Valid Data2) The case of first nibble cycle is delyed write IRead-Write)RAS ~ r--\~. ----------------------------~IDOUT\~---------'/\\.--_--1,------~~-------~-----I---- Read-Write.. I. Read-Write~ Read------t.- Read-write--I~: Valid Data161

• DYNAMIC RAM ·MSM41257AAS/RS .----------------MSM41257A Bit Map (Physical-Decimal)o Pin 16252 253 2540 0 0255 3 20 0 0,-----1 0 2560 0 02570258 259 511 5100 0 0 0509 5080 0252 253 254256 256 256255 3 2256 256 2561 0 256256 256 256257256258 259 511 510256 256 256 256509 508256 256252 253 2541 1 1252 253 254257 257 257252 253 254126 126 126255 3 21 1 1255 3 2257 257 257255 3 2126 126 1261 0 2561 1 10:1 0 w 256Cl257 257 0 257(JWClz::!::::J..J1 0 0 256126 126(J1262571257257257126258 259 511 5101 1 1 1258 259 511 510257 257 257 257258 259 511 510126 126 126 126509 5081 1509 508257 257509 508126 126252 253 254382 382 382255 3 2382 382 3821 0 256382 382 382257382258 259 511 510382 382 382 382509 508382 382252 253 254127 127 127255 3 2127 127 1271 0 256127 127 127257127258 259 511 510127 127 127 127509 508127 127252 253 254383 383 383255 3 2383 383 3831 0 256383 383 383L--257383258 259 511 510383 383 383 383509 508383 383ROW DECODERROW DECODER252 253 254511 511 511255 3 2511 511 5111r---0 256511 511 511257511258 259 511 510511 511 511 511509 508511 511252 253 254255 255 255255 3 2255 255 2551 0 256255 255 255257255258 259 511 510255 255 255 255509 508255 255252 253 254510 510 510255 3 2510 510 5101 0 256510 510 510257510258 259 511 510510 510 510 510509 508510 510252 253 254254 254 254252 253 254385 385 385252 253 254129 129 129255 3 2254 254 254255 3 2385 385 385255 3 2129 129 1291 0 0:w256254 254 Cl0254(JWClz::!:1 0:::J..J 256385 385 0(J 3851 0 256129 129 129257254257385257129258 259 511 510254 254 254 254I258 259 511 510385 385 385 385258 259 511 510129 129 129 129I509 508254 254509 508385 385509 508129 129252 253 254384 384 384255 3 2384 384 3841 0 256384 384 384257384258 259 511 510384 384 384 384509 508384 384252 253 254128 128 128255 3 2128 128 128A8ROW="L"REFRESH ADDRESS1 0 256128 128-128257128258 259 511 510128 128 128 128A8ROW="H"REFRESH ADDRESS509 508128 128(0-255)oPin8A =ROW ADDRESS (DECIMAL)CELLB =COLUMN ADDRESS (DECIMAL)(0-255)162

OKI semiconductorMSM41464RS65,536-WORD x 4-BITS DYNAMIC RANDOM ACCESS MEMORYGENERAL DESCRIPTIONThe Oki MSM41464 is a fully decoded, dynamic NMOS random access memory organized as65,536 words by 4 bits. The design is optimized for high-speed, high performance applications suchas mainframe memory, buffer memory, peripheral storage and environments where low power dissipationand compact layout is required.Multiplexed row and column address inputs permit the MSM41464 to be housed in a standard 18pin DIP. Pin-outs conform to the JEDEC approved pin out. Additionally, the MSM41464 offers newfunctional enhancements that make it more versatile than previous dynamic RAMs. "CASbefore-RAS"refresh provides an on-chip refresh capability.The MSM41464 is fabricated using silicon gate NMOS and Oki's advanced VLSI Polysiliconprocess. This process, coupled with single-transistor memory storage cells, permits maximum circuitdensity and minimum chip size. Dynamic circuitry is employed in the design, including the senseamplifiers.Clock timing requirements are noncritical, and power supply tolerance is very wide. All inputs andoutput are TTL compatible.FEATURES• 65,536 x 4 RAM, 18 pin package• Silicon-gate, Double Poly NMOS, singletransistor cell• Row access time:100 ns max (MSM41464-1 DRS)120 ns max (MSM41464-12RS)150 ns max (MSM41464-15RS)• Cycle time:200 ns min (MSM41464-1 DRS)230 ns min (MSM41464-12RS)260 ns min (MSM41464-15RS)• Low power:385 mW active, 28 mW max standby• Single +5V Supply, ± 10% tolerance• All inputs TTL compatible, low capacitive load• Three-state TTL compatible output• "Gated" CAS• 256 refresh cycles/4 ms• Output impedance controllable through earlywrite and OE operations• Output unlatched at cycle end allowsextended page boundary andtwo-dimensional chip select• Read-Modify-Write, RAS-only refresh,capability• On-chip latches for Addresses and Data-in• On-chip substrate bias generator for highperformance• CAS-before-RAS refresh capability• "Page Mode" capabilityPIN CONFIGURATION (TOP VIEW)OEDQ1DO,VSSDO,CASPin NamesAo-A,RASFUnctionAddress InputsRow Address StrobeWE D03 CAS Column Address StrobeRAS Ao DO,-DO, Data In/Data OutA, OE Output EnableA5 A,-WE Write EnableA, A3VCC Power Supply (+5V)VCC A-VSSGround (DV)163

• DYNAMIC RAM· MSM41464RS •• ------------------FUNCTIONAL BLOCK DIAGRAM~~~ -----~r.--- I'-______ ...JL--J OnchipVSBELECTRICAL CHARACTERISTICSABSOLUTE MAXIMUM RATINGS (See Note)RatingSymbolValueUnitVoltage on any pin relative to VSSVoltage on Vee supply relative to VSSOperating temperatureStorage temperaturePower disSipationShort circuit output currentVIN. VOUTVeeToprTstgPD-1 to +7 V-1 to +7 Vo to 70 °e-55 to +150 °e1.0 W50 mANote: Parmanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.Functional operation should be restricted to the conditions as detailed in the operational sectionsof this data sheet. Exposure to absolute maximum rating conditions for extended periodsmay affect device reliability.164

------------------. DYNAMIC RAM· MSM41464RS •RECOMMENDED OPERATING CONDITIONS(Referenced to VSS)Parameter Symbol Min.Typ.Max.UnitOperatingTemperatureSupply VoltageVCC 4.5VSS 05.005.5 V0 V O°C to +70°CInput High Voltage, all inputs VIH 2.4Input Low Voltage, all inputs VIL -1.06.5 V0.8 VDC CHARACTERISTICS(Recommended operating conditions unless otherwise noted.)ParameterOPERATING CURRENT'Average power supply current(RAS, CAS cycling; tRC = min.)STANDBY CURRENT'Power supply current(RAS = CAS = VIH)REFRESH CURRENT l'Average power supply current(RAS cycling, CAS = VIH; tRC = min.)PAGE MODE CURRENT'Average power supply current(RAS = VIL, CAS cycling; tpc = min.)REFRESH CURRENT 2'Average power supply current(CAS before RAS; tRC = min.)INPUT LEAKAGE CURRENTInput leakage current, any input(OV ::; VIN ::; 5.5V, all other pins notunder test = OV)OUTPUT LEAKAGE CURRENT(Data out is disabled, OV ::; VOUT ::; 5.5V)OUTPUT LEVELSOutput high voltage (lOH = -5 mAlOutput low voltage (lOL = 4.2 mAlSymbolICC1ICC2ICC3ICC4ICC5IIIILOVOHVOLMin. Max. Unit Notes70 mA5.0 mA55 mA60 mA60 mA-10 10 J1-A-10 10 J1-A2.4 V0.4 VNote": ICC is dependent on output loading and cycle rates. Specified values are obtained with theoutput open.165

• DYNAMIC RAM· MSM41464RS ... ------------------CAPACITANCE(Ta = 25°C, f = 1 MHz)Parameter Symbol Typ. Max. UnitInput capacitance (AD - A7) CIN1 - 7 pFInput capacitance (RAS, CAS, WE, OE) CIN2 - 10 pFData 1/0 capacitance (DO 1 - 004) CD - 7 pFCapacitance measured with Boonton Meter.166

------------------1. DYNAMIC RAM· MSM41464RS •AC CHARACTERISTICS(Recommended operating conditions unless otherwise noted.) Note 1,2,3Parameter Symbol UnitMSM41464- MSM41464- MSM41464-10 12 15Min. Max. Min. Max. Min. Max.NotesRefresh period tREF ms 4 4 4Random read or writecycle time tRC ns 200 230 260Read-write cycle time tRWC ns 275 320 360Page mode cycle time tpc ns 100 120 145Access time from RAS tRAC ns 100 120 150 4,6Access time from CAS tCAC ns 50 60 75 5,6Output buffer turn-offdelaytOFF ns 0 30 0 35 0 40Transition time tT ns 3 50 3 50 3 50RAS precharge time tRP ns 90 100 100RAS pulse width tRAS ns 100 10J.Ls 120 10J.Ls 150 10J.LsRAS hold time tRSH ns 50 60 75CAS precharge time(Page mode cycle only)tcp ns 40 50 60CAS pulse width tCAS ns 50 10J.Ls 60 10J.Ls 75 10J.LsCAS hold time tCSH ns 100 120 150RAS to CAS delay time tRCD ns 22 50 22 60 25 75 7,8CAS to RAS set-up time tCRS ns 20 25 30Row address set-uptimetASR ns 0 0 0Row address hold time tRAH ns 12 12 15Column address set-uptimetASC ns 0 0 0Column address holdtimetCAHns 15 15 20Read command set-uptime tRCS ns 0 0 0Read command holdtime tRCH ns 0 0 0 10Write command set-uptimetwcs ns -5 -5 -5 9167

• DYNAMIC RAM· MSM41464RS .------------------AC CHARACTERISTICS (Continued)(Recommended operating conditions unless otherwise noted.)Parameter Symbol UnitMSM41464- MSM41454- MSM41464-10 12 15Min. Max. Min. Max. Min. Max.NotesWrite command pulsewidthtwp ns 2025 30Write command holdtime tWCH ns 20 25 30Write command toRAS lead time tRWL ns 35 45 50Write command toCAS lead time tCWL ns 35 45 50Data-in set-up time tDS ns 0 0 0Data-in hold time tDH ns 20 25 30CAS to WE delay tCWD ns 85 100 120 9RAS to WE delay tRWD ns 135 160 195 9Read command holdtime reference to RAS tRRH ns 20 20 25 10Access time from OE tOEA ns 25 30 40OE data delay time tOED ns 30 35 40OE hold time tOEH ns 0 0 0Turn-off delay timefrom OERAS to CAS set-up time(CAS before RAS)tOEZ ns 0 30 0 35 0 40tFCS ns 2025 30RAS to CAS hold time(CAS before RAS) tFCH ns 20 25 30CAS active delay fromRAS prechargeCAS precharge time(CAS before RAS)Read/write cycle(Refresh counter test)RAS pulse width(Refresh counter test)CAS precharge time(Refresh counter test)Read/write cycle time(Page mode)tRPC ns 2020 20tCPR ns 20 2530tRTC ns 385450 515 11tTRAS ns 285 1 OILS 340 1 OILs 405 1 OILS 11tCPT ns 50 6070 11tpRWC ns 175 210245168

------------------. DYNAMIC RAM . MSM41464RS •Notes: 123456789An initial pause of 100 JJ.s is required after power-up followed by any 8 RAS cycles(Example: RAS only) before proper device operation is achieved.The AC characteristics assume at tT = 5 nsVIH (Min.) and VIL (Max.) are reference levels for measuring of input signals. Also transitiontimes are measured between VIH and VIL.Assumes that tRCD ~ tRCD (Max.) If tRCD > tRCD (Max.), tRAC will increase by {tRCD- tRCD (Max.)}.Assumes that tRCD ;;;, tRCD (Max.).Measured with a load circuit equivalent to 2TTL loads and 100 pF.Operation within the tRCD (Max.) limit insures that tRAC (Max.) can be met. tRCD (Max.)is specified as a reference point only; if tRCD is greater than the specified tRCD (Max.)limit, then access time is controlled exclusively by tCAC.Assumes that tRCD (Min.) = tRAH (Min.) + 2tT + tASC (Min.)twcs, tCWD and tRWD are not restrictive operating parameters. They are included inthe data sheet as electrical charcteristics only; if twcs > twcs (Min.), the cycle is anearly write cycle and the data in/data out pin will remain open circuit (high impedance)throughout the entire cycle; if tCWD ;;;, tCWD (Min.) and tRWD ;;;, tRWD (Min.) the cycleis read-write cycle and the data in/data out will contain data read from the selected cell;if neither of the above sets of conditions is satisfied the condition of the data out (ataccess time) is indeterminate.10 Either tRRH or tRCH must be satisfied for a read cycle.11 CAS before RAS refresh counter test cycle only.READ CYCLEtRASRAS V I H =-----i. 1------------'-"-"-".---------1 x.-------,L__ J----- tRsH------~---~~---_,r_ __ ~-------tCAs-----~CAS V IH -VIL-VILtcstRCAddresses V I HVlLVIH 77TT.n7TTTT.r.n777T---~-----------~-~~77TTTTTTTV I tCAC _____-II L ...LL..L.LLLI.".J..L.L.L£.L..l4T I------'~------tRAC ------~DATA VOH ______ _VOL - OPEN Valid DataV IHVIL LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL£~ __ -ZZLLLLLLLLLLLLLLLLLL~ "H", "L" = Don't Care169

• DYNAMIC RAM· MSM41464RS •• ------------------WRITE CYCLE (EARLY WRITE)-- V 1H - ------JRAS V 1L -~ "H", "L" = Don't CareOE WRITE CYCLEIRCt RASRAS V 1H -V 1L -tCSHtRSHt CASDCASV 1H -V 1L -WE V 1HV 1H~ "H", "L" = Don't Care170

-----------------. DYNAMIC RAM ·MSM41464RS •READ/WRITE AND READ MODIFY WRITE CYCLEDATAyY'/OH-/ ___ OPENVOL- Ir--- IRAeI~ "H", "L"=Don'ICarePAGE MODE READ CYCLE~----------------------IRAS [:}1'---------------ff--- I - RS =;-----= IRPICRSAddresses Y, HY ILolumnaddress~! t ICA !oF"F I f-ICAC-=W !oFF f- IC~RE!OFF IVOL - ~CS JJ~~~S LLdr-DATA Y OH -=--- OPEN I i I ------WE ~:~=!IlIi}~. I~~ I (I ~OEAOE ~: ~'L 1Wf&~ 1Il/llIIlllll1/J-~.-~ ~ ~ -ib~ ~ECZiI "W', "L" = Don'l Care171

.OVNAMICRAM·MSM41464RS.-----------------------------------PAGE MODE WRITE CYCLEtRASRASV IH -VIL - (ICAS V IH -VIL -Address VIHVlLWEV IHVlLDATAV IHVlLCl"E~ "H", "L" = Don't CarePAGE MODE OE WRITE CYCLECAS VI H _=-+f====tt- tCSHV lL --1--------tpc -------1 tRSH ___-1RC~-l-r---t CAS -----I_____ tCAS ____ ~1'---------1AddressWEV I H -ZTTTTT7"7TTT7-+-------

------------------. DYNAMIC RAM . MSM41464RS •PAGE MODE READ/WRITE CYCLEr-__________ t'PRWL-________ ~t R S H ----------iteA S ______ -IAddressWEV I H ~77771rcrn7Tm--+---------=\VIL~~~WU~~ ~~~~ ____ -JDATA V1H/VOH ~n7~~~~~~jb.~~\~~~~_in77TTTrr,77~,b~--\A,~~~_Jrv77TTTTTVIL/VOL~~4L~~~~~OE' V I H =------.VlL --~ "H", "L" = Don't CareRAS ONLY REFRESH CYCLENote: CAS = VIH, WE and OE not dependent on the high or low level.AddressDATA VOH --------------­VOLOPEN~ "H", "L" = Don't Care173

• DYNAMIC RAM ·MSM41464RS .1------------------CAS BEFORE RAS REFRESH CYCLENote: WE and OE not dependent on the high or low level.CAS VIH­VIL -1-----tCPRDATA VOH ---=-------------­VOL ---OPENHIDDEN REFRESH CYCLERASV IH -V IL -IlCASAddressWEV IH -V IL -V IHVILIw~'~::W#/~~DATA VOH --=---VOL-OEV IH -V IL -f---IRACOPENtOEA~ I~ "H", "L" = Don't Care174

-----------------------------------.OYNAMICRAM·MSM41464RS.CAS BEFORE RAS REFRESH COUNTER TEST CYCLE1--__________ tRTC__ ~r---------tTRAS ---------~~r_---~Itcp 1 ____ tRSH ---~I-k--------{f------ tCAS -----lc------,.III~I 1'W//,0/0ItRCH-jDATAYOL YOH::::~---------------------~~::1===~~~~~c}.~----------__Valid Data- YIH =TT:'777TrT7Tr;'7TTTO'T7-rr-;-r"T""rrr?;"""'"M~~ Y IL ==:.LL.LL.L.LL.LL.L.LL.LLL.L...L..'-L.I..L.L1LLLLLl.c:t.L4-______ ..,.-__---!...-tp0'..LLLLt.'..LL:.LLLLt.CL£L%ItoFFYIHWE (Write) =7=;

• DYNAMIC RAM' MSM41464RS .------------------Data Output:The three-state output buffer provides directTTL compatibility with a fan-out of two standardTTL loads. Data-out is the same polarity as datain.The output is in the high-impedance (floating)state until CAS is brought low. In a read cycle theoutput goes active after the access time intervaltCAC that begins with the negative transition ofCAS as long as tRAC and tOEA are satisfied.The output becomes valid after the access timehas elapsed and remains valid while CAS or OEare low. CAS or OE going high returns it to a highimpedance state. In an early-write cycle, theoutput is always in the high impedance state. Ina delayed-write or read-modify-write cycle, theoutput must be put in the high impedance stateprior to applying data to the DO input. This is accomplishedby bringing OE high prior to applyingdata, thus satisfy tOED.Output Enable:The OE controls the impedance of the outputbuffers. When OE is high, the buffers will remainin the high impedance state. Bringing OE lowduring a normal cycle will activate the output buffersputting them in the low impedance state. It isnecessary for both RAS and CAS to be broughtlow for the output buffers to go into the low impedancestate. Once in the low impedance state,they will remain in the low impedance state untilOE or CAS is brought high.Page Mode:Page-mode operation permits strobing therow-address while maintaining RAS at a logiclow (0) throughout all successive memory operationsin which the row-address doesn't change.Thus the power dissipated by the negative goingedge of RAS is saved. Further, access and cycletimes are decreased because the time normallyrequired to strobe a new row-address is eliminated.RAS Only Refresh:Refresh of the dynamic memory cells is accomplishedby performing a memory cycle ateach of the 256 row-addresses (Ao to A 7) at leastevery four milliseconds. RAS only refresh avoidsany output during refresh because the outputbuffer is in the high impedance state unless CASis brought low. Strobing each of 256 (Ao to A7)row-addresses with RAS will cause all bits ineach row to be refreshed. Further RAS-only refreshresults in a substantial reduction in powerdissipation.CAS Before RAS Refresh:CAS before RAS refreshing offers an alternaterefresh method. If CAS is held on low for thespecified period (tFCS) before RAS goes to low,on chip refresh control clock generators and therefresh address counter are enabled, and an internalrefresh operation takes place. After the refreshoperation is performed, the refresh addresscounter is automatically incremented in preparationfor the next CAS before RAS refreshoperation.Hidden Refresh:Hidden refresh cycle may take place whilemaintaining latest valid data at the output by extendingCAS active time. Hidden refresh meansCAS before RAS refresh and the internal refreshaddresses from the counter are used to refreshaddresses, because CAS is always low whenRAS goes to low in this mode.CAS Before RAS Refresh Counter Test Cycle:A special timing sequence using CAS beforeRAS counter test cycle provides a convenientmethod of verifying the functionality of CASbefore RAS refresh activated circuitry. As shownin CAS before RAS Counter Test Cycle, if CASgoes to high and goes to low again while RAS isheld low, the read and write operation areenabled. This is shown in the CAS before RAScounter test cycle. A memory cell address, consistingof a row address (8 bits) and a column address(8 bits), to be acceded can be defined asfollows:• A ROW ADDRESS- Bits Ao through A 7 are defined by the refreshcounter.• A COLUMN ADDRESSAll the bits Ao through A7 are defined bylatching levels on Ao through A 7 at thesecond falling edge of CAS.Suggested CAS before RAS Counter TestProcedure:The timing, as shown in CAS before RASCounter Test Cycle, is used for all the operationsdescribed as follows:(1) Initialize the internal refresh counter. Forthis operaton, 8 cycles are required.(2) Write a test pattern of lows into memorycells at a single column address and 256row addresses.(3) By using read-modify-write cycle, read thelow written at the last operation (Step (2))and write a new high in the same cycle. Thiscycle is repeated 256 times, and highs arewritten into the 256 memory cells.(4) Read the high written at the last operation(Step (3)).(5) Complement the test pattern and repeat thesteps (2), (3) and (4).176

--------_---------1. DYNAMIC RAM· MSM41464RS •252 253 2540 0 0252 253 2540 0 0252 253 2541 1 1252 253 2541 1 1252 253 2542 2 2252 253 2542 2 2252 253 254125 125 125252 253 254125 125 125252 253 254126 126 126252 253 254126 126 126252 253 254127 127 127252 253 254127 127 127I252 253 254255 255 255252 253 254255 255 255252 253 254254 254 254252 253 254254 254 254252 253 254253 253 253252 253 254253 253 253252 253 254130 130 130252 253 254130 130 130252 253 254129 129 129252 253 254129 129 129252 253 254128 128 128252 253 254128 128 128255025502551255125522552255125255125255126255126255127255127ROW255255255255255254255254255253255253255130255130255129255129255128255128303031313232312531253126312631273127DECODERREFRESH ADDRESSMSM41464 Bit Map (Physical-Decimal)DQ1 DQ2 DQ3 DQ42 1 0 0 1 20 0 0 0 0 02 1 00 1 20 0 01- k 0 0 02 1 0 0 1 21 1 1 1 1 12 1 0 0 1 2} k1 1 1 1 1 12 1 0 0 1 22 2 2 2 2 2a:2 1 00 1 21- gk2 2 2 2 2 2~0z:J '"2 1 0

.---=D=-._K __ I __s_._rn-'----l_c_onc:I __ U_c_.or ______ ~_~MSM414256RS262,144·WORD x 4·BITS DYNAMIC RAMGENERAL DESCRIPTIONThe MSM414256RS is a new generation dynamic RAM organized as 262,144 words by 4 bits.The technology used to fabricate the MSM414256RS is OKI's N channel silicon gate MOS processtechnology. The device operates at a single +5V power supply. Its I/O pins are TTL compatible.FEATURES• Silicon gate, tripple polysilicon NMOS,1-transistor memory cell• 262,144 words by 4 bits• Standard 20-pin plastic DIP• Family organizationFamilyMSM414256-10RSMSM414256-1 2RSAccess Time(MAX)100 ns120 nsCycle TimePower Dissipation(MIN) Operating Stand By(MAX)(MAX)200 ns 413mW230 ns 385mW28mW• Single +5V supply, ± 10% tolerance• Input: TTL compatible, address input, datainput latch• Output: TTL compatible, tristate, non latch• Refresh: 512 cycles/8 ms• Output impedance controllable through earlywrite and OE operations• Page mode, read modify write capability• CAS before RAS refresh, CAS before RAShidden refresh, RAS only refresh capability• "Gated"CAS• Built-in VBB generator circuitPIN CONFIGURATION (TOP VIEW)~D03D04WE DOl Pin Names FunctionCASAOtoA8 Address InputNCOERASRow Address Strobec;;;gColumn Address Strobe"AOAS"001 to 004 Data In/Data Out"Al A7" DE Output Enable"A2 WE Write Enable"A3VCCPower Supply (+5V)VSSGround (OV)"Refresh Address178

__________________ DYNAMIC RAM ·MSM414256RS _FUNCTIONAL BLOCK DIAGRAM1----- WEA.-A.DO ,-DO,WordDrivers______--'OnchipVBB----Y--,VSS-VCCMemoryCellsELECTRICAL CHARACTERISTICSABSOLUTE MAXIMUM RATINGSRatingSymbolConditionsValueUnitVoltage on any pin relative to VSSVTTa = 25°C-1.0 to +7.0 VShort circuit output currentlosTa =25°C50 rnAPower dissipationPDTa =25°C1 WOperating temperatureTopr-o to +70 °cStorage temperatureTstg--55 to +150 °cRECOMMENDED OPERATING CONDITIONS(Ta = 0 to +70°)Parameter Symbol ConditionsMINTYP MAX UnitSupply VoltageVCC -VSS -4.505.0 5.5 V0 0 VInput high voltage VIH -I nput low voltage VIL -2.4-1.0- 6.5 V- 0.8 V179

• DYNAMIC RAM· MSM414256RS .-----------------DC CHARACTERISTICS(VCC = 5V ±10%, Ta = 0 to +70°C)Parameter Symbol ConditionsMSM MSM414256-10 414256-12MIN MAX MIN MAXUnit NoteOutput high voltage VOH 10H =-5.0 mA 2.4 - 2.4 - VOutput low voltage VOL 10L =4.2 mA - -0.4 - 0.4 VOV ;;;; VI ;;;; 6.5V;Input leakage current III all other pins not -10 10 -10 10 JJ.Aunder test = OVOutput leakage currentILO00UT disableOV;;;; VO ;;;;5.5V-10 10 -10 10 JJ.AAverage power supplycurrent" (Operating)ICC1RAS, CAS cycling,tRC =min- 75 - 70 mAPower supply current"(Standby)ICC2RAS =VIHCAS=VIH- 5 - 5 mAAverage power supplyRAS cycling,current" ICC3 CAS=VIH - 65 - 60 mA(RAS only refresh)tRC = minAverage power supplyRAS=VIL,current" ICC4 CAS cycling - 70 - 65 mA(Page mode)tpc =minAverage power supplycurrent"(CAS before RAS refresh)ICC5RAScycling,CAS before RAS- 70 - 65 mA*Note: ICC is dependent on output loading and cycle rates. Specified values are obtained with theoutput open.CAPACITANCE(Ta = 25°C, f = 1 MHz)Parameter Symbol Conditions TYP MAX UnitInput capacitance (AO to A8) CIN1 - - 5 pFInput capacitance(RAS, CAS, WE, DE)CIN2 - - 10 pF1/0 capacitance (001 to 004) C - - 7 pF180

-----------------__ DYNAMIC RAM· MSM414256RS _AC CHARACTERISTICSNote 1,2,3 (VCC = 5V ±1 0%, Ta = 0 to +70°C)MSM414256-10 MSM414256-12Parameter Symbol Unit NoteMIN MAX MIN MAXRefresh period tREF - 8 - 8 msRandom read/write cycle time tRC 200 - 230 - nsRead/write cycle time tRWC 275 - 305 - nsPage mode cycle time tpc 100 - 120 - nsAccess time from RAS tRAC - 100 - 120 ns 4,6Access time from CAS tCAC - 50 - 60 ns 5,6Output buffer turn-off delay tOFF 0 25 0 25 nsTransition time tT 3 50 3 50 nsRAS precharge time tRP 90 - 100 - nsRAS pulse width tRAS 100 10000 120 10000 nsRAS hold time tRSH 50 - 60 - nsCAS precharge time(Page mode cycle only)tcp 40 - 50 - nsCAS pulse width tCAS 50 10000 60 10000 nsCAS hold time tCSH 100 - 120 - nsRAS to CAS delay time tRCD 25 50 25 60 ns 7,8CAS and RAS set-up time tCRS 15 20 - nsRow address set-up time tASR 0 - 0 - nsRow address hold time tRAH 15 - 15 - nsColumn address set-up time tASC 0 - 0 - nsColumn address hold time tCAH 20 - 20 - nsColumn address hold time from RAS, tAR 70 - 80 - nsRead command set-up time tRCS 0 - 0 - nsRead command hold time tRCH 0 - 0 - ns 10Write command hold time from RAS tWCR 80 . - 95 - nsWrite command set-up time twcs 0 - 0 - ns 9Write command hold time tWCH 30 - 35 - ns181

• DYNAMIC RAM • MSM414256RS .-----------------AC CHARACTERISTICS (CONT.)ParameterMSM414256-10 MSM41 4256-12Symbolr-----.-----+------r----~MIN MAX MIN MAXUnitNoteWrite command pulse widthtwp 30 35nsWrite command to RAS lead time40 40nsWrite command to CAS lead time,Data-in set-up timetCWL 40 40tDS o onsnsData-in hold time30 35nsData-in hold time from RAS80 95nsCAS to WE delayRAS to WE delayRead command hold timereference to RASAccess time from OEOE data delay timeOE hold timeTurn-off delay time from OEOE set-up timeRAS to CAS set-up time(CAS before RAS)RAS to CAS hold time(CAS before RAS)CAS active delay from RASprechargeCAS precharge time(CAS before RAS)Read/write cycle(Refresh counter test)RAS pulse width(Refresh counter test)CAS precharge time(Refresh counter test)tCWD 80 90tRWD 130 150tRRH 20 20tOEA 30 30tOED 25 25tOEH o otOEZ o 25 o 25tOES 30 30tFCS 20 25tFCH 30 30tRPC 20 20tCPR 20 25385 435tTRAS 285 10000 325 10000tCPT 50 - 60 -ns 9ns 9ns 10nsnsns 11nsnsnsnsnsnsns 11ns 11ns 11Read/write cycle time (Page mode) tpRWC 175 195ns182

------------------11. DYNAMIC RAM· MSM414256RS •Notes: 123456789An initial pause of 100 JLs is required after power-up followed by any 8 RAS cycles(Example: RAS only) before proper device operation is achieved.The AC characteristics assume at tT = 5 nsVIH (Min.) and VIL (Max.) are reference levels for measuring of input signals. Also,transition times are measured between VIH and VIL·Assumes that tRCD ;S tRCD (Max.). If tRCD > tRCD (Max.), tRAC will increase by {tRCD- tRCD (Max.)l·Assumes that tRCD :;;; tRCD (Max.).Measured with a load circuit equivalent to 2TTL + 100 pF.Operation within the tRCD (Max.) limit insures that tRAC (Max.) can be met. tRCD (Max.)is specified as a reference pOint only; if tRCD is greater than the specified tRCD (Max.)limit, then access time is controlled exclusively by tCAC.Assumes that tRCD (Min.) = tRAH (Min.) + 2tT + tASC (Min.).twcs, tCWD and tRWD are not restrictive operating parameters. They are included inthe data sheet as electrical charcteristics only; if twcs ~ twcs (Min.), the cycle is anearly write cycle and the data out pin will remain open circuit (high impedance)throughout the entire cycle; if tCWD ~ tCWD (Min.) and tRWD ~ tRWD (Min.) the cycleis read-write cycle and the data out will contain data read from the selected cell; ifneither of the above sets of conditions is satisfied the condition of the data out (ataccess time) is indeterminate.10 Either tRRH or tRCH must be satisfied for a read cycle.11 CAS before RAS refresh counter test cycle only.183

• DYNAMIC RAM 'MSM414256RS .-----------------READ CYCLEtRCRAS VIH -VIL-CAS VIH-VIL -tARtRAStcs 0'II,tRSHtCASAddress VIHVJLWEVIHVILDATA VOH -VOLi-------:--tCAC -----jf------- tRAC -------lOPENDEVIHVJL~ Don'tCareWRITE CYCLE (EARLY WRITE)-- V IH -CAS VIL -tARtRAStCSHItRCtRStCA184

-----------------. DYNAMIC RAM· MSM414256RS •READ/WRITE AND READ MODIFY WRITE CYCLERAS Y rH -YrL -CASYr/ OH -DATAy / ____ OPENVOL - It RAeIr--------~ Don'tCarePAGE MODE READ CYCLEr-------------- tRAS ~tAR---j~----~I-------------(f-----tR-StCRStRPAddress y I HYJLII~ Don'tCare185

• DYNAMIC RAM . MSM414256RS .1-----------------PAGE MODE WRITE CYCLERAStRASCASAddress VIHVILWEVIHVILDATAVIHVILDE~ Don'tCarePAGE MODE READ/WRITE CYCLE~-~---__ tpRw~----~~__lo.r_-o___-t CAS ----1t R S H -----1teA S -----1AddressWEVIH~n7ih~7Tnf--1_--------~V IL -z:lC/J..,'f-L.J..t..,f..!...!!DATA Vla/VOH~7nJ;~~~~~~~~,~~~--_i-/T.r,7777TTF,~\1 __ ~,~~~~_Jd7.r.n7777TV [L/V 0 L -::Z:;

____________________ DYNAMIC RAM· MSM414256RS -RAS ONLY REFRESH CYCLE'Note: CAS = VIH, WE and OE not dependent on the high or low level.DATA V 1H ----------­V/LOPENEZZJ Don'tCareCAS BEFORE RAS REFRESH CYCLENote: WE and OE not dependent on the high or low level.DATA V 1H ----------­V/LOPEN~ Don'tCare187

• DYNAMIC RAM . MSM414256RS .1-----------------HIDDEN REFRESH CYCLERASCASV IH -V IL -V IH -V IL -tRCtAR----11tRSHI1----tFCH ---I~---AddressWE~ IVI ff 1M" !II//#I $///#/II II 4OPENValid DataV IH =-----,V IL -~ Don'tCareCAS BEFORE RAS REFRESH COUNTER TEST CYCLEtRTCtTRASRAS .1CAStCPTDAddress /, I.WE (Read)DATAOE(Read)Ijj ITIIV / II//! 1/ I/ITI/ 1/./~IIrtCACWE (Write)DATA /1 10mOE (Write) 7ff!ll !I/!]-LLllf!7.lJ..IZ1Z17Z1 fZl;i~toEHV///////fl/! 11//////2~ Don'tCarc188

-----------------.... DYNAMIC RAM· MSM414256RS •FUNCTIONAL DESCRIPTIONAddress Inputs:18 bits of binary address input are requiredto decode anyone of the 262,144 words by 4bits storage cell locations.9 row-address bits are set up on addressinput pins AO through A8 and latched onto thechip by the row address strobe (RAS). Then 9column-address bits are set up on pins AOthrough A8 and latched onto the chip by thecolumn address strobe (CAS).All addresses must be stable on or before· thefalling edges of RAS. CAS is internally inhibited(gated) by the RAS to permit triggering of CAS assoon as the Row Address Hold Time (tRAH)specification has been satisfied and the addressinputs have been changed from row-addressesto column-addresses.Therefore specifications permit columnaddresses to be input immediately after the rowaddress hold time (tRAH).Write Enable:The read mode or write mode is selected withthe WE input. The logic high of the WE inputselects the read mode and a logic low selectsthe write mode. The data input is disabled whenthe read mode is selected. Data-out will remainin the high-impedance state allowing a writecycle with WE grounded.Data Input:Data is written during a write or read-modifywrite cycle. Depending on the mode of operation,the falling edge of CAS or WE strobes data intothe on-chip data latches. In an early-write cycle,WE is brought low prior to CAS and the data isstrobed in by CAS with setup and hold timesreferenced to this Signal. In a delayed write orread-modify-write cycle, CAS will already be low,thus the data will be strobed in by WE with setupand hold times referenced to this Signal. Indelayed or read-modify-write, OE must be highto bring the output buffers to high impedanceprior to impressing data on the I/O lines.Data Output:The three-state output buffer provides directTTL compatibility with a fan-out of two standardTTL loads. Data-out is the same polarity as datain.The output is in the high-impedance (floating)state until CAS is brought low. In a read cycle theoutput goes active after the access time intervaltCAC that begins with the negative transition ofCAS as long as tRAC and tOEA are satisfied.The output becomes valid after the access timehas elapsed and remains valid while CAS andOE is low. CAS or OE going high returns it to ahigh impedance state. In an early-write cycle,the output is always in the high impedance state.In a delayed-write or read-modify-write cycle,the output must be put in the high impedancestate prior to applying data to the DQ input. Thisis accomplished by bringing OE high prior to applyingdata, thus satisfy tOED,Output Enable:The OE controls the impedance of the outputbuffers. When OE is high, the buffers will remainin the high impedance state. Bringing OE lowduring a normal cycle will activate the output buffersputting them in the low impedance state. It isnecessary for both RAS and CAS to be broughtlow for the output buffers to go into the low impedancestate. Once in the low impedance state,they will remain in the low impedance state untilCAS or OE is brought high.Page Mode:Page-mode operation permits strobing therow-address while maintaining RAS at a logiclow (0) throughout all successive memoryoperations in which the row-address doesn'tchange. Thus the power dissipated by thenegative going edge of RAS is saved. Further,access and cycle times are decreased becausethe time normally required to strobe a newrow-address is eliminated.RAS Only Refresh:Refresh of the dynamic memory cells isaccomplished by performing a memory cycle ateach of the 51 2 row-addresses (Ao to As) at leastevery eight milliseconds. RAS only refreshavoids any output during refresh because theoutput buffer is in the high impedance stateunless CAS is brought low. Strobing each of 512(Ao to As) row-addresses with RAS will cause allbits in each row to be refreshed. FurtherRAS-only refresh results in a substantialreduction in power dissipation.CAS Before RAS Refresh:CAS before liAS" refreshing offers analternate refresh method. If CAS is held on lowfor the specified period (tFCS) before RAS goesto low, on chip refresh control clock generatorsand the refresh address counter are enabled,and an internal refresh operation takes place.After the refresh operation is performed, therefresh address counter is automaticallyincremented in preparation for the next CASbefore RAS refr~sh operation.Hidden Refresh:Hidden refresh cycle may take place whilemaintaining latest valid data at the output byextending CAS active time. Hidden refreshmeans CAS before RAS refresh and the internalrefresh addresses from the counter are used torefresh addresses, because CAS is always lowwhen RAS goes to low in this mode.189

• DYNAMIC RAM· MSM414256RS •• -----------------CAS Before RAS Refresh Counter Test Cycle:A special timing sequence using CAS beforeRAS counter test cycle provides a convenientmethod of verifying the functionality of CAS"before RAS refresh activated circuitry. As shownin CAS before "RAS Counter Test Cycle, if CASgoes to high and goes to low again while 'RAS isheld low, the read and write operation areenabled. This is shown in the CAS before RAScounter test cycle. A memory cell address,consisting of a row address (9 bits) and acolumn address (9 bits), to be acceded can bedefined as follows:• A ROW ADDRESS- Bits AD through As are defined by therefresh counter.• A COLUMN ADDRESSAll the bits AD through As are defined bylatching levels on AD through As at thesecond falling edge of CAS".Suggested CAS before RAS Counter TestProcedure:The timing, as shown in CAS before RASCounter Test Cycle, is used for all the operationsdescribed as follows:(1) Initialize the internal refresh counter. Forthis operaton, 8 cycles are required.(2) Write a test pattern of lows into memorycells at a single column address and 512row addresses.(3) By using read-modify-write cycle, read thelow written at the last operation (Step (2))and write a new high in the same cycle. Thiscycle is repeated 512 times, and highs arewritten into the 512 memory cells.(4) Read the high written at the last operation(Step (3».(5) Complement the test pattern and repeat thesteps (2), (3) and (4).190

OKI setnlconductor .,.~~-------------------------------------------~~~MSM411000RS1,048,576-WORD x 1-BITS DYNAMIC RAMGENERAL DESCRIPTIONThe MSM411 OOORS is a new generation dynamic RAM organized as 1,048,576 words by 1 bit.The technology used to fabricate the MSM411 OOORS is OKI's N channel silicon gate MOS processtechnology. The device operates at a single +5V power supply. Its I/O pins are TTL compatible.FEATURES• Silicon gate, tripple polysilicon NMOS,1-transistor memory cell• 1,048,576 words by 1 bitFamilyMSM411 000-1 ORSMSM411 000-1 2RSAccess Time(MAX)100 ns120 ns• Single +5V supply, ±1 0% tolerance• Input: TTL compatible, address input, datainput latch• Output: TTL compatible, tristate, nonlatch• Refresh: 512 cycles/8 ms• Common I/O capability using "Early Write"operation• Standard 1 8-pin plastic DIP• Family organizationCycle TimePower Dissipation(MIN) Operating Stand By(MAX)(MAX)200 ns 413mW230 ns 385mW28mW• Page mode, read modify write capability• CAS before RAS refresh, CAS before RAShidden refresh, RAS only refresh capability• "Gated" CAS• Built-in VBB generator circuitPIN CONFIGURATION (TOP VIEW)Pin NamesAOtoA9RASCASDINDOUTWEVCCVSSFunctionAddress InpulRow Address StrobeColumn Address StrobeData InputData OutputWrite EnablePower Supply (+5V)Ground (OV)• Refresh Address191

_ DYNAMIC RAM· MSM411 OOORS ___ ----------------FUNCTIONAL BLOCK DIAGRAMi-----WEAo-A.DOUTWordDrIvers______-'OnchipVBB----y--,VCC Vss-MemoryCellst-----DINELECTRICAL CHARACTERISTICSABSOLUTE MAXIMUM RATINGSRating Symbol ConditionsValueUnitVoltage on any pin relative to VSSVTTa = 25°C-1.0 to +7.0 VShort circuit output currentlosTa = 25°C50 mAPower disSipationPoTa =25°C1 WOperating temperatureTopr-o to +70DCStorage temperatureTstg--55 to +150 °cRECOMMENDED OPERATING CONDITIONS(Ta = 0 to +70°)Parameter Symbol ConditionsMINTYP MAX UnitSupply VoltageVCC -VSS -4.505.0 5.5 V0 0 VInput high voltage VIH -Input low voltage VIL -2.4-1.0- 6.5 V- 0.8 V192

________________ __._ DYNAMIC RAM· MSM411 OOORS _DC CHARACTERISTICS(VCC = 5V ±1 0%, Ta = 0 to +70°C)Parameter Symbol ConditionsMSM MSM411000-10 411000-12MIN MAX MIN MAXUnit NoteOutput high voltage VOH IOH =-5.0 mA 2.4 - 2.4 - VOutput low voltage VOL IOL=4.2 mA - 0.4 - 0.4 VOV ~ VI ~ 6.5V;Input leakage current III all other pins not -10 10 -10 10 ~Aunder test = OVOutput leakage currentILODOUT disableOV ~VO ~5.5V-10 10 -10 10 ~AAverage power supplycurrent" (Operating)ICC1RAS, CAS cycling,tRC =min- 75 - 70 mAPower supply current"(Standby)ICC2RAS=VIHCAS=VIH- 5 - 5 mAAverage power supplyRAS cycling,current" ICC3 CAS =VIH - 65 - 60 mA(RAS only refresh)tRC =minAverage power supplyRAS=VIL,current" ICC4 CAS cycling - 70 - 65 mA(Page mode)tpc =minAverage power supplyRAScycling,current" ICC5 - 70 - 65 mACAS before RAS(CAS before RAS refresh)"Note: ICC is dependent on output loading and cycle rates. Specified values are obtained with theoutput open.CAPACITANCE(Ta = 25°C, f = 1 MHz)Parameter Symbol Conditions TYP MAX UnitInput capacitance (AO to A9, DIN) CIN1 - - 5 pFInput capacitance(RAS, CAS, WE)CIN2 - - 10 pFOutput capacitance (DOUT) COUT - - 7 pF193

• DYNAMIC RAM· MSM411 OOORS •• -----------------AC CHARACTERISTICSNote 1,2,3 (VCC = 5V ±1 0%, Ta = 0 to +70°C)MSM411000-10 MSM411000-12Parameter Symbol Unit NoteMIN MAX MIN MAXRefresh period tREF - 8 - 8 msRandom read/write cycle time tRC 200 - 230 - nsRead/write cycle time tRWC 235 - 255 - nsPage mode cycle time tpc 100 - 120 - nsAccess time from RAS tRAC - 100 - 120 ns 4,6Access time from CAS tCAC - 50 - 60 ns 5,6Output buffer turn-off delay tOFF 0 25 0 25 nsTransition time tT 3 50 3 50 ns--RAS precharge time tRP 90 - 100 - ns--RAS pulse width tRAS 100 10000 120 10000 ns-- RAS hold time tRSH 50 - 60 - nsCAS precharge time(Page mode cycle only)tcp 40 - 50 - nsCAS pulse width tCAS 50 10000 60 10000 nsCAS hold time tCSH 100 - 120 - nsRAS to CAS delay time tRCD 25 50 25 60 ns 7,8CAS and RAS set-up time tCRS 15 I- ! 20 - nsRow address set-up time tASR 0 - 0 - nsRow address hold time tRAH 15 - 15 - nsColumn address set-up time tASC 0 - 0 - nsColumn address hold time tCAH 20 - 20 - nsColumn address hold time from RAS, tAR 70 - 80 - nsRead command set-up time tRCS 0 - 0 - nsRead command hold time tRCH 0 - 0 - ns 10Write command hold time from RAS tWCR 80 - 95 - nsWrite command set-up time twcs 0 - 0 - ns 9Write command hold time tWCH 30 - 35 - ns194

________________........ DYNAMIC RAM ·MSM411000RS •AC CHARACTERISTICS (CONT.)MSM411000-10 MSM411000-12Parameter Symbol Unit NoteMIN MAX MIN MAXWrite command pulse width twp 30 - 35 - nsWrite command to RAS lead time tRWL 40 - 40 - nsWrite command to CAS lead time tCWL 40 - 40 - nsData-in set-up time tDS 0 - 0 - nsData-in hold time tOH 30 - 35 - nsData-in hold time from RAS tOHR 80 - 95 - nsCAS to WE delay tcwo 40 - 40 - ns 9RAS to WE delay tRWD 90 - 100 - ns 9Read command hold timereference to RASRAS to CAS set-up time(CAS before RAS)RAS to CAS hold time(CAS before RAS)CAS active delay from RASprechargeCAS precharge time(CAS before RAS)Read/write cycle(Refresh counter test)RAS pulse width(Refresh counter test)CAS precharge time(Refresh counter test)tRRH 20 - 20 - ns 10tFCS 20 - 25 - nstFCH 30 - 30 - nstRPC 20 - 20 - nstCPR 20 - 25 - nstRTC 355 - 385 - ns 11tTRAS 255 10000 275 10000 ns 11tCPT 50 - 60 - ns 11Read/write cycle time (Page mode) tpRWC 135 - 145 - ns195

• DYNAMIC RAM· MSM411 OOORS •• -----------------Notes:123456789An initial pause of 100 iJ-s is required after power-up followed by any 8 RAS cycles(Example: RAS only) before proper device operation is achieved.The AC characteristics assume at tT = 5 nsVIH (Min.) and VIL (Max.) are reference levels for measuring of input signals. Also,transition times are measured between VIH and VIL·Assumes that tRCD ;:S tRCD (Max.). If tRCD > tRCD (Max.), tRAC will increase by {tRCD- tRCD (Max.)}.Assumes that tRCD ~ tRCD (Max.).Measured with a load circuit equivalent to 2TTL + 100 pF.Operation within the tRCD (Max.) limit insures that tRAC (Max.) can be met. tRCD (Max.)is specified as a reference point only; if tRCD is greater than the specified tRCD (Max.)limit, then access time is controlled exclusively by tCAC.Assumes that tRCD (Min.) = tRAH (Min.) + 2tT + tASC (Min.).twcs, tCWD and tRWD are not restrictive operating parameters. They are included inthe data sheet as electrical charcteristics only; if twcs ~ twcs (Min.), the cycle is anearly write cycle and the data out pin will remain open circuit (high impedance)throughout the entire cycle; if tCWD ~ tCWD (Min.) and tRWD ~ tRWD (Min.) the cycleis read-write cycle and the data out will contain data read from the selected cell; ifneither of the above sets of conditions is satisfied the condition of the data out (ataccess time) is indeterminate.10 Either tRRH or tRCH must be satisfied for a read cycle.11 CAS before RAS refresh counter test cycle only.196

----------------___ DYNAMIC RAM· MSM411 OOORS _READ CYCLERAS V IH -V IL -CAS V IH -VIL-AddressV IHV 1LWEVIHVILDOUT V OH -VOL------- OPEN ------1f------,;:-'''' ~ __ _ValidData~ Don't CareWRITE CYCLE (EARLY WRITE)____--.,j, t RAS ,Je------{.- VIH- ~-----------·~I~~--------~RAS V I L _~---tAR--~-~·tRCDtCSHtRCVOH_DOUT VOL ------------------- OPEN ~ Don't Care197

• DYNAMIC RAM· MSM411 OOORS ... -----'------------READ/WRITE AND READ MODIFY WRITE CYCLEV I H- --1r-~----.r-""VIL-DOUT~ Oon'tCarePAGE MODE READ CYCLE1----------- tRAS ntAR---jl'-----'--------rf----t-RSa::::=:.j----' tRPteAtCRSAddress V IHV 1L'f~ Don'teare198

-----------'--------. DYNAMIC RAM· MSM411 OOORS •PAGE MODE WRITE CYCLERAS VIR -VIL -Address VIRVILWEVIRVILDINVIRV IL~ Don't CarePAGE MODE READ/WRITE CYCLERAS VIR ~~t _____V IL -tRAS----'tA~R~---_~I----------~~~---------------------~~-~I------'I'--__ -'t P RW"-----------iItRS" ___-IteA S ------IAddressWEVIR~nT.~n77T,~-+-------~V IL --=:..u...¥L.LJ..L:J~ Don'tCare199

• DYNAMIC RAM· MSM411 OOORS •• -----------------RAS ONLY REFRESH CYCLENote: CAS = VIH' WE and DIN not dependent on the high or low level.AddressOPEN~ Don'tCareCAS BEFORE RAS REFRESH CYCLENote: Address WE and DIN not dependent on the high or low level.VOH -DOUT VOL ------------ OPEN~ Don'tCare200

-----------------11. DYNAMIC RAM· MSM411 OOORS •HIDDEN REFRESH CYCLERAS VIH -VIL -CASVIH -VIL -AddressesVIH -VIL -DOUTWE (Read) VIH -VIL-VOH-WE~ Don't CareCAS BEFORE RAS REFRESH COUNTER TEST CYCLERASvOL-vIH-(Read-Write) V I L -VIH-VIL -CASAddressesVIH-VIL -vIH-VIL---- VIH- ~~~~~~~~~~~~~~--------------~~---i~~~WE (Read) VIL _ ::.:::.:::."'""''"'"'""''"''"'="'''"'DOUTVIH- ~""~~~~~~~~~~~~ ~----------~,~~~~~~"V I L - ~~~~~"''"'"''"'"'""''"'"'~ 1I-________ -.JI~ Don't Care201

• DYNAMIC RAM· MSM411 OOORS •• -----------------FUNCTIONAL DESCRIPTIONAddress Inputs:20 bits of binary address input are requiredto decode anyone of the 1,048,576 words by 1bit storage cell locations.10 row-address bits are set up on addressinput pins AO through A9 and latched onto thechip by the row address strobe (RAS). Then 10column-address bits are set up on pins AOthrough A9 and latched onto the chip by thecolumn address strobe (CAS).All addresses must be stable on or before thefalling edges of RAS. CAS is internally inhibited. (gated) by the RAS to permit triggering of CAS assoon as the Row Address Hold Time (tRAH)specification has been satisfied and the addressinputs have been changed from row-addressesto column-addresses.Therefore specifications permit columnaddresses to be input immediately after the rowaddress hold time (tRAH).Write Enable:The read mode or write mode is selected withthe WE input. The logic high of the WE inputselects the read mode and a logic low selectsthe write mode. The data input is disabled whenthe read mode is selected.Data Input:Data is written during a write or read-modifywrite cycle. Depending on the mode of operation,the falling edge of CAS or WE strobes data intothe on-chip data latches. In an early-write cycle,WE is brought low prior to CAS and the data isstrobed in by CAS with setup and hold timesreferenced to this signal. In a delayed write orread-modify-write cycle, CAS will already be low,thus the data will be strobed in by WE with setupand hold times referenced to this signal.Data Output:The three-state output buffer provides directTTL compatibility with a fan-out of two standardTTL loads. Data-out is the same polarity asdata-in. The output is in the high-impedance(floating) state until CAS is brought low. In a readcycle the output goes active after the accesstime interval tCAC that begins with the negativetransition of CAS as long as tRAC is satisfied.The output becomes valid after the access timehas elapsed and remains valid while CAS is low.CAS going high returns it to a high impedancestate. In an early-write cycle, the output isalways in the high impedance state.Page Mode:Page-mode operation permits strobing therow-address while maintaining RAS at a logiclow (0) throughout all successive memoryoperations in which the row-address doesn'tchange. Thus the power dissipated by thenegative going edge of RAS is saved. Further,access and cycle times are decreased becausethe time normally required to strobe a newrow-address is eliminated.RAS Only Refresh:Refresh of the dynamic memory cells is accomplishedby performing a memory cycle ateach of the 51 2 row-addresses (Ao to As) at leastevery 8 milliseconds. RAS only refresh avoidsany output during refresh because the outputbuffer is in the high impedance state unless CASis brought low. Strobing each of 512 (Ao to As)row-addresses with RAS will cause all bits ineach row to be refreshed. Further RAS-only refreshresults in a substantial reduction in .powerdissipation.CAS Before RAS Refresh:CAS before RAS refreshing offers analternate refresh method. If CAS is held on lowfor the specified period (tFCS) before RAS goesto low, on chip refresh control clock generatorsand the refresh address counter are enabled,and an internal refresh operation takes place.After the refresh operation is performed, therefresh address counter is automaticallyincremented in preparation for the next CASbefore RAS refresh operation.Hidden Refresh:Hidden refresh cycle may take place whilemaintaining latest valid data at the output byextending CAS active time. Hidden refreshmeans CAS before RAS refresh and the internalrefresh addresses from the counter are used torefresh addresses, because CAS is always lowwhen RAS goes to low in this mode.CAS Before RAS Refresh Counter Test Cycle:~ special timing sequence using CAS beforeRAS counter test cycle provides a convenientmethod of verifying the functionality of CASbefore RAS refresh activated circuitry. As shownin CAS before RAS Counter Test Cycle, if CASgoes to high and goes to low again while RAS isheld low, the read and write operation areenabled. This is shown in the CAS before RAScounter test cycle. A memory cell address,consisting of a row address (9 bits) and acolumn address (10 bits), to be acceded can bedefined as follows:• A ROW ADDRESS- Bits Ao through As are defined by therefresh counter.• A COLUMN ADDRESSAll the bits Ao through A9 are defined bylatching levels on Ao through A9 at thesecond falling edge of CAS.202

-----------------. DYNAMIC RAM ·MSM411000RS •Suggested CAS before RAS Counter TestProcedure:The timing, as shown in CAS before RASCounter Test Cycle, is used for all the operationsdescribed as follows:(1) Initialize the internal refresh counter. Forthis operaton, 8 cycles are required.(2) Write a test pattern of lows into memorycells at a single column address and 512row addresses.(3) By using read-modify-write cycle, read thelow written at the last operation (Step (2»and write a new high in the same cycle. Thiscycle is repeated 512 times, and highs arewritten into the 51 2 memory cells.(4) Read the high written at the last operation(Step (3».(5) Complement the test pattern and repeat thesteps (2), (3) and (4).203

OKI semiconductorMSM411 001 RS1048576-BIT DYNAMIC RANDOM ACCESS MEMORY < Nibble Mode Type>GENERAL DESCRIPTIONThe Oki MSM411 001 is a fully decoded, dynamic NMOS random access memory organized as 1 048576 one-bit words.The design is optimized for high-speed, high performance applications such as mainframe memory, buffer memory,peripheral storage and environments where low power dissipation and compact layout is required.Multiplexed row and column address inputs permit the MSM411 001 to be housed in a standard 18 pin DIP. Pin-outsconform to the JEDEC approved pin out. Additionally, the MSM411001 offers new functional enhancements thatmake it more versatile than previous dynamic RAMs. "CAS-before-RAS" refresh provides an on-chip refresh capability,also features "nibble mode" which allows high speed serial access to up to 4 bits of data.The MSM411001 is fabricated using sil icon gate NMOS and Oki's advanced VLSI Polysilicon process. This process,coupled with single-transistor memory storage cells, permits maximum circuit density and minimal chip size. Dynamiccircuitry is employed in the design, including the sense amplifiers.Clock timing requirements are noncritical, and power supply tolerance is very wide. All inputs and output are TTLcompatible.FEATURES.1048576 x 1 RAM, 18 pin package• Silicon-gate, Tripple Poly NMOS, single transistor cell• Row access time100 ns max (MSM411001-10RS)120 nsmax (MSM411001-12RS)• Cycle time200 ns min (MSM411001-10RS)230 ns min (MSM411001-12RS)• Low power: 411001-12RS413 mW/28 mW (MSM411001-10RS)385 mW/28 mW (MSM411001-12RS)• Single+5V Supply, ±10% tolerance• All inputs TTL compatible, low capacitive load• Three-state TTL compatible output• Gated CAS• 8ms/512 refresh cycles• Common I/O capability using "Early Write"operation• Output unlatched at cycle end allows extended pageboundary and two-dimensional chip select• Read-Modify-Write, RAS-only refresh, capability• On-

-----------------. DYNAMIC RAM· MSM411 001 RS •BLOCK DIAGRAMI----WE°OUTWordDriversVCC------~y~VSS-I _________ ~On chip VSSMemoryCellsI-----OINABSOLUTE MAXiMUM RATINGS (See Note)RatingVoltage on any pin relative to VSSVoltage on Vee supply relative to VSSOperating temperatureStorage temperaturePower dissipationShort circuit output currentSymbolVIN, VOUTVeeToprTstgPolOSValueUnit-1 to +7 V-1 to +7 Vo to 70 °e-55 to +150 °e1.0 W50 mANote: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operationshould be restricted to the conditions as detailed in the operational sections of this data sheet. Exposureto absolute maximum rating conditions for extended periods may affect device reliability.RECOMMENDED OPERATING CONDITIONS(Referenced to VSS)ParameterSymbol Min. Typ. Max. UnitSupply VoltageVee 4.5 5.0 5.5 VVSS 0 0 0 VInput High Voltage, all inputs VIH 2.4 6.5 VInput Low Voltage, all inputs VIL -1.0 0.8 .VOperatingTemperatureoOe to +70 o e205

• DYNAMIC RAM· MSM411 001 RS .-----------------DC CHARACTERISTICS(Recommended operating conditions unless otherwise noted.)ParameterSymbolMSM411001-10 MSM411001-12Min Max Min MaxUnitNotesOPERATING CURRENT"Average power supply current ICC1 - 75 - 70 mA(RAS, CAS cycling; tRC = min.)STANDBY CURRENT*Power su pply cu rrent ICC2 - 5 - 5 mA(RAS = CAS = VIH)REFRESH CURRENT 1 *Average power supply current ICC3 - 65 - 60 mA(RAS cycling, CAS = VIH; tRC= min.)Nibble MODE CURRENT*Average power supply current ICC4 - 70 - 65 mA(RAS = VIL, CAS cycling; tNC = min.)REFRESH CURRENT 2*Average power supply current ICC5 - 70 - 65 mA(CAS before RAS; tRC = min.)INPUT LEAKAGE CURRENTInput leakage current, any input(OV ::: V IN::: 5.5V, all other pins notunder test = OV)III -10 10 -10 10 /lAOUTPUT LEAKAGE CURRENT(Data out is disabled, ILO -10 10 -10 10 /lAOV ~ VOUT ~ 5.5V)OUTPUT LEVELSOutput high voltage UOH = -5 mAl VOH 2.4 - 2.4 - VOutput low voltage UOL = 4.2 mAl VOL - 0.4 - 0.4 VNot.": ICCis dependent on output loading and cycle rates. Speci·fied values are obtained with the output open.CAPACITANCE(Ta = 25°C, f = 1 MHz)ParameterInput Capacitance (Ao - A" DIN)Input Capacitance (RAS, CAS, WE)Output Capacitance (DOUT)Capacitance measured with Boonton Meter.SymbolCIN1CIN2COUTTyp. Max. Unit- 5 pF- 10 pF- 7pF206

------------------11. DYNAMIC RAM· MSM411 001 RS •AC CHARACTERISTICS(Recommended operating conditions unless otherwise noded.)MSM411001 MSM411001Parameter Symbol Unit 10 12 NotesMin Max Min MaxRefresh period tREF ms 8 8Random read or write cycle time tRC ns 200 230Read-write cycle time tRWC ns 235 255Access time from RAS tRAC ns 100 120 4,6Access time from CAS tCAC ns 50 60 5,6Output buffer turn-off delay tOFF ns 0 25 0 25Transition time tT ns 3 50 3 50RAS precharge time tRP ns 90 100RAS pulse width tRAS ns 100 10l's 120 10l'sRAS hold time tRSH ns 50 60CAS pulse width tCAS ns 50 10l'S 60 10 I'SCAS hold time tCSH ns 100 120RAS to CAS delay time tRCO ns 25 50 25 60 7CAS to RAS set-up time tCRS ns 15 20Row address set-up time tASR ns 0 0Row address hold time tRAH ns 15 15Column address set-up time tASC ns 0 0Column address hold time tCAH ns 20 20Column address hold time from RAS tAR ns 70 80Read command set-up time tRCS ns 0 0Read command hold time referenced to CAS tRCH ns 0 0Read command hold time referenced to RAS tRRH ns 20 20Write command hold time from RAS tWCR ns 80 951Write command set-up time twcs ns 0 0 8Write command pulse width twp ns 30 35Write command hold time tWCH ns 30 35Write command to RAS lead time tRWL ns 40 40Write command to CAS lead time tCWL ns 40 40Oata-in set-up time tos ns 0 0Oata-in hold time tOH ns 30 35Oata-in hold time from RAS tOHR ns 80 95CAS to WE delay time tcwo ns 40 40 8RAS to WE delay time tRWO ns 90 100Refresh set-up time for CAS referenced to RAS tFCS ns 20 25Refresh hold time for CAS referenced to RA::; tFCH ns 30 30CAS precharge time (C before R cycle) tCPR ns 20 25RAS precharge to CAS active time tRPC ns 20 20Nibble mode read/write cycle time tNC ns 65 70 9Nibble mode read-write cycle time tNRWC ns 65 70 9Nibble mode access time tNCAC ns 30 35 9Nibble mode CAS pulse width tNCAS ns 30 35 9207

• DYNAMIC RAM· MSM411001 RS ••----------------AC CHARACTERISTICS (Continued)(Recommended operating conditions unless otherwise noted.)MSM411001 MSM411001Parameter Symbol Unit 10 12 NotesMin Max Min MaxNibble mode CAS precharge time tNCP ns 25 25 9Nibble mode read RAS hold time tNRRSH ns 40 40 9Nibble mode write RAS hold time tNWRSH ns 40 40 9Nibble mode CAS hold time referenced to RAS tRNH ns 20 20 9Refresh counter test cycle time tRTC ns 355 385 10Refresh counter test RAS pulse width tTRAS ns 255 10,000 275 10,000 10Refresh counter test CAS precharge time tCPT ns 50 60 10NOTES:1)2)3)4)5)6)7)8)An initial pause of 100 IJS is required after power-up followed by any 8 RAS cycles (Examples; RASonly) before proper device operation is achieved.AC measurements assume tT = 5 ns.VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals. Also, transitiontimes are measured between VIH and VIL.Assumes that tRCO ~ tRCO (max.).If tRCO is greater than the maximum recommended value shown in this table, tRAC will increase bythe amount that tRCO exceeds the values shown.Assumes that tRCO ~ tRCO (max.)Measured with a load circuit equivale.nt to 2 TTL loads and 100 pF.Operation within the tRCO (max.) limit insures that tRAC (max.) can be met. tRCO (max.) is specifiedas a reference point only; if tRCO is greater than the specified tRCO (max.) limit, then accesstime is controlled exclusively by tCAC.twcs, tcwo and tRWO are not restrictive operating parameters. They are included in the data dheetas electrical characteristics only; if twcs2:twcs (min.). the cycle is an early write cycle and the dataout pin will remain open circuit (high impedance) throughout the entire cycle; if tcwo2:tcwo(min.),and tRWO 2:tRWO (min.) the cycle is read-write cycle and the data out will contain data read from theselected cell; if neither of the above sets of conditions is satisfied the condition of the data out (atacccess time) is indeterminate.9) Nibble mode cycle.10) CAS before RAS Refresh Counter Test Cycle only.208

------------------11. DYNAMIC RAM· MSM411 001 RS •READ CYCLEtRCRASCASAddressesWEDOUT~ Don'tearaWRITE CYCLE (EARLY WRITE)RASCASAddressesWEVIH-VIL-vIH-VIL-VIH-VIL-VIH-VIL-VOL-VIH-VIL-vIH-VIL-VIH-VIL-VIH-VIL -DINDOUT -------------11 OPEN ~I ------------~ Don'teare209

• DYNAMIC RAM· MSM411 001 RS .----------------­READ-WR ITE/READ-MODI FY -WRITE CYCLEDOUT~ Don'tCareNIBBLE MODE READ CYCLEVIH- ~~~~~~~------~~~~--~~~------~~~--------~~V I L - """'"""'""~"'DOUT~ Don't Care210

_________________ 1. DYNAMIC RAM· MSM411 001 RS •NIBBLE MODE WRITE CYCLERASVIL -CASVIH-VIH-VIL -Addresses VIH-VIL -WEVIH-VIL -DINVIH-VIL -DOUTvOH-VOL-~Don't CareNIBBLE MODE READ-WRITE CYCLERASVIL -CASVIH-VIH-VIL -Addresses VIH-VIL -11WEDOUTDINVIH-vIL-VOH-VOL-VIH-VIL-~ Don't Care211

_ DYNAMIC RAM· MSM411 001 RS ___ -----------------RAS ONLY REFRESH CYCLENOTE: CAS = VIH, WE, DIN = Don't careDOUT~ Don'teareCAS-BEFORE-RAS REFRESH CYCLENOTE: Address, WE, DIN = Don't careDRASCASDOUTVIH -VIL -roe>VOL- ----------~I OPENVOH------------"""il OPENVOL-VIH-VIL-VOH-~ Don'teare212

-----------------. DYNAMIC RAM· MSM411 001 RS •HIDDEN REFRESH CYCLERASVIH-VIL -CASVIH -VIL -AddressesVIH -VIL -WE (Read) VIH-VIL -DOUTvOH-VOL-~ Don't CareCAS-BEFORE-RAS REFRESH COUNTER TEST CYCLERASCASAddressesWE VIH-(Read-Write) V1L-VIH-VIL-VIH-vIL-VIH-VIL-V I H -'777"""",""""''''"'''''''''''''''"''''''''''"'''''''''''''''''''''"' l..-------J ,..,.,..,.,,,.,.,,.,..,.,,,.,.,""""'"'"VI L - """''''"'''''''''"'''''''''' ....'''"'''''''''"''''''''''"'''''''''' .... .:u "1'--____ Jr "'"'~'"'~'"'~"~ Don't Care213

• DYNAMIC RAM' MSM411 001 RS •• ----------------~DESCRIPTIONSimple nming RequirementThe MSM411001 has the circuit considerations for easyoperational timing requirements for high speed accesstime operations. The MSM411001 can operate underthe condition of tRCD (max) = tCAC which provides anoptimal time space for address mUltiplexing. In addition,the MSM411001 has the minimal hold times ofAddress (tCAH), WE (tWCH) and DIN (tDHl. Andthe MSM411001 can commit better memory systemthrough-put during operations in an inter-leaved system.Fast Read- While-Write cycleThe MSM411001 has the fast read while write cyclewhich is achieved by excellent control of the three-stateoutput buffer in addition to the simplified timingsdescribed in the previous section. The output buffer iscontrolled by the state of WE when CAS' goes low.When WF. is low during CAS transition to low, theMSM411001 goes to early write mode where the outputbecomes floating and common 1/0 bus can be used onthe system level. Whereas, when WE goes low aftertCWDfoliowing CAS transition to low, the MSM411001goes to delayed write mode where the output containsthe data from the cell selected and the data from 0 I Nis written into the cell selected. Therefore, very fastread write cycle becomes available.Address InputsA total of twenty binary input address bits are requiredto decode any 1 of 1048576 storage cell locations withinthe MSM411 001. Nine row-address bits are establishedon the input pins (Ao through A,) and latched withthe Row Address Strobe (RAS). Then ten columnaddress bits are established on the input pins and latchedwith the Column Address Strobe (CAS). All inputaddresses must be stable on or before the falling edge ofRAS. CAS is internally inhibited (or "gated") by RASto permit triggering of CAS as soon as the Row AddressHold Time (tRAH) specification has been satisfiedand the address inputs have been changed from rowaddressesto column-addresses.Write EnableThe read or write mode is selected with the WE input.A logic "high" on WE dictates read mode, logic "low"dictates write mode. Data input is disabled when readmode is selected.Data InputData is written into the MSM411001 during a write orread-write cycle. The last falling edge of WE or CAS isa strobe for the Data in (DIN) register. In a write cycle,if WE is brought "low" (write mode) before CAS, DINis strobed by CAS, and the set-up and hold times arereferenced to CAS. In a read-write cycle, WE will bedelayed until CAS has made its negative transition.Thus DIN is strobed by WE, and set-up and hold timesare referenced to WE.Data OutputThe output buffer is three-state TTL compatible with afan-out of two standard TTL loads. Data out is thesame polarity as data in. The output is in a high impedancestate until CAS is brought "low". In a read cycle,or a read-write cycle, the output is valid after tRACfrom transistion of RAS when tRCD(max) is satisfied,or after tCAC from' transition of CAS when the transitionoccurs after tRCD (maxl. Data remain valid untilCAS is returned to "high". In a write cycle, the identicalsequence occurs, but data is not valid.Nibble ModeNibble mode allows high speed serial read, write or readmodify-writeaccess of 2, 3 or 4 bits of data. The bitsof data that may be accessed during nibble mode aredetermined by the 9 row addresses and the 9 columnaddresses. The 2 bits of addresses (CA, RA,) are usedto select 1 of the 4 nibble bits for initial access. Afterthe first bit is accessed by normal mode, the remainingnibble bits may be accessed by CAS "high" then "low"while RAS remains "low". Toggling CAS causes RA,and CA, to be incremented internally while all otheraddress bits are held constant and makes the next nibblebit available for access. (See Table 1)If more than 4 bits are accessed during nibble mode, theaddress sequence will begin to repeat. If any bit iswritten during nibble mode, the new data will be readon any subsequent access. If the write operation maybe executed again on subsequent access, the new datawill be written into the selected cell location.In nibble mode, the three-state control of DOUT Pin isdetermined by the first normal access cycle.The data output is controlled by only WE state referencedat CAS negative transition of the normal cycle(first Nibble bitl. That is, when twcs > twcs (min) ismet, the data output will remain open ci rcuit throughoutthe succeeding Nibble cycle regardless of WE state.Whereas, when tCWD > tCWD (min) is met, the dataoutput will contain data from the cell selected duringthe succeeding nibble cycle regardless of WE state. Thewrite operation is done during the period where WE andCAS clocks are low. Therefore, write operation can bedone bit by bit during each nibble operation at anytiming conditions of WE (twcs and tCWD) at thenormal cycle (first Nibble bit).214

-----------------. DYNAMIC RAM' MSM411 001 RS •Table 1 NIBBLE MODE ADDRESS SEQUENCE EXAMPLESEQUENCERAS/CAS {normal model 1 0NIBBLE BIT ROW ADDRESS COLUMN ADDRESSRA,toggle CAS (nibble model 2 1toggle CAS (nibble model 3 0toggle CAS (nibble model 4 1toggle CAS (nibble model 1 0CA,101010101 0 101010101 ----- input addresses101010101 0 101010101101010101 101010101 generated inter-101010101 101010101 nally101010101 0 101010101 1 sequence repeatsRAS only RefreshRefresh of the dynamic memory cells is accomplishedby perform ing a memory cycle at each of the 512 rowaddresses(Ao through Asl at least every 8 millisecond.RAS only refresh avoids any output during refreshbecause the buffer is in the high impedance state unlessCAS is brought "low". Strobing each of the 512 rowaddresses(Ao through Asl with RAS will cause all bitsin each row to be refreshed. Further RAS only refreshresults in a substantial reduction in power dissipation.CAS before RAS RefreshCAS before RAS refreshing available on theMSM411001 offers an alternate refresh method. IfCAS is held on "low" for the specified period (tFcslbefore RAS goes to "low", on chip refresh control clockgenerators and the refresh address counter are enabled,and an internal refresh operation takes place. After therefresh operation is performed, the refresh addresscounter is automatically incremented in preparationfor the next CAS before RAS refresh operation.Hidden RefreshHidden refresh cycle may takes place while maintaininglatest valid data at the output by extending CAS activetime from the previous memory read cycle. InMSM411001 hidden refresh means CAS before RASrefresh and the internal refresh addresses from thecounter are used to refresh addresses, because CAS isalways "low" when RAS goes to "low" in hiddenrefresh.CAS before RAS Refresh Counter TestCycleA speCialtiming sequence using CAS before RAScounter test cycle provides a convenient method of verifyingthe functionality of CAS before RAS refreshactivted circuitry.As shown in CAS before RAS Counter Test Cycle, ifCAS goes to "high" and goes to "low" again while RASis held "low", the read and write operations are enabled.A memory cell address (consisting of a row address (10bitsl and a column address (10 bitsll to be accessed canbe defined as follows:• A ROW ADDRESS -Bits Ao through As are definedby the refresh counter.The other bit A, is set "high" internally.• A COLUMN ADDRESS - All the bits Ao through A,are defined by latching levels on Ao throgh A, at thesecond falling edge of CAS.Suggested CAS before RAS Counter TestProcedureThe timing as shown in CAS before RAS Counter TestCycle is used for all the operations described as follows:(11 Initialize the internal refresh counter. For thisoperation, 8 cycles are required.(21 Write a test pattern of data "low" into memorycells at a single column address and 512 rowaddresses.(31 By using read-modify-write cycle, read the "low"written at the last operation (Step (211 and writea new data "high" in the same cycle. This cycle isrepeated 512 times, and data "high" are writteninto the 512 memory cells.(41 Read the data "high" written at the last operation(Step (311.(51 Complement the test pattern and repeat the steps(21, (31 and (41.215

• DYNAMIC RAM· MSM411 001 RS .1-----------------NIBBLE MODE1) The case of first nibble cycle is Early write~~ __________________________ ~r__''-_...JI'~ ___ -JIDOUT :)>-_____________ HiQh-Z ______________ _~ Early Write~NO Ope. ..I.(Add Increment)write--...... -tl ... --Write~~: Valid Data2) The case of first nibble cycle is delyed write (Read-Write)RAS ~ ,--\~._______________________-...J'\'--___ -J1\\....__.....J1DOUT---~---------~~--~ Read-Write .. I. Read-Write-----t..-- Read-------+,- Read-Write ....... l~: Valid DetaFUNCTIONAL TRUTH TABLERAS CAS WE DIN DOUT Read Write Refresh NoteH H Don't Care Don't Care High-Z No No No StandbyL L H Don't Care Valid Data Yes No Yes ReadL L L Valid Data High-Z No Yes YesL L L Valid Data Valid Data Yes Yes YesEarly Writetwcs ~ twcs (min)Delayed Write or Read-Wr·itetCWD ~ tCWD (min)L H Don't Care Don't Care High-Z No No Yes RAS Only RefreshCAS-before-RAS Refresh ValidL L Don't Care Don't Care Valid Data No No Yes data selected at previous Reador Read-Write cycle is held.H L Don't Care Don't Care High-Z No No No CAS disturb.216

~OKI semiconductor $~~~-------------------------------------------------------------------------- ~~MSM511000RS1,048,576-WORD x 1-BIT DYNAMIC RAM GENERAL DESCRIPTIONThe MSM511 OOORS is a new generation dynamic RAM organized as 1,048,576 words by 1 bit.The technology used to fabricate the MSM511 OOORS is OKl's silicon gate CMOS process technology.The device operates from a single +5V power supply. Its I/O pins are TTL compatible.FEATURES• Silicon gate, N-well CMOS, 1 -transistormemory cell• 1,048,576 words by 1 bitFamilyMSM511000-1ORSMSM511000-12RSAccess Time(MAX)100 ns120 ns• Single +5V supply, ±1 0% tolerance• Input: TTL compatible, address input, datainput latch• Output: TTL compatible, tristate, nonlatch• Refresh: 512 cycles/8 ms• Common I/O capability using "Early Write"operation• Standard 18-pin plastic DIP• Family organizationCycle TimePower Dissipation(MIN) Operating Standby(MAX)(MAX)190 ns 385mW220 ns 330mW11 mW• Fast page mode, read modify write capability• CAS before RAS refresh, CAS before RAShidden refresh, RAS only refresh capability• "Gated" CAS• Built-in VBB generator circuitFUNCTIONAL BLOCK DIAGRAMDOUTMemoryCells1--------- DINVCC vss-- --------~---'-__________---'OnchipVBB217

OKI semiconductor ~----------------------------------------------------- ~MSM511 001 RS1,048,576-WORD x 1-BIT DYNAMIC RAM GENERAL DESCRIPTIONThe MSM511 001 RS is a new generation dynamic RAM organized as 1,048,576 words by 1 bit.The technology used to fabricate the MSM511 001 RS is OKI's silicon gate CMOS process technology.The device operates from a single +5V power supply. Its 1/0 pins are TTL compatible.FEATURES• Silicon gate, N-well CMOS, 1-transistormemory cell• 1,048,576 words by 1 bit• Standard 18-pin plastic DIP• Family organizationFamilyMSM511 001-1 ORSMSM511001-12RSAccess Time(MAX)100 ns120 nsPower DissipationCycle Time(MIN) Operating Standby(MAX)(MAX)190 ns 385mW220 ns 330mW11 mW• Single +5V supply, ±1 0% tolerance• Input: TTL compatible, address input, datainput latch• Output: TTL compatible, tristate, non latch• Refresh: 512 cycles/8 msFUNCTIONAL BLOCK DIAGRAM• Common 1/0 capability using "Early Write"operation• Static column mode, read modify writecapability• RAS only refresh capability• Suilt-in VSS generator circuitColumn I-_____ ~r-----.,AddressBuffers 1---------./L..,..----,-J1-.,--- WE~~~(r--esA.-A.DOUlRowAddressBuffersRowDecodersWordDriversMemoryCells~;:-:-l====~ DINVec ----Y--L _____VSS----lOnchipVBB218

.-=C=-.--=-K __I_---=s~e_rn_l___=_c_O_ncl_U_C_.orMSM514256RS262,144-WORD x 4-BIT DYNAMIC RAM ______ ~~GENERAL DESCRIPTIONThe MSM514256RS is a new generation dynamic RAM organized as 262,144 words by 4 bits.The technology used to fabricate the MSM514256RS is OKI's silicon gate CMOS process technology.The device operates from a single +5V power supply. Its I/O pins are TTL compatible.FEATURES• Silicon gate, N-well CMOS, 1 -transistormemory cell• 262,144 words by 4 bits• Standard 20-pin plastic DIP• Family organizationFamilyMSM514256-10RSMSM514256-12RSAccess Time(MAX)100 ns120 nsCycle TimePower Dissipation(MIN) Operating Standby(MAX)(MAX)190 ns 413mW220 ns 385mW11 mW• Single +5V supply, ±1 0% tolerance• Input: TTL compatible, address input, datainput latch• Output: TTL compatible, tristate, non latch• Refresh: 512 cycles/8 ms• Output impedance controllable through earlywrite and OE operations• Fast page mode, read modify write capability• CAS before RAS refresh, CAS before RAShidden refresh, RAS only refresh capability• "Gated" CAS• Built-in VBB generator circuitFUNCTIONAL BLOCK DIAGRAMt----- WEMemoryCellsOQ,-OQ,Vce ----Y--L _____vss----'OnchipVBB219

O __ K __ I __ seMSM514257RS__ rn_IC_O_nc:I __ U_C_._or ______ ~262,144-WORD x 4-BIT DYNAMIC RAM GENERAL DESCRIPTIONThe MSM514257RS is a new generation dynamic RAM organized as 262,144 words by 4 bits.The technology used to fabricate the MSM514257RS is OKl's silicon gate CMOS processtechnology. The device operates from a single +5V power supply. Its I/O pins are TTL compatible.FEATURES• Silicon gate, N-well CMOS, 1 -transistormemory cell• 262,144 words by 4 bits• Standard 20-pin plastic DIP• Family organizationFamilyMSM514257-10RSMSM514257-12RSAccess Time(MAX)100 ns120 nsCycle Time(MIN)Operating(MAX)190 ns 413mW220 ns 385mWPower DissipationStandby(MAX)11 mW• Single +5V supply, ±1 0% tolerance• Input: TTL compatible, address input, datainput latch• Output: TTL compatible, tristate, non latch• Refresh: 512 cycles/8 msFUNCTIONAL BLOCK DIAGRAM• Output impedance controllable through earlywrite and OE operations• Static column mode, read modify writecapability• RAS only refresh capability• Built-in VBB generator circuitDColumn 1------........ 1AddressBuffers 1---------/L....r---......I--~--WE.~~~r:t-- csAo-A,RowAddressRowBuffersDecoders----y--'-_____ --'VCC vss-OnchipVBBMemoryCellsDQ,-DQ,220

OKI semiconductorMSM37S64ARS/37S64RS131 ,072-BIT DYNAMIC RANDOM ACCESS MEMORYGENERAL DESCRIPTIONThe Oki MSM37S64 is a fully decoded dynamic NMOS random access memory organized as131,072 one-bit words using 65,536 bit stacked. The design is optimized for high-speed, high performanceapplications such as main-frame memory, buffer memory, peripheral storage and environmentswhere low power dissipation and compact layout is required.Multiplexed row and column address inputs permit the MSM37S64 to be housed in a standard 16pin DIP.The MSM37S64 is fabricated using silicon gate NMOS and Oki's advanced Double-Layer Polysiliconprocess. This process, coupled with single-transistor memory storage cells, permits maximumcircuit density and minimum chip size. Dynamic circuitry is employed in the design, including thesense amplifiers.Clock timing requirements are noncritical, and power supply tolerance is very wide. All inputs andoutput are TTL compatible.FEATURES• 131,072 x 1 RAM, 16 pin package• Silicon-gate, Double Poly NMOS, singletransistor cell• Row access time:150 ns max (MSM37S64-15)200 ns max (MSM37S64-20)• Cycle time:270 ns min (MSM37S64-15)330 ns min (MSM37S64-20)• Low power:360 mW active, 55 mW max standby• Single +5V Supply, ± 10% tolerance• All inputs TTL compatible, low capacitive load• Three-state TTL compatible output• "Gated" CAS• 128 refresh cycles/2 ms• Common I/O capability using "Early Write"operation• Output unlatched at cycle end allowsextended page boundary andtwo-dimensional chip select• Read-Modify-Write, RAS-only refresh, andPage-Mode capability• On-chip latches for Addresses and Data-in• On-chip substrate bias generator for highperformancePIN CONFIGURATION (TOP VIEW)Pin Names I FunctionDINVSSAo-A. Address InputsWECASRAS1, RAS2 Row Address StrobeCASColumn Address StrobeRAS1DOUTWEWrite EnableRAS2As"DINData InputAo" A!DOUT Data OutputA," A? VCC Power Supply (+5V)A," As" VSS Ground (OV)A·" Refresh Address1. Designates Bottom Module2. Designates Top Module221

• DYNAMIC RAM· MSM37S64ARS/37S64RS .1-----------,..---FUNCTIONAL BLOCK DIAGRAM (ONE MODULE)I----WEDOUTRowAddressBuffers--'OnchipVBB----y--'-_____ VCC vss-MemoryCells1------ DINELECTRICAL CHARACTERISTICSABSOLUTE MAXIMUM RATINGS (See Note)(TA = 25°C unless otlierwise noted)RatingSymbolValueUnitVoltage on any pin relative to VSSVoltage on Vee supply relative to VSSOperating temperatureStorage temperaturePower dissipationShort circuit output currentVIN. VOUTVeeToprTstgPolos-1 to +7 V-1 to +7 Va t070 °e-55 to +150 °e2 W50 mANote: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operationshould be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.222

------------____ DYNAMIC RAM· MSM37S64ARS/37S64RS _RECOMMENDED OPERATING CONDITIONS (Referenced to VSS)Parameter Symbol Min. Typ. Max. UnitOperatingtemperatureSupply VoltageInput High Voltage,all inputsInput Low Voltage,all inputsVCC 4.5 5.0 5.5 VVSS 0 0 0 VVIH 2.4 6.5 VVIL -1.0 0.8 VO°C to +70°CDC CHARACTERISTICS(Recommended operating conditions unless otherwise noted.)Parameter Symbol Min. Max. Unit NoteOperating Current* - One ModuleSelectedAvera~wer supply current(RAS, CA cycling; tRC = min.)ICC1 65 rnA 1Standby CurrentPower S~y current(RAS = CA = VIH)ICC2 10 rnARefresh Current*- One Module SelectedAverage power supply current ICC3 45 rnA(RAS cycling, CAS = VIH; tRC =min.)Page Mode Current* - One ModuleSelectedAverage power supply current(RAS = VIL, CAS cycling; tpc =min.)Refresh Current* - Two ModuleSelectedAverage power supply current(RAS cycling, CAS = VIH: tRC = min.)Input Leakage CurrentInput leakage current, any input(OV ~ VIN ~ 5.5V, all otherpins not under test = OV)ICC4 65 rnA 1ICC5 80 rnA1L1 -10 10 p..AOutput Leakage Current(Data out is disabled, ILO -10OV ~ VOUT ~ 5.5V)10 p..AOutput LevelsOutput high voltageOOH=-5mA)VOH 2.4 VOutput low voltageOOL=4.2mA)VOL 0.4 VNote·: ICC is dependent on output loading and cycle rates. Specified values are obtained with theoutput open.223

• DYNAMIC RAM· MSM37S64ARS/37S64RS •• -------------CAPACITANCE(Ta= 25°C, f = 1 MHz)ParameterSymbolMax.UnitInput Capacitance (Ao - A7, DIN)Input Capacitance (RAS1, RAS2)Input Capacitance (CAS)Input Capacitance (WE)Output Capacitance (DOUT)CIN1CIN2CIN3CIN4COUT10 pF10 pF15 pF12 pF14 pFAC CHARACTERISTICS(Recommended operating conditions unless otherwise noted.)Note 1,2,3Parameter Symbol UnitsMSM37S64-15Min. Max.MSM37S64-20Min.Max.NoteRefresh period tREF ms 22Random read or writecycle timetRC ns 270330Read-write cycle time tRWC ns 270Page mode cycle time tpc ns 170330225Access time from RAS tRAC ns 150Access time from CAS tCAC ns 100200 4,6135 5,6Output buffer turn-offdelaytOFF ns 0 400 50Transition time tT ns 3 35RAS precharge time tRP ns 100RAS pulse width tRAS ns 150 10,000RAS hold time tRSH ns 100CAS precharge time tcp ns 60CAS pulse width tCAS ns 100 10,000CAS hold time tCSH ns 150RAS to CAS delay time tRCD ns 25 503 50120200 10,00013580135 10,00020030 65 7CAS to RAS prechargetimetCRP ns 00Row Address set-up time tASR ns 00224

---------'----__._ DYNAMIC RAM· MSM37S64ARS/37S64RS -AC CHARACTERISTICS (Continued)(Recommended operating conditions unless otherwise noted.)Parameter Symbol UnitsMSM37S64-15Min. Max.MSM37S64-20Min.Max.NoteRow Address hold time tRAH ns 1520Column Address set-uptimetASC ns 00Column Address holdtimetCAHns 4555Column Address holdtime reference to RAStARns 95120Read command set-uptimetRCS ns 00Read command hold time tRCH ns 00Write command set-uptimetwcs ns -10-10 8Write command hold time tWCH ns 4555Write command hold timereferenced to RAStWCRns 95120Write command pulsewidthtwp ns 4555Write command to RASlead timetRWLns 4555Write command to CASlead timetCWLns 4555Data-in set-up time tos ns 0Data-in hold time tOH ns 45055Data-in hold timereferenced to RAStOHRns 95120CAS to WE delay tcwo ns 60RAS to WE delay tRWO ns 11080 8145 8Read command holdtime reference to RAStRRH ns 2025225

• DYNAMIC RAM· MSM37S64ARS/37S64RS ... -------------AC CHARACTERISTICS(Recommended operating conditions unless otherwise noted.) Note 1,2,3Parameter Symbol UnitsMSM37S64A- MSM37S64A-15 20Min. Max. Min. Max.NoteRefresh period tREF ms 2 2Random read or writecycle time tRCns 260 330Read-write cycle time tRWC ns 280 345Page mode cycle time tpc ns 145 190Access time from RAS tRAC ns 150 200 4,6Access time from CAS tCAC ns 75 100 5,6Output buffer turn-offdelaytOFF ns 0 40 0 50Transition time tT ns 3 35 3 50RAS precharge time tRP ns 100 120RAS pulse width tRAS ns 150 10,000 200 10,000RAS hold time tRSH ns 75 100CAS precharge time(page mode only) tcp ns 60 80CAS precharge time tCPN ns 35 45CAS pulse width tCAS ns 75 10,000 100 10,000CAS hold time tCSH ns 150 200RAS to CAS delay time tRCO ns 25 75 30 100 7CAS to RAS prechargetimetCRP ns 0 0Row Address set-up time tASR ns 0 0Row Address hold time tRAH ns 15 20Column Address-set-uptimetASC ns 0 0Column Address holdtimeColumn Address holdtime reference to RAStCAHtARns 20 25ns 95 125Read command set-uptimetRCS ns 0 0226

------------______ DYNAMIC RAM· MSM37S64ARS/37S64RS _AC CHARACTERISTICS (Continued)(Recommended operating conditions unless otherwise noted.)Parameter Symbol UnitsMSM37S64A-15Min. Max.MSM37S64A-20Min.Max.NoteRead command hold time tRCH ns 00Write command set-uptimetwcs ns -10-10 8Write command hold time tWCH ns 4555Write command hold timereferenced to RASWrite command pulsewidthWrite command to RASlead timeWrite command to CASlead timetWCR ns 120twp ns 45tRWL ns 45tCWL ns 45155555555Data-in set-up time tDS ns 0Data-in hold time tDH ns 45055Data-in hold timereferenced to RAStDHR ns 120155CAS to WE delay tCWD ns 45RAS to WE delay tRWD ns 12055 8155 8Read command holdtime reference to RAStRRH ns 00Notes: 1 An initial pause of 100 P.s is required after power-up followed by. any 8 RAS cycles(Example: RAS only) before proper device operation is achieved.2345678AC measurements assume at tT = 5 nsVIH (Min.) and VIL (Max.) are reference levels for measuring timing of input Signals. Alsotransition times are measured between VIH and VIL.Assumes that tRCD < tRCD (Max.)If tRCD is greater than the maximum recommended value shown in this table, tRAC willincrease by the amount that tRCD exceeds the value shown.Assumes that tRCD < tRCD (Max.).Measured with a load circuit equivalent to 2TTL loads and 100 pF.Operation within the tRCD (Max.) limit insures that tRAC (Max.) can be met. tRCD (Max.)is specified as a reference point only; if tRCD is greater than the specified tRCD (Max.)limit, then access time is controlled exclusively by tCAC.twcs, tCWD and tRWD are not restrictive operating parameters. They are included inthe data sheet as electrical characteristics only; if twcs ~ twcs (min.), the cycle is anearly write cycle and the data out pin will remain open circuit (high impedance) throughoutthe entire cycle; if tCWD ~ tCWD (min.) and tRWD > tRWD (min.) the cycle is readwritecycle and the data out will contain data read from the selected cell; if neither of theabove sets of conditions is satisfied the condition of the data out (at access time) isindeterminate.227

• DYNAMIC RAM· MSM37S64ARS/37S64RS •• -------------READ CYCLE TIMING~-----------------tRC-----------------1~RAS1, RAS2 vVIH -IL -~-----------tRAs------------~--___._1 1-----tAR "I Ir-------'1-----+--tRsH-----iVII.j _ ---..:....:...---+---.- f----+--tCAS----I r--lo------..VIL -'-----VIH­Addresses V I L -I tRCS~~IIHL=~DOUT VOH- --------..,1 OPENVOL-!---tCAC~1·~-------tRAC----------~Valid Data~"H", "L" = Don't Care228

------------____ DYNAMIC RAM' MSM37S64ARS/37S64RS _WRITE CYCLE TIMING(EARLY WRITE)tRSH___ -++==~~=;II-tCAS-----1 .t!--Ir-"';;;';"~-"----,.AddressesV,H - ~V,L -~~~~~~Jt~~~=t~~t=~::~~::~~~~~~~~~V I H - 77'77:~"'7/'77i7'7'!"77,", 1;--"'---.,.1 n-r7"T7".,.....,..,.,...,...,'"?'"?'rr.,..,.,-r7"T7",..,.,,..,..,.~DOUTV,L - ';"':"'~~~"""I~~'-V r-------"] '(.""'-~~~~~:...:...:~""'-~~""'-"-"-f----tDHR------IVOH- _______--1OPENVOL-~ "H", "L" =Don't CareREAD-WRITE/READ-MODIFY-WRITE CYCLERAS1.RAS2~:~ ::::CAS V,H -V,L -tARtRWC--tRAStCSHtRSHtCASAddressesV,H -V,L -WEV,H -V,L -DOUTVOH-VOL-tCAC~ tOFF~--H-----~D,NV,H -V,L -~ "H", "L" = Don't Care229

_ DYNAMIC RAM· MSM37S64ARS/37S64RS ___ ------------RAS ONLY REFRESH TIMING(CAS: VIHo WE & DIN: Don't care)Addresses ~:~_~ RowAddress~RAH~tASRVOH -DOUT ____________ ~VOL -OPEN~"H", "L" = Don't CarePAGE MODE READ CYCLE---- VIH­RAS1,RAS2VIL_VIH­Adresses V I L -tRAS----------------4;}--~~------~----------------~ tRSH tRPtCAS tCRPI~"H" ,"L"= Don't Care230

------------__ DYNAMIC RAM· MSM37S64ARS/37S64RS _PAGE MODE WRITE CYCLEAddressesVIH -=,*'?n~1VIL-~"f~~~~~~~~~~~~~~·~~~~~~~~~~~DINVIH - ~m~.J.""':':'-=~.L",~"-j,.~""':;;~_~7""'~fJ,.;. [,-~;...;..."j ,",,-rr,..,..,~...,...,"""vlL -~ "H", "L" = Don't CarePAGE MODE, READ-MODIFY-WRITE CYCLERAS1,RAS2VIH -VIL -CAS VIH -VIL -AddressesWEDINDOUTVIH -VIL -VIH -VIL -VOH-VOL-~ "H", "L" = Don't Care231

• DYNAMIC RAM· MSM37S64ARS/37S64RS •• -------------HIDDEN REFRESHVIH_Addresses V I L -vlL VIH- - ~ tCAC~tRACDOUTVOH-_____ VOL- OPEN_~-----------------------______________________ Valid Data_~ "H", "L" = Don't CareFUNCTIONAL DESCRIPTIONAddress Inputs:A total of sixteen binary input address bitsare required to decode any 1 of 65536 storagecell locations within the one module. Eight rowaddressbits are established on the input pins(Ao - A7) and latched with the Row AddressStrobe (RAS). The eight column-address bits areestablished on the input pins and latched withthe Column Address Strobe (CAS). All input addressesmust be stable on or before the fallingedge of RAS, CAS is internally inhibited (or"gated") by RAS to permit triggering of CAS assoon as the Row Address Hold Time (tRAH) specificationhas been satisfied and the addressinputs have been changed from row-addressesto column-addresses. The top module or bottommodule is selected with RAS1 input and RAS2input.Write Enable:The read mode or write mode is selected withthe WE input. A logic high (1) on WE dictatesread mode; logic low (0) dictates write mode.Data input is disabled when read mode isselected.Data Input:Data is written into the MSM37S64 during awrite or read-write cycle. The last falling edge ofWE or CAS is a strobe for the Data In (DIN)register. In a write cycle, if WE is brought low(write mode) before CAS, DIN is strobed by CAS,and the set-up and hold times are referenced toCAS. In a read-write cycle, WE will be delayeduntil CAS has made its negative transition. ThusDIN is strobed by WE, and set-up and hold timesare referenced to WE.Data Output:The output buffer is three-state TTL compatiblewith a fan-out of two standard TTL loads.Data-out is the same polarity as data-in. Theoutput is in a high impedance state until CAS isbrought low. In a read cycle, or read-write cycle,~ output is valid after tRAC from transition ofRAS when tRCD (Max.) is satisfied, or after tCACfrom transition of CAS when the transitionoccurs after tRCD (Max.). Data remain valid untilCAS is returned to a high level. In a write cyclethe identical sequence occurs, but data is notvalid.Page Mode:Page-mode operation permits strobing therow-address into the MSM37S64 while maintainingRAS at a logic low (0) throughout all successivememory operations in which the rowaddressdoesn't change. Thus the power dissipatedby the negative going edge of RAS issaved. Further, access and cycle times are decreasedbecause the time normally required tostrobe a new row-address is eliminated.Refresh:Refresh of the dynamic memory cells is accomplishedby performing a memory cycle at232

______________ 1. DYNAMIC RAM' MSM37S64ARS/37S64RS •each of the 128 row-addresses (AD - Ae) atleast every two milliseconds. During refresh,either VIL or VIH is permitted for A7. RAS only refreshavoids any output during refresh becausethe output buffer is in the high impedance stateunless CAS is brought low. Strobing each of 128row-addresses with RAS will cause all bits ineach row to be refreshed. Further RAS-only refreshresults in a substantial reduction in powerdissipation.Hidden Refresh:RAS ONLY REFRESH CYCLE may take placewhile maintaining valid output data. This featureis referred to as Hidden Refresh.Hidden Refresh is performed by holding CASas VIL from a previous memory read cycle.233

_O_K __ I __se_rn_I_C_O_nc:I_U_c_.o_r ____ ~ ~MSC2301 YS9/KS9 - ~65,536 BY 9 BIT DYNAMIC RAM MODULEGENERAL DESCRIPTIONThe Oki MSC2301 YS9/KS9 is a fully decoded, 65,536 words x 9 bit NMOS dynamic randomaccess memory composed of nine 64K DRAMs in plastic leaded chip carrier. The mounting of ninePLCCs together with nine 0.2J.tF decoupling capacitors on a 30 pin glass epoxy Single-In-Line Packageprovides any application where high density and large capacity of storage memory are required.The electrical characteristics of the MSC2301 YS9/KS9 are quite same as the original MSM3764A;each timing requirements are noncritical, and power supply tolerance is very wide.FEATURES• 65,536 word x 9 bit Organization• Single +5V Supply (10% Tolerance)• 30-Pin Socket Insertable Module• Refresh Period ... 2ms (128 cycles)• All Inputs, Outputs, ClocksFully TTL compatible• 3-States Outputs• Common CAS Control for Eight CommonData-In and Data-Out LinesFUNCTIONAL BLOCK DIAGRAM• Separate CAS Control for One Separate Pairof Data-In and Data-Out Lines• Row Access Time;120ns max. (MSC2301-12YS9/KS9)150ns max. (MSC2301-15YS9/KS9)• Low Power Dissipation;2970mW max. (MSC2301-12YS9/KS9)2725mW max. (MSC2301-15YS9/KS9)• Operating Temperature ... O°C to 70°CA.-A'Sf-+-r:;:;::-;:-f--- ~t--- e:AllWE001I IOvre visWil DQ5f-+- I A~A- Ir---- RASf---o CASDO'WEI IDVfCVf~il DOS003DO'CAS9osVccVss,.....l-l--!--+- A.-Aj---.RASj--. CASWE) ~1l_D07,..L--L-~ A.-A-~~'-----

---------------__ DYNAMIC RAM· MSC2301 YS9/KS9 _PIN ASSIGNMENTMSC2301YS9MSC2301KS9PIN No. PIN NAME PIN No. PIN NAME PIN No. PIN NAME1 VCC 11 A4 21 WE2 CAS" 12 A5 22 VSS3 001 13 004 23 0074 AO 14 A6 24 NC5 Al 15 A7 25 0086 002 16 005 26 097 A2 17 NC 27 RAS8 A3 18 NC 28 CAS99 VSS 19 NC 29 0910 003 20 006 30 VCCABSOLUTE MAXIMUM RATINGS (See Note)Rating Symbol Value UnitVoltage on any pin relative to VSS VIN. VOUT -1 to +7 VVoltage on Vee supply relative to VSS Vee -1 to +7 VOperating temperature Topr Ot070 °eStorage temperature Tstg -40 to +125 °ePower dissipation PD 9 WShort circuit output current 50 mANote: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operationshould be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.235

• DYNAMIC RAM· MSC2301 YS9/KS9 .1---------------RECOMMENDED OPERATING CONDITIONS (Referenced to VSS)Parameter Symbol Min. Typ. Max. UnitOperatingtemperatureSupply VoltageInput High Voltage,all inputsInput Low Voltage,all inputsVCC 4.5 5.0 5.5 VVSS 0 0 0 VVIH 2.4 6.5 VVIL --1.0 0.8 VO°C to +70°CDC CHARACTERISTICS(Recommended operating conditions unless otherwise noted.)1 20ns MODULE 150ns MODULEParameter Symbol UnitMin. Max. Min. Max.Operating Current·Average power supply current ICC1 540 495 mA(RAS, CAS cycling; tRC = min.)Standby Current'Power supply current ICC2 45 45 mA(RAS = CAS =VIH)Refresh Current'Average power supply current ICC3 360 360 mA(RAS cycling, CAS = VIH; tRC =min.)Page Mode Current·Average power supply current ICC4 450 405 mA(RAS = VIL, CAS cycling; tpc =min.)Input Leakage CurrentInput leakage current, any input(OV S VIN S 5.5V, all otherpins not under test = OV)IL1 -90 90 -90 90 /LAOutput Leakage Current(Data out is disabled, ILO -10 10 -10 10 /LAOV S VOUT S 5.5V)Output LevelsOutput high voltage VOH 2.4 2.4 VUOH =-5mA)Output low voltage VOL 0.4 0.4 VUOL =4.2mA)Note": ICC is dependent on output loading and cycle rates. Specified values are obtained with theoutput open.236

________________ • DYNAMIC RAM' MSC2301 YS9/KS9 •CAPACITANCE(Ta = 25°C, f = 1 MHz)ParameterSymbolTyp.Max.UnitInput Capacitance (AD ~ A7)Input Capacitance (RAS, CAS, WE)Data Input/OutputCapacitance (DO)Input Capacitance (CAS9)Input Capacitance (09)Output Capacitance (09)Capacitance measured with Boonton Meter.CIN1 40CIN2 40COO 7CIN3 5CIN4 4COUT 470 pF75 pF20 pF10 pF10 pF15 pFAC CHARACTERISTICS(Recommended operating conditions unless otherwise noted.)Note1,2,3Parameter Symbol UnitsMSC2301-12YS/KSMin. Max.MSC2301-15YS/KSMin.Max.NoteRefresh period tREF ms 22Random read or writecycle timetRCns 220260Page mode cycle time tpc ns 120145Access time from RAS tRAC ns 120--Access time from CAS tCAC ns 60150 4,675 5,6Output buffer turn-offdelaytOFF ns 0 350 40Transition time tT ns 3 35RAS precharge time tRP ns 90RAS pulse width tRAS ns 120 10,000RAS hold time tRSH ns 60CAS precharge time tcp ns 50CAS pulse width tCAS ns 60 10,000CAS hold time tCSH ns 1203 35100150 10,000756075 10,000150237

_ DYNAMIC RAM· MSC2301 YS9/KS9 ------------------AC CHARACTERISTICS (Continued)(Recommended operating conditions unless otherwise noted.)Note 1,2,3Parameter Symbol UnitsMSC2301-12YS/KSMin. Max.MSC2301-15YS/KSMin.Max.NoteRAS to CAS delay time tRCD ns 25 6025 75 7CAS to RAS prechargetimetCRP ns 00Row Address set-up time tASR ns 0Row Address hold time tRAH ns 15015Column Address set-uptimetASC ns 00Column Address holdtimetCAHns 2020Column Address holdtime reference to RASRead command set-uptimetAR ns 80tRCS ns 0950Read command hold time tRCH ns 00Write command set-uptimetwcs ns -10-10Write command hold time tWCH ns 4045Write command hold timereferenced to RASWrite command pulsewidthWrite command to RASlead timetWCR ns 100twp ns 40tRWL ns 401204545Write command to CASlead timetCWLns 4045Data-in set-up time tDS ns 0Data-in hold time tDH ns 40045Data-in hold timereferenced to RAStDHR ns 100120238

----------------1. DYNAMIC RAM· MSC2301 YS9/KS9 •Notes:An initial pause of 100 Ils is required after power-up followed by any 8 RAS cycles(Example: RAS only) before proper device operation is achieved.2 AC measurements assume at tT = 5 ns3 VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals. Alsotransition times are measured between VIH and VIL.4 Assumes that tRCD < tRCD (Max.)If tRCD is greater than the maximum recommended value shown in this table, tRAC willincrease by the amount that tRCD exceeds the values shown.5 Assumes that tRCD < tRCD (Max.).6 Measured with a load circuit equivalent to 2TTL loads and 100 pF.7 Operation within the tRCD (Max.) limit insures that tRAC (Max.) can be met. tRCD (Max.)is specified as a reference point only; if tRCD is greater than the specified tRCD (Max.)limit, then access time is controlled exclusively by tCAC.READ CYCLE TIMINGVIH­Addresses V I L -I tRCS~~:~=~ I--tCAC1~·~--------tRAC--~----~~DOUT VOH- ----------..,1 OPENVOL-Valid Data~ "'H"', "'L"' = Don't Care239

• DYNAMIC RAM· MSC2301 YS9/KS9 •• ----------------WRITE CYCLE TIMING(EARLY WRITE)RASVIH -VIL -CAS VIH -VIL -tRSH___ -+-t==~~~t_I-tCAS-----I A--+---=';"';';"'---'-----.AddressesVIH -VIL -WEVIH - %VIL -DINVIH -VIL -DOUTVOH-VOL-~------tDHR------~OPEN~ "H", "L" = Don't CareRAS ONLY REFRESH TIMING(CAS: VIH,W'E'& DIN: Don'teare)Addresses ~:~~~ASR~="'wm""'7"fT"""""'~,"" "'-R-O-W-A-d-d-r-es-~--.LL'R,3-~R,"jt~RASDOUTVOH ~VOL ~OPEN~"H", "L" = Don't Care240

---------------...... DYNAMIC RAM· MSC2301 YS9/KS9 •PAGE MODE READ CYCLE~-----------------tRAS--------------------.,CASVIH­VIL -DOUT VOH - -----C)PI:N------

• DYNAMIC RAM· MSC2301 YS9/KS9 .---------------HIDDEN REFRESH1-----Read Cycle----1--~-tAR--jIf-tRPAddressesDOUTrn!"H", "L" = Don't CareFUNCTIONAL DESCRIPTIONAddress Inputs:A total of sixteen binary input address bitsare required to decode any 1 of 65536 storagecell locations within the MSC2301. Eight rowaddressbits are established on the input pins(AD - A7) and latched with the Row AddressStrobe (RAS). The eight column-address bits areestablished on the input pins and latched withthe Column Address Strobe (CAS). All input addressesmust be stable on or before the fallingedge of RAS, CAS is internally inhibited (or"gated") by RAS to permit triggering of CAS assoon as the Row Address Hold Time (tRAH) specificationhas been satisfied and the addressinputs have been changed from row-addressesto column-addresses.Write Enable:The read mode or write mode is selected withthe WE input. A logic high (1) on WE dictatesread mode; logic low (0) dictates write mode.Data input is disabled when read mode isselected.Data Input:Data is written into the MSC2301 during awrite cycle. The last falling edge of WE or CAS isa strobe for the Data In (DIN) register. In a writecycle, if WE is brought low (write mode) beforeCAS, DIN is strobed by CAS, and the set-up andhold times are referenced to CAS.Data Output:The output buffer is three-state TTL compatiblewith a fan-out of two standard TTL loads.Data-out is the same polarity as data-in. Theoutput is in a high impedance state until CAS isbrought low. In a read cycle, the output is validafter tRAC from transition of RAS when tRCD(Max.) is satisfied, or after tCAC from transitionof CAS when the transition occurs after tRCD(Max.). Data remain valid until CAS is returned toa high level. In a write cycle the identical sequenceoccurs, but data is not valid.Page Mode:Page-mode operation permits strobing therow-address into the MSC2301 while maintainingRAS at a logic low (0) throughout all successivememory operations in which the rowaddressdoesn't change. Thus the pow~issipatedby the negative going edge of RAS issaved. Further, access and cycle times aredecreased because the time normally requiredto strobe a new row-address is eliminated.Refresh:Refresh of the dynamic memory cells is accomplishedby performing a memory cycle ateach of the 128 row-addresses (AD - As) atleast every two milliseconds. During refresh,either VIL or VIH is permitted for A7. RAS only refreshavoids any output during refresh becausethe output buffer is in the high impedance stateunless CAS is brought low. Strobing each of 128row-addresses with RAS will cause all bits in242

---------------___ DYNAMIC RAM· MSC2301 YS9/KS9 _each row to be refreshed. Further RAS-only refreshresults in a substantial reduction in powerdissipation.Hidden Refresh:RAS ONLY REFRESH CYCLE may take placewhile maintaining valid output data. This featureis referred to as Hidden Refresh.Hidden Refresh is performed by holding CASas VIL from a previous memory read cycle.243

• DYNAMIC RAM· MSC2301 YS9/KS9 .-----------'------MSC2301YS988.93.3882.14"I 5.08MAX-3.18..............."""""'" .-.- C')ciz"I:.~o---+1 ~';;Ill~~

OKI semiconductorMSC2304YSS/KSS262,144 BY 8 BIT DYNAMIC RAM MODULEGENERAL DESCRIPTIONThe Oki MSC2304YSS/KSS is a fully decoded, 262,144 words x S bit NMOS dynamic randomaccess memory composed of eight 256K DRAMs in plastic leaded chip carrier (MSM41256JS). Themounting of eight PLCCs together with eight 0.2/LF decoupling capacitors on a 30 pin glass epoxySingle-In-Line Package provides any application where high density and large capacity of storagememory are required. The electrical characteristics of the MSC2304 YSS/KSS are quite same as theoriginal MSM41256JS; each timing requirements are noncritical, and power supply tolerance is verywide.FEATURES• 262,144 word x S bit Organization• Single +5V Supply (1 0% Tolerance)• 30-Pin Socket Insertable Module• Refresh Period ... 4ms (256 cycles)• All Inputs, Outputs, ClocksFully TTL compatible• 3-States Outputs• Common CAS Control for Eight CommonData-In and Data-Out LinesFUNCTIONAL BLOCK DIAGRAM• Row Access Time;120ns max. (MSC2304-12YSS/KSS)150ns max:iMSC2304-15YSS/KSS)• Low Power Dissipation;30S0mW max. (MSC2304-12YSS/KSS)2860mW max. (MSC2304-15YS8/KS8)• Operating Temperature ... ODC to 70DCACt-AsRAS-=~~t===============~CAS --.-++---------"WE-"T-""I-++-----------,D02 -+-II-+-h-~OQ3OQ4 -----====:;~Vee ~~c~. :=r7:c.I~-----~Vss -"----I'-----4-_______-----...l245

• DYNAMIC RAM· MSC2304YSS/KSS .1----------------PIN ASSIGNMENTMSC2304YS8\~COCQ:J:!:K:~LD:I- ________ O~N~~~wR$mO~NM~~w~oomoMSC2304KS8 ~~~~~~~~~~=========~~~~~~~~~~~~ H----_____ O~@M~~~~OOmO~@M~~~R$ma~~~S~Sb$~==========~~~~~~~~~~~PIN No. PIN NAME PIN No. PIN NAME1~ 16 D052 CAS 17 A83 D01 18 NC4 AO 19 NC5 A1 20 D066 D02 21 WE7 A2 22 VSS8 A3 23 D079 VSS 24 NC10 D03 25 D0811 A4 26 .lli2.12 A5 27 RAS13 D04 28 NC14 A6 29 NC15 A7 30 VCCABSOLUTE MAXIMUM RATINGS (See Note)Rating Symbol Value UnitVoltage on any pin relative to VSS VIN. VOUT -1 to +7 VVoltage on Vee supply relative to VSS Vee -1 to +7 VOperating temperature Topr o to 70 °eStorage temperature Tstg -40 to +125 °ePower dissipation PD 8 WShort circuit output current 50 mANote: Perrolanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operationshould be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.246

---------------1. DYNAMIC RAM· MSC2304YSS/KSS •RECOMMENDED OPERATING CONDITIONS (Referenced to VSS)Parameter Symbol Min. Typ. Max. UnitOperatingtemperatureSupply VoltageInput High Voltage,all inputsInput Low Voltage,all inputsVCC 4.5 5.0 5.5 VVSS 0 0 0 VVIH 2.4 6.5 VVIL -1.0 0.8 V0°Cto+70°CDC CHARACTERISTICS(Recommended operating conditions unless otherwise noted.)120ns MODULE 150ns MODULEParameter Symbol UnitMin. Max. Min. Max.Operating Current"Average power supply current(RAS, CAS cycling; tRC = min.)ICC1 560 520 mAStandby CurrentPower supply current(RAS = CAS = VIH)ICC2 40 40 mARefresh CurrentAverage power supply current ICC3 440(RAS cycling, CAS = VIH; tRC =min.)400 mAPage Mode Current"Average power supply current(RAS = VIL, CAS cycling; tpc =min.)ICC4 440 400 mAInput Leakage CurrentInput leakage current, any input(OV :::: VIN :::: 5.5V, all otherpins not under test = OV)1L1 -80 80 -80 80 /LAOutput Leakage Current(Data out is disabled, ILO -10OV :::: VOUT :::: 5.5V)10 -10 10 /LAOutput LevelsOutput high voltage(iOH=-5mA)VOH 2.4 2.4 VOutput low voltage(iOL=4.2mA)VOL 0.4 0.4 VNote*: ICC is dependent on output loading and cycle rates. Specified values are obtained with theoutput open.247

.DYNAMICRAM·MSC2304YSS/KSS.-------------------------------CAPACITANCE(Ta = 25°C, f = 1 MHz)ParameterSymbolTyp. Max. UnitInput Capacitance (Ao -AalCIN137 60 pFInput Capacitance (RAS, CAS, WE)Data Input/OutputCapacitance (DO)Capacitance measured with Boonton Meter.CIN2COO35 65 pF7 20 pFAC CHARACTERISTICSParameterSymbolUnitsMSC2304-12YS/KSMSC2304-15YS/KSNoteMin. Max. Min. Max.Refresh periodtREFms4 4Random read or writecycle timetRCns230 260Page mode cycle timetpcns125 145Access time from RAStRACns120 150 4,6Access time from CAStCACns60 75 5,6Output buffer turn-offdelaytOFFns0 40 0 40Transition timetTns3 50 3 50RAS precharge timetRPns100 100RAS pulse widthtRASns120 10,000 150 10,000RAS hold timetRSHns60 75CAS precharge timetcpns55 60CAS pulse widthtCASns60 10,000 75 10,000CAS hold timetCSHns120 150RAS to CAS delay timetRCOns25 60 25 75 7CAS to RAS prechargetimetCRPns0 0248

----------------. DYNAMIC RAM· MSC2304YS8/KS8 •AC CHARACTERISTICS (CONT.)Parameter Symbol UnitsMSC2304- MSC2304-12YS/KS 15YS/KSMin. Max. Min. Max.NoteRow Address set-up time tASR ns 0 0Row Address hold time tRAH ns 15 20Column Address set-uptimeColumn Address holdtimeColumn Address holdtime reference to RASRead command set-uptimetASC ns 0 0tCAH ns 3035tAR ns 90110tRCS ns 0 0Read command hold time tRCH ns 0 0Write command set-uptimetwcs ns 0 0Write command hold time tWCH ns 40 45Write command hold timereferenced to RAStWCRns 100 120Write command pulsewidthtwp ns 40 45Write command to RASlead timetRWLns 40 45Write command to CASlead time tCWL ns 40 45Data-in set-up time tDS ns 0 0Data-in hold time tDH ns 40 45Data-in hold timereferenced to RAS tDHR ns 100 120Note 1,2,3: Under recommended operating conditions249

• DYNAMIC RAM· MSC2304YSS/KSS .1---------------Notes: 1234567An initial pause of 100 p's is required after power-up followed by any 8 RAS cycles(Example: RAS only) before proper device operation is achieved.AC measurements assume at tT = 5 nsVIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals. Alsotransition times are measured between VIH and VIL·Assumes that tRCD < tRCD (Max.)If tRCD is greater than the maximum recommended value shown in this table, tRAC willincrease by the amount that tRCD exceeds the values shown.Assumes that tRCD < tRCD (Max.).Measured with a load circuit equivalent to 2TTL loads and 100 pF.Operation within the tRCD (Max.) limit insures that tRAC (Max.) can be met. tRCD (Max.)is specified as a reference point only; if tRCD is greater than the specified tRCD (Max.)limit, then access time is controlled exclusively by tCAC.READ CYCLE TIMINGtRCRASVIH -VIL -CASVIH -VIL -VIH-Addresses VIL -DWEDOUTI tRcsHVIH-~rVIL-!--tCACtRACI-VOH-I OPENVOL-J tOFFValid Data~OOHOO, ooLoo = Don't Care250

• DYNAMIC RAM' MSC2304YSS/KSS •• ---------------PAGE MODE READ CYCLE~----------------tRAS---------------------VIH­Adresses VI L -~"H","L"=Don't CarEPAGE MODE WRITE CYCLEAddressesVIH -VIL -~~!ll~~~!ll!f~~~~VIH -,,""""~~VIL-~"f~~~~~~~~~~~~~~~~~~~~~~~~~DINVIH -V IL - ~'4'o"l1'------III~~ l'----J'f '(.""'"""'~l\--;"";"-Ji """"'''''''...:..::~"'''~ "H", "L" = Don't Care252

_______________.... DYNAMIC RAM· MSC2304YSS/KSS •HIDDEN REFRESHAddressesI tRCS IDOUT~ "H", "L" = Don't CareFUNCTIONAL DESCRIPTIONAddress Inputs:A total of eighteen binary input address bitsare required to decode any 1 of 262144 storagecell locations within the MSC2304. Nine rowaddressbits are established on the input pins(Ao - A8I and latched with the Row AddressStrobe (RAS). The Nine column-address bits areestablished on the input pins and latched withthe Column Address Strobe (CAS). All input addressesmust be stable on or before the fallingedge of RAg, CAS is internally inhibited (or"gated") by RAS to permit triggering of CAS assoon as the Row Address Hold Time (tRAH) specificationhas been satisfied and the addressinputs have been changed from row-addressesto column-addresses.Write Enable:The read mode or write mode is selected withthe WE input. A logic high (1) on WE dictatesread mode; logic low (0) dictates write mode.Data input is disabled when read mode isselected.Data Input:Data is written into the MSC2304 during awrite. The last falling edge of WE or CAS is astrobe for the Data In (DIN) register. In a writecycle, if WE is brought low (write mode) beforeCAS, DIN is strobed by CAS, and the set-up andhold times are referenced to CAS.Data Output:The output buffer is three-state TTL compatiblewith a fan-out of two standard TTL loads.Data-out is the same polarity as data-in. Theoutput is in a high impedance state until CAS isbrought low. In a read cycle, the output is validafter tRAC from transition of RAS when tRCD(Max.) is satisfied, or after tCAC from transitionof CAS when the transition occurs after tRCD(Max.). Data remain valid until CAS is returned toa high level. In a write cycle the identical sequenceoccurs, but data is not valid.Page Mo~e:Page-mode operation permits strobing therow-address into the MSC2304 whilemaintainingRAS at a logic low (0) throughout allsuccessive memory operations in which therow-address doesn't change. Thus the powerdissipated by the negative gOing edge of RAS issaved. Further, access and cycle times aredecreased because the time normally requiredto strobe a new row-address is eliminated.Refresh:Refresh of the dynamic memory cells is accomplishedby performing a memory cycle ateach of the 256 row-addresses (Ao - A7) atleast every four milliseconds. During refresh,either VIL or VIH is permitted for As. RAS only refreshavoids any output during refresh becausethe output buffer is in the high impedance stateunless CAS is brought low. Strobing each of 256row-addresses with RAS will cause all bits ineach row to be refreshed. Further RAS-only refreshresults in a substantial reduction in powerdissipation.Hidden Refresh:RAS ONLY REFRESH CYCLE may take placewhile maintaining valid output data. This featureis referred to as Hidden Refresh.Hidden Refresh is performed by holding CASas VIL from a previous memory read cycle.253

• DYNAMIC RAM . MSC2304YSS/KSS •MSC2304YS8 ,----------- ..88.982.14Glass-Epox Y B oard18pin PlCCChip Condenser1. Substrate: GlASS-EP2. Through Hole. OXYFollowed by S Copper Plating3. Contact pads:~:b PlatingFollowed by S pper Platingon Copper FI n/(Pb Plating4. S rf 1m 18/Lmt)u ace Coating: Ph 00 t Film . Resist88.982.1410C\IoTin-lead SolderChipCond enser1. Substrate: GlASS-EP2. Through Hole. OXYFollowed by S· Copper Plating3 n/PbPI t". Contact Pads. C a IngFollowed by S opper Platingon Copper Fil nt b Plating4. Surf m 18/Lmt)ace Coating: Photo Film Resist254

---------------..... DYNAMIC RAM· MSC2304YSS/KSS •MSC2304YSS/KSS (SIP/SIM) DERATING CURVE~:;J"§CIla.ECIll-e:CIl:0E«:~I-(OC)7060504030AllowableNot Allowable-~----"" .... ........ "........ ...."....-AirFlow---- :Om/s------ : lm/s------ : 3m/s20L----4 ____-L____-L____ ~~--~--2 3 4 f 54.35 MHz (MHz)l/tRC. Cycle Rate255

OKI semiconductorMSC2304YS9/KS9262,144 BY 9 BIT DYNAMIC RAM MODULEGENERAL DESCRIPTIONThe Oki MSC2304YS9/KS9 is a fully decoded, 262,144 words x 9 bit NMOS dynamic randomaccess memory composed of nine 256K DRAMs in plastic leaded chip carrier (MSM41 256JS). Themounting of nine PLCCs together with nine 0.2/-tF decoupling capacitors on a 30 pin glass epoxySingle-In-Line Package provides any application where high density and large capacity of storagememory are required. The electrical characteristics of the MSC2304YS9/KS9 are quite same as theoriginal MSM41256JS; each timing requirements are noncritical, and power supply tolerance is verywide.FEATURES• 262,144 word x 9 bit Organization• Single +5V Supply (10% Tolerance)• 30-Pin Socket Insertable Module• Refresh Period ... 4ms (256 cycles)• All Inputs, Outputs, ClocksFully TTL compatible• 3-States Outputs• Common CAS Control for Eight CommonData-In and Data-Out Lines• Separate CAS Control for One Separate Pairof Data-In and Data-Out Lines• Row Access Time;1 20ns max. (MSC2304-1 2YS9/KS9)150ns max. (MSC2304-15YS9/KS9)• Low Power Dissipation;3465mW max. (MSC2304-12YS9/KS9)3218mW max. (MSC2304-15YS9/KS9)• Operating Temperature ... O°C to 70°CFUNCTIONAL BLOCK DIAGRAM. :::J--r--r;:;:-I----- RASI----- CAllWI':D01I IDvfc Vi§~'l DOSD02DO.r-'---If-+-A~A.1-----liA!lI----- CASWEL ,ovre vf~ Il ooer-'-'-~Ao-A8I----- i'iASI------ CASWE 0I .Dvfc vr fl D07r-'-'-'--+- A~A._RAS~=WEDO. e ail 008I ~~SSCAS9D9VCCVSS~c, ___ ~ C.r--.-+--A~A.------t RASCAllWEr IDICCVf~~.-+-~~RAS~CASWE.'t,ccI v~~ilr'---'-~Ao-A8~AAllf------=WEI ,~ccv~,\'1r-'---'-f-+- ~.r-- RASr----- CASWEI "v,ccV~SOILr--rl--l..A~A.~AASCAllWED 0_JCCVr09256

----------------1. DYNAMIC RAM· MSC2304YS9/KS9 •PIN ASSIGNMENTMSC2304YS9MSC2304KS9PIN No. PIN NAME PIN No. PINNAME PIN No. PIN NAME1-VCC 11 A4 21 WE2 CAS 12 A5 22 VSS3 D01 13 D04 23 D074 AO 14 A6 24 NC5 A1 15 A7 25 D086 D02 16 D05 26 097 A2 17 A8 27 RAS8 A3 18 NC 28 CAS99 VSS 19 NC 29 D910 D03 20 D06 30 VCCABSOLUTE MAXIMUM RATINGS (See Note)Rating Symbol Value UnitVoltage on any pin relative to VSS VIN, VOUT -1 to +7 VVoltage on Vee supply relative to VSS Vee -1 to +7 VOperating temperature Topr o to 70 °eStorage temperature Tstg -40 to +125 °ePower dissipation PD 9 WShort circuit output current 50 mANote: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operationshould be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.257

• DYNAMIC RAM· MSC2304YS9/KS9 .---------------RECOMMENDED OPERATING CONDITIONS (Referenced to VSS)Parameter Symbol Min. Typ. Max. UnitOperatingtemperatureSupply VoltageInput High Voltage,all inputsInput Low Voltage,all inputsVee 4.5 5.0 5.5 VVSS 0 0 0 VVIH 2.4 6.5 VVIL -1.0 0.8 Vooe to +70oeDC CHARACTERISTICS(Recommended operating conditions unless otherwise noted.)120ns MODULE 150ns MODULEParameter Symbol UnitMin. Max. Min. Max.Operating Current'Average power supply current ICC1 630 585 mA(RAS, CAS cycling; tRC = min.)Standby CurrentPower supply current(RAS = CAS =VIH)ICC2 45 45 mARefresh CurrentAverage power supply current ICC3 495 450 mA(RAS cycling, CAS = VIH; tRC =min,)Page Mode Current·Average power supply current(RAS = VIL, CAS cycling; tpc =min,)Input Leakage CurrentInput leakage current, any input(OV :::: VIN :::: 5.5V, all otherpins not under test = OV)ICC4 495 450 mAIL 1 -90 90 -90 90 /LAOutput Leakage Current(Data out is disabled, ILO -10 10 -10 10 /LAOV :::: VOUT :::: 5.5V)Output LevelsOutput high voltage VOH 2.4 2.4 V(lo~=-5mA)Ou put low voltage VOL 0.4 0.4 V(lOL=4.2mA)Note*: ICC is dependent on output loading and cycle rates. Specified values are obtained with theoutput open.258

----------------. DYNAMIC RAM· MSC2304YS9/KS9 •CAPACITANCE(Ta = 25°C, f = 1 MHz)ParameterInput Capacitance (Ao -As)------Input Capacitance (RAS, CAS, WE)Data Input/OutputCapacitance (DO)Input Capacitance (CAS9)Input Capacitance (09)Output Capacitance (09)SymbolCIN1CIN2COOCIN3CIN4COUTTyp. Max. Unit40 70 pF40 75 pF7 20 pF5 10 pF4 10 pF4 15 pFCapacitance measured with Boonton Meter.AC CHARACTERISTICSParameter Symbol UnitsRefresh period tREF msRandom read or writecycle time tRC nsPage mode cycle time tpc nsMSC2304-1 2YS/ MSC2304-15YS/KSKSMin. Max. Min. Max.4 4230 260125 145NoteAccess time from RAS tRAC nsAccess time from CAS tCAC nsOutput buffer turn-offdelay tOFF nsTransition time tT nsRAS precharge time tRP nsRAS pulse width tRAS nsRAS hold time tRSH nsCAS precharge time tcp nsCAS pulse width tCAS nsCAS hold time tCSH ns120 150 4,660 75 5,60 40 0 403 50 3 50100 100120 10,000 150 10,00060 7555 6060 10,000 75 10,000120 150259

B DYNAMIC RAM· MSC2304YS9/KS9 B---------------AC CHARACTERISTICS (CONT.)·Parameter Symbol UnitsMSC2304- MSC2304-12YS/KS 15YS/KSMin. Max. Min. Max.NoteRAS to CAS delay time tRCO ns 25 60 25 75 7CAS to RAS prechargetimetCRP ns 0 0Row Address set-up time tASR ns 0 0Row Address hold time tRAH ns 15 20Column Address set-uptimeColumn Address holdtime..column Address holdtime reference to RASRead command set-uptimetASC ns 0 0tCAH ns 30 35tAR ns 90 110tRCS ns 0 0Read command hold time tRCH ns 0 0Write command set-uptimetwcs ns 0 0Write command hold time tWCH ns 40 45Write command hold timereferenced to RASWrite command pulsewidthWrite command to RASlead timeWrite command to CASlead timetWCR ns 100 120twp ns 40 45tRWL ns 40 45tCWL ns 40 45Data-in set-up time tos ns 0 0Data-in hold time tOH ns 40 45Data-in hold timereferenced to RAStOHR ns 100 120260

---------------1. DYNAMIC RAM· MSC2304YS9/KS9 •NOTES: 11213141516171An initial pause of 1oolols is required after power-up followed by any 8 ~ cycles (Examples; RASonlyl before proper device operation is achieved.AC measurements assume tT = 5 ns.VIH (Min.) and Vil (Max.) are reference levels for measuring timing of input signals. Also, transitiontimes are measured between VIH and Vil.Assumes that tACO < tACO (max.l.If tACO is greater than the maximum recommended value shown in this table, tAAC will increase bythe amount that tACO exceeds the values shown.Assumes that tACO < tACO (max.)Measured with a load circuit equivalent to 2 TTL loads and 100pF.Operation within the tACO (max.1 limit insures that tAAC (max.) can be met. tACO (max.1 is specifiedas a reference point only; if tACO is greater than the specified tACO (max.) limit, then accesstime is controlled exclusively by tCAC.READ CYCLE TIMING~------------------tAC------------------~VIH _ ---~ f...---tAR------

• DYNAMIC RAM· MSC2304YS9/KS9 •• ---------------WRITE CYCLE TIMING(EARLY WRITE)RAS VIH -VIL -CAS VIH -VIL -tRSH___ --++==~~=;_II-tCAS------t A-+....;;,;,.~-"--.......AddressesVIH -VIL -WEVIH - /jVIL -DINVIH -VIL -DOUTVOH-VOLr------tDHR-----~OPEN~ "H", "L" = Don't CareRAS ONLY REFRESH TIMING(CAS: VIH,M& DIN: Don't care)___ VIH­RAS VIL-DOUTVOH -VOL -OPEN~"H", "L" = Don't Care262

------------------------------___ OYNAMICRAM·MSC2304YS9/KS9_PAGE MODE READ CYCLEVIAdresses V I L~"H","L"=Don't CarePAGE MODE WRITE CYCLEV I H - ",""'+'.,.,.,.,..jVIL -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~DINV IH - ,.,.,""'~J"":';""';;';";"..J "''"''-.li...;.:.--=;.;.;....J....,,,..,..-::~.,,n...r.;........;;.;.~.n'.,..,.,~77',..,..:;~VIL -~ "H", "L" = Don't Care263

• DYNAMIC RAM· MSC2304YS9/KS9 .---------------HIDDEN REFRESHAddressestRCS IDOUT~ "H", "L" = Don't CareFUNCTIONAL DESCRIPTIONAddress Inputs:A total of eighteen binary input address bitsare required to decode any 1 of 262144 storagecell locations within the MSC:!304. Nine rowaddressbits are established on the input pins(Ao - As) and latched with the Row AddressStrobe (RAS). The Nine column-address bits areestablished on the input pins and latched withthe Column Address Strobe (CAS). All input addressesmust be stable on or before the fallingedge of RAS, CAS is internally inhibited (or"gated") by RAS to permit triggering of CAS assoon as the Row Address Hold Time (tRAH) specificationhas been satisfied and the addressinputs have been changed from row-addressesto column-addresses.Write Enable:The read mode or write mode is selected withthe WE input. A logic high (1) on WE dictatesread mode; logic low (0) dictates write mode.Data input is disabled when read mode is selected.Data Input:Data is written into the MSC2304 during awrite. The last falling edge of WE or CAS is astrobe for the Data In (DIN) register. In a writecycle, if WE is brought low (write mode) beforeCAS, DIN is strobed by CAS, and the set-up andhold times are referenced to CAS.Data Output:The output buffer is three-state TTL compatiblewith a fan-out of two standard TTL loads.Data-out is the same polarity as data-in. Theoutput is in a high impedance state until CAS is264brought low. In a read cycle, the output is validafter tRAC from transition of RAS when tRCD(Max.) is satisfied, or after tCAC from transitionof CAS when the transition occurs after tRCD(Max.). Data remain valid until CAS is returned toa high level. In a write cycle the identical sequenceoccurs, but data is not valid.Page Mode:Page-mode operation permits strobing therow-address into the MSC2304 whilemaintaining RAS at a logic low (0) throughout allsuccessive memory operations in which therow-address doesn't change. Thus the powerdissipated by the negative going edge of RAS issaved. Further, access and cycle times aredecreased because the time normally requiredto strobe a new row-address is eliminated.Refresh:Refresh of the dynamic memory cells is accomplishedby performing a memory cycle ateach of the 256 row-addresses (Ao - A7) atleast every four milliseconds. During refresh,either VIL or VIH is permitted for As. RAS only refreshavoids any output during refresh becausethe output buffer is in the high impedance stateunless CAS is brought low. Strobing each of 256row-addresses with RAS will cause all bits ineach row to be refreshed. Further RAS-only refreshresults in a substantial reduction in powerdissipation.Hidden Refresh:RAS ONLY REFRESH CYCLE may take placewhile maintaining valid output data. This featureis referred to as Hidden Refresh.Hidden Refresh is performed by holding CASas VIL from a previous memory read cycle.

-----------------11. DYNAMIC RAM· MSC2304YS9/KS9 •MSC2304YS93.3888982.14'I5.08MAXL()(!);:tiIlliCJ; ~3.18y~I~r ,;lllI cn:rm:r' 'ct:rm:r203 5.592.5411 ~ 1.27±0.13Glass-Epoxy Board18pin PLCCChip Condenser1. Substrate: GLASS-EPOXY2. Through Hole: Copper PlatingFollowed by Sn/Pb Plating3. Contact Pads: Copper PlatingFollowed by Sn/Pb Platingon Copper Film (18j!mt)4. Surface Coating: Photo Film ResistTin-Lead Solder /.MSC2304KS9338 1318-L889OL()~Oc:ic:i+1L()C\Jc:i18 pin PLCCL()c:iC\JChip Condenser1. Substrate: GLASS-EPOXY2. Through Hole: Copper PlatingFollowed by Sn/Pb Plating3. Contact Pads: Copper PlatingFollowed by Sn/Pb Platingon Copper Film (18j!mt)4. Surface Coating: Photo Film Resist265

• DYNAMIC RAM· MSC2304YS9/KS9 •• ---------------MSC2304YS9/KS9 (SIP/SIM) DERATING CURVE(OC)7060I!!~Q) 50CoEQ)._-""""---.............. , ' .........AllowableNot Allowable'.. ..... ..........." '" ''''.AirFlow--- :Om/s_.-._ :1m/s------ : 3m/st-

MOSSTATICRAMS

OKI semiconductorMSM5114RS4096-BIT (1024 x 4) CMOS STATIC RAMGENERAL DESCRIPTIONThe Oki MSM5114 is a 4096-bit static Random Access Memory organized as 1024 words by 4 bits using Oki'sreliable Silicon Gate CMOS technology. It uses fully static circuitry and therefore requires no clocks or refreshingto operate. Microwatt power dissipation typical of all CMOS is exhibited in all static states. Directly TTL compatibleinputs, outputs and operation from a single +5V supply simplify system designs. Common data input/outputpins using three-state outputs are provided.The MSM5114 series is offered in an 18-pin plastic (RS suffix) package. The series is guaranteed for operation fromO°C to 70°C and over a 4V to 6V power supply range.FEATURES• Fully Static Operation• Low Power Dissipation40j.lW Max. Standby Power192 mW/MHz Max. OperatingPower• Data Retention to V CC=2V• Single 4 - 6V Power Supply• High Density 300-mil 18-Pin Package• Common I/O Capability using Three­State Outputs• Directly TTL/CMOS Compatible• Silicon Gate CMOS Technology• Interchangeable with Intel 2114LDevices5114-2 5114-3Max. A_ Time (NS)200 300Max. Op .... ting Power (MW/MHzI 192 192Max_ Standby Power (,.WI 40 40511445019240FUNCTIONAL BLOCK DIAGRAM~.f-}".'I.I~II~~J I I l~mi"---1>--1A,---{)---!ROWA, ---1>:=:1 SELECTA'---1>:=:IA.-~-1>--1MEMORY ARRAY641

------------------1. STATIC RAM ·MSM5114RS •ABSOLUTE MAXIMUM RATINGSRating Symbol Value Unit ConditionsSupply Voltage VCC -0.3 to 7.0 VInput Voltage VIN -0.3 to V CC + 0.3 V Respect to VSSData I/O Voltage VD -0.3 to VCC + 0.3 VStorage Temperature T stg -55 to 150 °cNota: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to thedevice. This is a stress rating only and functional operations of the device at these or at any other conditionabove those indicated in the operational sections of this specification is not implied. Exposure to absolutemaximum rating conditions for extended periods may affect device reliability.OPERATING CONDITIONSParameter Symbol Min. Typ. Max. Unit ConditionsSupply Voltage VCC 4 5 6 VVIH 2.4 5 VCC VI nput Signal Level 5V ±10%VIL -0.3 0 0.8 VOperating Temperature Topr 0 70 °cDC CHARACTERISTICS(Vcc = 5V ± 10%; Ta = O°C to + 70 D C, unless otherwise noted.)Parameter Symbol Min. Typ. Max. Unit ConditionsInput Load Current III -1 1 p,A VIN=OtoVCCData I/O Leakage Current ILO -1 1 p,A VI/O = 0 to VCCOutput High Voltage VOH 2.4 V lOUT = -1.0 mAOutput Low Voltage VOL 0.4 V 10UT= 1.6mAStandby Supply Current ICCS 0.2 50 p,AOperating Supply Current ICC 19 35 mAVIN = 0 or VCC,VCS =VCCVIN = 0 or VCC,tRC = 1 p,s269

• STATIC RAM ·MSM5114RS •• ------------------AC CHARACTERISTICSREAD CYCLE(Vcc ~ 5V ±10%, Ta = o°c to +70°C)ParameterSymbol5114-2 5114-3 5114Min_ Max. Min. Max. Min. Max.UnitRead Cycle TimetRC200 300 450nsAccess TimetAC200 300 450nsChip Selection to OutputValidtco200 300 450nsChip Selection to OutputActivetcx20 20 20nsOutput 3-state fromOeselectiontOTO60 SO 100nsOutput Hold from AddressChangetOHA10 10 10nsREAD CYCLEtRC/tACINPUT/OUTPUT/i---tOTOtcor---tcx-V I L\tOHA-j---'\Notes:1. A Read occurs du ring the overlap of a low CS and high WE.2. Input Pulse levels: O.SV to +2.4V3. Input Rise and Fail Time: 10 ns4. Timing Measurement Reference Levels: 1.5V5. Output Load: 1 TTL Gate and CL ~ 50 pFWRITE CYCLE(VCC ~ 5V ±10%, Ta = o°c to +70°C)5114-2 5114-3 5114ParameterSymbolMin. Max_ Min. Max. Min. Max.Write Cycle Time twc 200 300 450Write Time tw 150 190 250Write Release Time tWR 20 30 50Address Setup Time tAS 20 20 20Data Setup Time tos 120 150 200Data Hold From Write Time tOH 10 10 '10Unitnsnsnsnsnsns270

-------------------1. STATIC RAM· MSM5114RS •WRITE CYCLEtwctw---tAS--"tDs-----;r---twRtDHINPUT/OUTPUTI\-DATA IN STABLEJNotes: 1. A Write occurs during the overlap of a low CS and low WE.2. Input Pulse Levels: 0.8V to +2.4V3. Input Rise and Fall Time: 10 ns4. Timing Measurement Reference Levels: 1.5V5. two Overlap time of a low CS and low WE.6. tAS: Low WE from address or low CS from address7. tWR, tDS and tDH are defined from High CS or High WE. whichever occurs first.LOW VCC DATA RETENTION CHARACTERISTICS(T a = 0° C to + 70° C, unless otherwise noted.)Parameter Symbol Min. Typ. Max. Unit ConditionsV CC for Data Retention VCCH 2 V VIN = 0 or VCC. VCS = VCCData Retention Current ICCH 0.1 20 IJACS to Data Retention Time tsu 0 nsOperation Recovery Time tR tRC nsVCC = 2V VCS = VCCVIN = OV or VCCLOW VCC DATA RETENTION WAVEFORM~'!--~~-STANDBY MODE~~~~~-5V ~---=.V..!;C~C,--+ __ ---,4.5V -----VIH ----- ------VCCH---- - ---- - - - '-----------'VILGND-------------------- - - - - ------ - ---271

• STATIC RAM ·MSM5114RS .11-------------------CAPACITANCE(T a = 25"C, f = 1 MHzlParameterInput/Output CapacitanceInput CapacitanceSymbolCI/OCINMin.Typ. Max. Unit10 pF8 pFNote: This parameter is pariodically sampled and not 100% tested.272

OKI semiconductorMSM2128RS2 KW x 8 BIT STATIC RAMGENERAL DESCRIPTIONThe OKI MSM2128 is a 16384 bits static Random Access Memory organized as 2048 words by 8 bits usingAdvanced N-channel Silicon Gate MOS technology_ ·'t uses fully static circuitry throughout and no clocks or refreshare required. The reduced standby power dissipation is automatically performed by CS control. Single +5 V Powersupply. All inputs and outputs are directly TTL compatible. Common data I/O using three-state outputs. The 24 pinpackage is pin compatible with standard 16 K UV Erasable Programmable ROM.FEATURES• Single power supply• External clock and refresh.operation not required• Access timeMSM2128-12RSMSM2128-15RSMSM2128-20RS• Low power dissipationduring operation120ns (maxI150ns (maxI200ns (maxIMSM2128-15RS/20RS550mW (maxIMSM2128-12RS660mW (maxIduring standby 110 mW (maxI• TTL compatible I/O• Three-state I/O• Common data I/O capability• Power down mode using chip select signal• Convertibility of pins used in 16KEPROM MSM2716FUNCTIONAL BLOCK DIAGRAMA.A,A.A,PIN CONFIGURATIONA.A,.. 2(Top ViewlA, ,24 Vee 1/0 123 A, liD!A, 3 22 A9 110 .•II,• 2' mI/O~A, s 200lt IIO~A,•19 AIO I/O~A, 7 ,. cs 110,A,•17 liD. IIOK,. 110,€110)liDsVSS '2 '3 11041101 9 ,. 110,liD!,."Ao "vAIO: Address InputsI/O, 'V I/O. ; Data Input/OutputVee: Power (5V)VSS: GroundWE: Write Enablees: ehip SelectOE: Output EnableAI(>I---Vee2':: r---GNDMEMORY ARRAY~:"-RO"128ROWS2':: SELECT 16COLUMNSx8Block2':: r------- -:'-I I:r- ~ COLUMN I/O CIRCUITS:c- INPUT COLUMN SELECT ~~'- DATACONTROL:---:..'-~~~~h 1 h' n~~hn273

• STATIC RAM ·MSM2128RS .-------------------ABSOLUTE MAXIMUM RATINGSRating Symbol Value Unit ConditionsSupply Voltage Vee -0.5 to 7 VInput VoltageVIN -0.5 to 7 VOperating Temperature Topr o to 70 °cStorage Temperature T stg -55 to 150 °cPower Dissipation Po 1.0 WRespect to V ssDC AND OPERATING CHARACTERISTICS(Ta = o°c to + 70°C, VCC = 5V ±10%, unless otherwise notes.)2128·12RS2128-15/20RSParameter Symbol Unit ConditionsMin. Typ. Max. Min. Typ. Max.Input LoadCurrentOutput LeakageCurrentOperatingCurrentStandbyCurrentPeak Power-onCurrentInput VoltageOutput VoltageIII -10 10 -10 10 /LAVee = Max.VIN = GND to VeeCS = OE = VIH,ILO -10 10 -10 10 /LA Vee = Max.V out = GND to VeeICC 120 100 mAISS 15 15 mAVee = Max. CS = VILI I/O = 0 mA teye = Min.Vee = Min. to Max.CS = VIHVee = GND to Vee = Min.ISSp 20 20 mA CS = Lower of Veeor VIHVIH 2 5 6 2 5 6 VVIL -0.5 0 0.8 -0.5 0 0.8 VRespeet to VssVOH 2.4 Vee 2.4 Vee V 10H = -1.0 mA0.4VOL 0.4 V 10L = 2.1 mANotes 1. Typical limits are at Vee = 5V, Ta = 25°C, and specified loading.AC CHARACTERISTICS(T a = o°c to + 70°C, VCC = 5V ± 10%, unless otherwise noted.)AC TEST CONDITIONSParameterConditionsI nput High Level 2.0VI nput Low Level 0.8VI nput Rise and Fall Times10 nsInput and Output Timing Levels 1.5VOutput LoadCL = 100 pF, 1TTL Gate274

-------------------11. STATIC RAM ·MSM2128RS •READ CYCLE (1)ParameterSymbol2128-12RSMin. Max.2128·15RSMin. Max.2128-20RSMin. Max.UnitConditionsRead Cycle Time tRC 120150200nsAddress Access Time tAC 120150200nsOutput Enable toOutput DelaytOE 506070nsCh ip Select Access Time tco 120150200nsChip Selection toOutput in Low ZtCX(2) 101010nsChip Selection toOutput in High ZtOTD(3) 0 400 500 60nsOutput Hold fromAddress TimetOHA 101010nsChip Select toPower Up Timetpu 000nsChip Select toPower Down TimetpD 506080nsREAD CYCLE NO. 1(8)(9)I/O(out)READ CYCLE NO. 2(8)(10)I/O(out)VCCSupplyCurrentICC------+-J+---; tpuNotes: 1. ~ is high for Read Cvcle.2. Device is continuously selected. CS = VI L.3. Address valid prior to or coincident with "CS" transition low.275

• STATIC RAM ·MSM2128RS •• ------------------WRITE CYCLE (4)(5)2128·12RS 2128·15RS 2128·20RSParameter Symbol Unit ConditionsMin. Max. Min. Max. Min. Max.Write Cycle Time twc 120 150 200 nsChip Selection to Endof Writetcw 90 120 150 nsAddress Setup Time tAS 20 20 20 nsWrite Pulse Width twp SO 80 100 nsWrite Recovery Time tWR(S) 10 10 10 n.Data Valid to End of Write tOS(S) 50 70 90 nsData Hold Time tOH(S) 10 15 15 nsWrite Enabled to Outputin High ZtOTWI7l 0 40 0 50 0 SO nsOutput Active fromEnd of Whitetwx 5 5 5 nsNotes1. A read occurs during the overlap of a low CS, a low OE and a high WE.2. tcx is specified from CS or CE, whichever occurs last.3. tOTO is specified from CS or CE, wh ichever occurs first.4. A write occurs during the overlap of a low CS and a low WE.5. OE may be allowed in a Write Cycle both high and low.S. tWR, tos, and tOH are specified from CS or WE, whichever occurs first.7. tOTW is specified by the time when DATA OUT is floating, not defined by output level.WRITE CYCLE NO. 1 (11 )113)twcA."'A,.~WE"I/O(OOUT)twptosI/O(DIN)276

-------------------11. STATIC RAM ·MSM2128RS •WR ITE CYCLE NO. 2112) 113)~---------------twc---------------~t----tcw -------1Notes1. WE control mode2. CS control mode3. When 1/0 pins are Data output mode, don't force inverse signal to these pins.FUNCTION TRUTH TABLECS WE OE Mode Output PowerH X X Not Selected High Z StandbyL L X Write High Z ActiveL H L Read DOUT ActiveL H H Not Selected High Z ActiveCAPACITANCE(Ta = 25°C, f = 1 MHz)Parameter Symbol Min. Max. Unit ConditionsInput/Output Capacitance ClIO 8 pF VI/O = OVInput Capacitance CIN 6 pF VIN =OVNote: This parameter is periodically sampled and not 100% tested.277

OKI semiconductorMSM5128RS2048-WORD x 8-BIT C-MOS STATIC RAMGENERAL DESCRIPTIONThe MSM5128RS is a 2048-word by 8-bit CMOS static RAM featuring 5V power supply operation and direct TTLinput/output compatibility. Since the circuitry is completely static, external clock and refreshing operations areunnecessary, making this device very easy to use. The MSM5128RS is also a CMOS silicon gate deVice which requiresvery little power during stanciby (maximum standby current of 50ltA) when there is no chip selection. Stored data isretained if the power voltage drops to 2V, thereby enabling battery back-up.A byte system is adopted, and since there is pin compatibility with standard ultra-violet EPROMs, this device is idealfor use as a peripheral memory for microcomputers and data terminal units etc. In addition, CS and OE signalsenable OR ties with the output terminals of other chips, thereby facilitating simple memory expansion and bus linecontrol etc.FEATURES• Single 5V Supply• Battery Back-up at 2V• Operating temperature range Ta = _40°C to -+a5°C• Low Power DissipationStandby;5128-205128-12/151.0 itA MAX Ta = 25°C 0.3 itA MAX Ta = 25°C10llA MAX Ta = 60°C 1.0 IlA MAX Ta = 60°C50 itA MAX Ta = 85°COperation;200mW TYP• High Speed (Equal Access and Cycle Time)MSM5128-12/15/20; 120 ns/150 ns/200 ns MAX• Direct TTL Compatible. (Input and Output)• 3-State Output• Pin Compatible with16K EPROM (MSM2716)16K NMOS SRAM (MSM2128)FUNCTIONAL BLOCK DIAGRAMPIN CONFIGURATION(Top View)1/0, C>--

_______.,..--__________-11. STATIC RAM· MSM5128RS •TRUTH TABLEMode CS ~ O"E" I/O OperationStandby H X X High ZL H H High ZReedL H L DOUTWrite L L X DINX: H or LABSOLUTE MAXIMUM RATINGSRating Symbol Value Unit ConditionsSupply Voltage VCC -0.3 to 7.0 VInput Voltage VIN -0.3 to VCC + 0.3 VOperating Temperature Topr -40 to 85 DCStorage Temperature Tstg -55 to 150 DCRespect to GNDPower Dissipation PD 1.0 W Ta = 25'CRECOMMENDED OPERATING CONDITIONSupply VoltageParameter Symbol Min. Typ. Max. Unit ConditionsVCC 4.5 5 5.5 V 5V ± 10%VSS 0 VData Retention Voltage VCCH 2 5 5.5 VVIH 2.2 VCC + 0.3 VInput Voltage 5V ± 10%VIL -0.3 0.8 VOutput LoadCL 100 pFTTL 1279

• STATIC RAM· MSM5128RS •• ------------------_DC CHARACTERISTICSParam- MSM5128-12 MSM5128-15 MSM5128-20SymboleterMin. Typ. Max. Min. Typ. Max. Min. Typ. Max.InputLeakage III -1CurrentOutputLeakage ILO -1CurrentOutputVoltageVOH 2.4VOLTai 250 CStandbyICCS 60°CSupplyCurrent 85°COperatingSupplyCurrentICCS1 0.3ICCA4040110.40.21.016072-1-12.40.33737UnitTest Condition1 -1 1 /J.A VIN=OtoVCCCS=VIHor1 -1 1 /J.A OE = VIHVI/O = 0 to VCC2.4 V IOH =-1 mA0.4 0.4 V0.2 0.1 1.01.0 10 /J.A501 0.3 1 mA55 35 50 mA66 35 60 mAIOL =4 mA(5128-12)IOL=2.1 mA(5128-15/20)CS;; VCC - 0,2VVIN = 0 to VCCCS = VIHtcyc = Min. cycleMin.cycleTa = 0-85°CTa=-40-85° CAC CHARACTERISTICSTest ConditionParameterI nput Pulse LevelInput Aise and Fall TimesI nput and OutputTiming Aeference LevelOutput Load10 ns1.5VConditions--------------~--------------------------------------CL =100 pF, 1 TTL GateREAD CYCLE(Vcc = 5V ± 10%, Ta = -4o"C to +85° C)MSM5128-12 MSM5128-15 MSM5128-20Parameter Symbol UnitMin. Max. Min. Max. Min. Max.Aead Cycle Time tAC 120 150 200 nsAdd ress Access Tim e tAC 120 150 200 nsChip Select Access Time tco 120 150 200 nsOutput Enable to Output Valid tOE 80 100 120 nsChip Selection to Output Active tcx 10 15 20 nsOutput Hold Time FromAddress Change tOHA 10 15 20nsOutput 3-state from Deselection tOTD 0 50 0 50 0 60 ns280

-------------------. STATIC RAM 'MSM5128RS •READ CYCLENote.: 1. A Read occurs during the overlap of a low

• STATIC RAM ·MSM5128RS •• ------------------WRITE CYCLE>~-----LOW VCC DATA RETENTION CHARACTERISTICS(T a = _40 0 C to +8S o C, un less otherwise noted)5128-12/15 5128-20Parameter Symbol Unit ConditionsMIN MAX MIN MAXV CC for Data Retention VCCH 2 2 V V,N = OV to VCC, CS = VCC25°C 0.2 O.SData Retention Current ICCH 60°C 1.0 p.A8SoC 20CS to Data Retention Time tsu 0 0 nsOperation Recovery Time tR tRC tRC nsVCC = 2V CS = VCCV,N = OV to VCC--!-----STANDBy MODE --~~-­SV _---'-V..::C"'C'---+-__ ---.4.SV -----VCCH---­CSVIL-"-'-~GND-------------------- - - - ------- - ---CAPACITANCE(Ta = 2SoC, f = 1 MHz)ParameterSymbolMin.Typ, Max. UnitI nput/Output CapacitanceInput CapacitanceCliOC,N8 pF6 pFNote: This parameter is periodically sampled and not 100% tested.282

OKI semiconductorMSM5128 - 20GSK2048-WORD x 8-BIT C-MOS STATIC RAM (E3-S-013-32)GENERAL DESCRIPTIONThe MSM5128GS is a 2048-word by 8-pit CMOS static RAM featuring 5V power supply operation and direct TTLinput/output compatibility. Since the circuitry is completely static, external clock and refreshing operations areunnecessary, making this device very easy to use. The MSM5128GS is also a CMOS silicon gate device which requiresvery little power during standby (maximum standby current of 50/JA) when there is no chip selection. Stored data isretained if the power voltage drops to 2V, thereby enabling battery back-up.A byte system is adopted, and since there is pin compatibility with standard ultra-violet EPROMs, this device is idealfor use as a peripheral memory for microcomputers and data terminal units etc. In addition, CS and OE signalsenable OR ties with the output terminals of other chips, thereby facilitating simple memory expansion and bus linecontrol etc.FEATURES• Single 5V Supply• Battery Back-up at 2V• Operating temperature range Ta = _40°C to +85°C• Low Power DissipationStandby; 1.0 /JA MAX Ta = 25°C10 IlA MAX Ta = 60°C50 IlA MAX Ta = 85°COperation; 200 mW TYP• High Speed (Equal Access and Cycle Time)MSM5128-20; 200 ns MAX• Direct TTL Compatible. (Input and Output).3-State Output• 24 Pin Flat PKGPIN CONFIGURATION(Top View)FUNCTIONAL BLOCK DIAGRAMA. 24A. 23A. 22A, 21A, 20A, 19A, 18A" 17110 1 161/0, 10 15110.1 11 14VSS 12 13VeeA,A,WE01'A,"cslIDs1/0.1/0,1/0,1/04AoAs 0---------A60----A, D----Pd ROWA,A,A"1/01l/Ol1/0) o-M----t;,::l-jINPUT1/04 o-ttI

• STATIC RAM· MSM51 28-20GSK .-----------------TRUTH TABLEMode es WE OE I/O OperationStandby H X X High ZL H H High ZReadL H L DOUTWrite L L X DINX: H or LABSOLUTE MAXIMUM RATINGSRating Symbol Value Unit ConditionsSupply Voltage Vce -0.3 to 7.0 VI nput Voltage VIN -0.3 to VCC + 0.3 VRespect to GN DOperating Temperature Topr -40 to 85 °cStorage Temperature Tstg -55 to 150 °cPower Dissipation PD 1.0 W Ta = 25°CRECOMMENDED OPERATING CONDITIONSupply VoltageParameter Symbol Min. Typ. Max. Unit ConditionsVec 4.5 5 5.5 V 5V ± 10%VSS 0Data Retention Voltage VeCH 2 5 5.5 VVIH 2.2 Vee + 0.3 VI nput Voltage 5V ± 10%VIL -0.3 0.8 VOutput LoadeL 100 pFTTL 1V284

-----------------. STATIC RAM· MSM5128-20GSK •DC CHARACTERISTICS(Vee = 5V ± 10%, Ta = _40°C to +85° C)ParameterSymbolMin_MSM5128-20Typ_ Max_UnitTest ConditionInput LeakageCurrentIII-11IJ.AVIN = 0 to VCCOutput LeakageCurrentILO-11IJ.ACS = VIH orOE = VIHVI/O = 0 to VCCVOH2.4VIOH = -1 rnAOutput VoltageVOL0.4VIOL = 2.1 rnATa~Standby Supply ICCS 60°CCurrent85°COperatingSupply CurrentICCSlICCA0.1 1.010500.3 135 5035 60IJ.ArnACS;;; VCC - 0.2VVIN = 0 to VCCCS = VIHtcyC = Min. cyclernA Min. l Ta=0-85°CrnA cycle I Ta = -40 - 85°CAC CHARACTERISTICSTest ConditionParameterInput Pulse LevelInput Rise and Fall TimesI nput and OutputTiming Reference LevelOutput LoadConditions10 ns1.5VCL =100 pF. 1 TTL GateREAD CYCLE(Vee = 5V ± 10%, Ta = -4o"C to +85° C)ParameterRead Cycle TimeAdd ress Access Ti meChip Select Access TimeOutput Enable to Output Val idChip Selection to Output ActiveOutput Hold Time from Address ChangeOutput 3-state from DeselectionSymboltRCtACtcotOEtcxtOHAtOTOMSM5128-20UnitMin. Max.200 ns200 ns200 ns120 ns20 ns20 ns0 60 ns285

• STATIC RAM· MSM5128-20GSK .1-----------------READ CYCLENotes:1. A Read occurs during the overlap of a low CS, a low OE and a high WE.2. tex is specified from CS or OE, whichever occurs last.3. tOTD is specified from CS or OE, whichever occurs first.4. tOHA and tOTD are specified by the time when DATA OUT is floating.WRITE CYCLE(Vcc= 5V ± 10%, Ta= -40°C to +S5°C)MSM512S:20ParameterSymbolMin.Max.Writ!' Cycle Time twc 200Address to Write Setup Time tAS 20Write Time tw 120Write Recovery Time tWR 20Data Setup Time tDS SOData Hold from Write Time tDH 10Output 3·State from Write tOTW 60UnitnsnsnsnsnsnsnsNotes:1. A Write Cycle occurs during the overlap of a low CS and a low WE.2. OE may be both high and low in a Write Cycle.3. tAS is specified fromCS or WE, whichever occurs last.4. tw is an overlap time of a low CS and a low WE.5. twR, tDS and tDH are specified from CS or WE, whichever occurs first.6. tOTW is specified by the time when DATA OUT is floating, not defined by output level.7. When I/O pins are Data output mode, don't force inverse signal to those pins.286

-----------------. STATIC RAM· MSM5128-20GSK •WRITE CYCLEtwc=> V ) Vf'..f'..twf--tAS--""V/f--twR-"i'\ /VtOTWtDS_ f--tDH1/0______""-i--""-;~~ 8ATA IN STABLi >>--~~~-LOW VCC DATA RETENTION CHARACTERISTICS(Ta = -40°C to +85°C, unless otherwise noted)Parameter Symbol Min. Typ. Max. Unit ConditionsV CC for Data Retention VCCH 2 V VIN = OV to VCC, CS = VCCData Retention Current ICCH 0.05 20 /JACS to Data Retention Time tsu 0 nsOperation Recovery Time tR tRC nsVCC = 2V CS = VCCVIN = OV to VCC5V __ V-'--"'C"'-C_-+-__ -,4.5V - - ------ST ANDBY MODE ---+---VCCH ----VILGND-------------------- - - - - ------ - ---287

• STATIC RAM· MSM5128-20GSK .-----------------CAPACITANCE(Ta = 25°C, f = 1 MHz)ParameterI nput/Output CapacitanceInput CapacitanceSymbolCI/OCINMin.Typ. Max. Unit8 pF6 pFNote: This parameter is periodically sampled and not 100% tested.288

OKI semiconductorMSM5126RS2048-WORD x 8-BIT C-MOS STATIC RAM (E3-S-014-321GENERAL DESCRIPTIONThe MSM5126RS is a 2048-word by 8-bit CMOS static RAM featuring 5V power supply operation and direct TTLinput/output compatibility. Since the circuitry is completely static, external clock and refreshing operations areunnecessary, making this device very easy to use. The MSM5126RS is also a CMOS silicon gate device which requiresvery little power during standby (maximum standby current of 30"AI when there is no chip selection. Stored data isretained if the power voltage drops to 2V, thereby enabling battery back-up.A byte system is adopted, and since there is pin compatibility with standard ultra-violet EPROMs, this device is idealfor use as a peripheral memory for microcomputers and data terminal units etc. In addition, CS and OE signalsenable OR ties with the output terminals of other chips, thereby facilitating simple memory expansion and bus linecontrol etc.FEATURES• Single 5V Supply• Battery Back-up at 2V• Operating temperature range Ta = _30°C to +85°C• Low Power DissipationStandby; 1.0 "A MAX T a = 25° C5.0 "A MAX T a = 60°C30 "A MAX Ta = 85°COperation; 200 mW TYP• High Speed (Equal Access and Cycle TimelMSM5126-20/25; 200 ns/250 ns MAX• Direct TTL Compatible. (Input and Output!• 3-State Output• Pin Compatible with16K EPROM (MSM2716116K NMOS SRAM (MSM21281FUNCTIONAL BLOCK DIAGRAMPIN CONFIGURATION(Top ViewlAoo-----~=1---,A,c>-­A,o----­A, o-------t/l:::lA, C>------D

• STATIC RAM ·MSM5126RS •• ------------------TRUTH TABLEMode CS WE" OE I/O OperationStandby H X X High ZL H H High ZReadL H L DOUTWrite L L X DINX: H or LABSOLUTE MAXIMUM RATINGSRating Symbol Value Unit ConditionsSupply Voltage VCC -0.3 to 7.0 VInput Voltage VIN -0.3 to VCC + 0.3VRespect to GNDOperating Temperature Topr -30 to 85 °cStorage Temperature Tstg -55 to 150 °cPower Dissipation PD 1.0 W Ta = 25°CRECOMMENDED OPERATING CONDITIONSupply VoltageParameter Symbol Min. Typ. Max. Unit ConditionsVCC 4.5 5 5.5 V 5V ± 10%VSS 0Data Retention Voltage VCCH 2 5 5.5 VVIH 2.2 VCC + 0.3 VInput Voltage 5V ±10%VIL -0.3 0.8 VOutput LoadCL 100 pFTTL 1V290

-------------------. STATIC RAM 'MSM5126RS •DC CHARACTERISTICS(VCl; = sv ± 10%, Ta = _30°C to +8S0C)Parameter Symbol Test ConditionInputMSM512S-20/25Min. Typ. Max.Leakage ILl VIN =Oto VCC -1 1CurrentOutputCS=VIHorLeakage ILO OE= VIH -5 5CurrentVI/O=OtoVcCOutput VOH IOH=-l mA 2.4Voltage VOL IOL =2.0mA 0.4CS ~ VCC - 0.5VTa c 25°C 0.05 1.0Standby ICCS VCC = 2V to 5.5V Ta" SO°C 5.0SupplyVI=OtoVCCTa = 85°C 30CurrentCS = VIHICCS,tCYC = Min. cycle1 3OperatingSupplyCurrentICCACS = OV, VIN = VIH/VIL lOUT = 0 mA 40 70CS = OV, VIN = VCC/GNO, lOUT = 0 mA 3055Unitp-Ap-AVVp-AmAmAmAAC CHARACTERISTICSTest ConditionParameterI nput Pulse LevelInput Rise and Fall TimesI nput and OutputTiming Reference LevelOutput LoadConditionsVIH = 2.4V, VIL = o.sv10 ns2.2V 0.8VCL =100 pF. 1 TTL GateREAD CYCLE(Vcc= 5V ± 10%, Ta= _30°C to +85°C)ParameterSymbolMSM512S-20 MSM512S-25Min. Max. Min. Max.UnitRead Cycle TimetRC200 250nsAddress Access TimetAC200 250nsChip Select Access Timetco200 250nsOutput Enable to Output ValidtOE100 100nsChip Selection to Output Activetcx10 10nsOutput Hold Time FromAddress ChangetOHA10 10nsOutput 3-state from OeselectiontOTO0 80 0 80ns291

• STATIC RAM· MSM5126RS •• -------------------READ CYCLE~------------tRC--------------~A.'VA,.I/ONotes: 1. A Read occurs during the overlap of a low -es, a low OE and a high WE.2. tcx is specified from CS or OE, whichever occurs last.3. tOTO is specified from CS or OE, whichever occurs first.4. tOHA and tOTO are specified by the time when DATA OUT is floating.WRITE CYCLE(Vcc = 5V ± 10%, Ta = _30°C to +85°C)ParameterSymbolMSM5126-20 MSM5126-25Min. Max. Min. Max.Write Cycle Time twc 200 250Address to Write Setup Ti me tAS. 0 0Write Time tw 160 200Write Recovery Time tWR 10 10Data Setup Time tDS 80 120Data Hold from Write Time tDH 0 0Output 3-State from Write tOTW 80 80UnitnsnsnsnsnsnsnsNotes:1. A Write Cycle occurs during the overlap of a low CS and a low WE.2. OE may be both high and low in a Write Cycle.3. tAS is specified from CS or WE, whichever occurs last.4. tw is an overlap time of a low CS and a low WE.5. twR, tDS and tDH are specified from CS or WE, whichever occurs first.6_ tOTW is specified by the time when DATA OUT is floating, not defined by output level.7. When I/O pins are Data output mode, don't force inverse signal to those pins.292

-------------------. STATIC RAM ·MSM5126RS •WRITE CYCLEI/OLOW VCC DATA RETENTION CHARACTERISTICS(Ta = -30 0 e to +85°C. unless otherwise noted)Parameter Symbol Min. Typ. Max. Unit ConditionsV CC for Data Retention VCCH 2 V VIN = OV to VCC. CS = VCCData Retention Current ICCH 0.05 30 p.ACS to Data Retention Time tsu a nsOperation Recovery Time tR tRC nsVCC = 2V to 5.5V. VI = OV to VCCCS? = VCC - 0.5V-1----STANDBY MODE ----+-~- tR5V __ V.:;.C.:;.C_+-__ ---,4.5V -----VCCH ---­VILCS- - - - - - - - '-------------'GND--------------- - ---- - - - - ------ - ---CAPACITANCE(Ta = 25°C. f = 1 MHz)ParameterSymbolMin.Typ. Max. UnitInput/Output CapacitanceInput CapacitanceCliOelN5 10 pF5 10 pFNote: This parameter is periodically sampled and not 100% tested.293

OKI semiconductorMSM5165RS/JS8,192-WORD x 8-BIT CMOS STATIC RAM (E3-S-017-321GENERAL DESCRIPTIONThe MSM5165RS/JS is a 8192-word by 8-bit CMOS static RAM featuring 5V power supply operation and direct TTLinput/output compatibility_ Since the circuitry is completely static, external clock and r.efreshing operations areunnecessary, making this device very easy to use. The MSM5165RS/JS is also a CMOS silicon gate device whichrequires very low power during standby (standby current of lmA) when there is no chip selection.A byte system is adopted, and since there is pin compatibility with standard ultra-violet EPROMs, this device is idealfor use as a peripheral memory for microcomputers and data term inal units etc. In addition, CE, CE, and OE signalsenable OR ties with the output terminals of other chips, thereby facilitating simple memory expansion and bus linecontrol etc.FEATURES• Single 5V Supply• etc - 70°C• Low Power DissipationStandby; 5.5 mW MAXOperation; 248 mW MAX• High Speed (Equal Access and Cycle Time)120 - 200 ns MAX• Direct TTL Compatible. (Input and Output).3-State Output• Pin Compatible with64K EPROM (MSM2764).28-pin DIP PKG• 32-pin PLCCPIN CONFIGURATION(Top View)

------------------. STATIC RAM· MSM5165RS/JS •FUNCTIONAL BLOCK DIAGRAMA,o-----~=f--~A. o-----Qc::1A, 0-----"'.--1A, ROWA. o-----Qc:::l:A •• o----Qc:::lAllo----QOAll o-----~=t __ ---1~vcc~Vss1/0. O-..--~-;1/0, o-~-~::±11/0, INPUTI/O.DATA1/0, CON-I/O.TROL1/0, o-tt-t1fffl-l:l-:±-11/0, o-+++t+H~=t-L_JCE,eelWE~ ~==3i~----------------------------~295

• STATIC RAM· MSM5165RS/ JS •• ------------------TRUTH TABLEMode CE, CE, WE OE I/O Ope rat ionStandbyH X X XX L X XHigh ZL H H H High ZReadL H H L DOUTWreite L H L X DINX: H or LABSOLUTE MAXIMUM RATINGSRating Symbol Value Unit ConditionsSupply Voltage VCC -0.3 to 7.0 VI nput Voltage VIN -0.3 to VCC + 0.3VRespect to GNDOperating Temperature Topr o to 70 °cStorage Temperature Tstg -55 to 150 °cPower Dissipation Po 1.0 W Ta ~ 25°CRECOMMENDED OPERATING CONDITIONSupply VoltageParameter Symbol Min. Typ. Max. Unit ConditionsVCC 4.5 5 5.5 V 5V ± 10%VSS 0 VVIHI nput Voltage2.2 VCC + 0.3 V5V ± 10%VIL -0.3 0.8 VOutput LoadCL 100 pFTTL 1296

------------------. STATIC RAM· MSM5165RS/JS •DC CHARACTERISTICSParamter SymbolMin.InputLeakage III -1CurrentOutputLeakage ILO -1CurrentOutput VOH 2.4VoltageVOLMSM5165Typ.Max.UnitTest Condition1 IlA VIN = Oto VCCCE I = V I H or CE., = V I L or1 IlA OE = VIHVI/O = 0 to VCCV IOH = -1 mA0.4 V IOL = 2.1 mACE, ~ VCC - 0.2V, CE, ~ VCC - 0.2VStandbySupplyCurrentOperatingSupplyCurrentICCSICCS1ICCA0.021 mA VIN = 0 to VCC3 mACDCE , ;'; 0.2VVIN = 0 to VCCCE, = VIH, CE , = VILtcyc = Min, cycleTCYC = Min, cyclemA15 TCYC=1IlsAC CHARACTERISTICSTest ConditionParameterInput Pulse LevelInput Rise and Fall TimesInput and OutputTiming Reference LevelOutput Load5165·12 55 mA 5165·15 50 mA 5165·20 45 mAConditions10 ns1.5VCL =100 pF, 1 TTL GateREAD CYCLE(Vcc = 5V ± 10%, Ta = OCC to 70 C C)ParameterRead Cycle TimeAddress Access TimeChip Enable Access TimeOutput Enable to Output ValidChip Selection to Output ActiveOutput Hold Time FromAddress ChangeOutput Enable to Output ActiveOutput 3·state from Output DisableOutput 3·state from Chip DeselectionSymboltRCtACtcotOEtcxtOHAtoxtOTOtCTDMSM5165·12 MSM5165·15 MSM5165·20UnitMin. Max. Min. Max. Min. Max.120 150 200 ns120 150 200 ns120 150 200 ns60 70 90 ns10 1Q 10 ns10 15 20 ns5 5 5 ns0 40 0 50 0 60 ns0 60 0 70 0 80 ns297

• STATIC RAM ·MSM5165RS/JS •• -----------------READ CYCLE~-----------tRC----------~1/0 --------....;::;.:..:.....*""~Notas:1. A Read occurs during the overlap of a low CE I , a high CE "a low OE and a high WE.2. tcx is specified from CE I' CE, or OE, whichever occurs last.3. tOTO is specified from CE I , CE , or OE, whichever occurs first.4. tOHA and tOTO are specified by the time when DATA OUT is floating.WRITE CYCLE(Vcc = 5V ± 10%, Ta = O°C to +70°C)MSM5165-12 MSM5165-15 MSM5165-20ItemSymbolMin. Max. Min. Max. Min. Max.Write Cycle Time twc 120 150 200Address to Write Setup Time tAS 0 0 0Write Time tw 70 90 120Write Recovery Time tWR 15 15 15Data Setup Time tDS 50 60 80Data Hold from Write Time tDH 0 0 0Output 3-State from Write tOTW 0 40 0 50 0 60.Chip Selection to End of Write tcw 100 120 150Address Valid to End of Write tAW 100 120 150Output Active from End of Write twx 5 5 5UnitnsnsnsnsnsnsnsnsnsnsNotes: 1. A Write Cycle occurs during the overlap of a low CE I , a high CE, and a low WE.2. OE may be both high and low in a Write Cycle.3. tAS is specified from CE I' CE, or WE, whichever occurs last.4. tw is an overlap time of a low CE I , a high CE , and a low WE.5. twR, tDS and tDH are specified from CE I , CE. or WE, whichever occurs first.6.7.tOTW is specified by the time when DATA OUT is floating, not defined by output level.When 1/0 pins are Data output mode, don't force inverse signal to those pins.298

-----------------11. STATIC RAM· MSM5165RS/JS •WRITE CYCLE~------------~C------------~CE,I/O (DIN) --------+-----1(CAPACIT ANCE(Ta = 2SoC, f = 1 MHz)ParameterSymbolMin.Typ. Max. UnitInput/Output CapacitanceInput CapacitanceCliOCIN8 pF6 pFNote: This parameter is periodically sampled and not 100% tested.299

OKI semiconductorMSM5165LRS IJS8,192-WORD x 8-BIT CMOS STATIC RAM (E3-S-017-321GENERAL DESCRIPTIONThe MSM5165LRS/JS is a 8192-word by 8-bit CMOS static RAM featuring 5V power supply operation and direct TTLinput/output compatibility. Since the circuitry is completely static, external clock and refreshing operations areunnecessary, making this device very easy to use. The MSM5165LRS/JS is also a CMOS silicon gate device whichrequires very low power during standby (standby current of 100/tA) when there is no chip selection.A byte system is adopted, and since there is pin compatibility with standard ultra-violet EPROMs, this device is idealfor use as a peripheral memory for microcomputers and data terminal units etc. In addition, CE, CE, and OE signalsenable OR ties with the output terminals of other chips, thereby facilitating simple memory expansion and bus linecontrol etc.FEATURES• Single 5V Supply• rt'C - 7rt'C• Low Power DissipationStandby; 0.55 mW MAXOperation; 248 mW MAX• High Speed (Equal Access and Cycle Time)120 - 200 ns MAX• Direct TTL Compatible. (Input and Output)• 3-5tate Outpu t• Pin Compatible with64K EPROM (MSM2764).28-pin DIP PKG.32-pin PLCCPIN CONFIGURATION(TOP VIEWIcf

-----------------1. STATIC RAM· MSM5165LRS/ JS •FUNCTIONAL BLOCK DIAGRAMA,o-----~=f--~A, 0--------Qc:::::JA, 0--------".--1As 0-----­A, o------l:;id:A 10 o--------QOAu o--------QOAI, o------i?;:=t.. __ ~1/0 1 ()---+1I/O, o-+t+~---I>+1I/O,o-+t+tff----I>+1I/O, o-++tItt1--tt::f1I/O, o-+t+fttt~---HCE,CE,WE~ ~==5i~------------------------------~301

• STATIC RAM· MSM5165LRS/JS •• ----------------TRUTH TABLEMode CE, CE, WE OE I/O Ope rat ionStandbyH X X XX L X XHigh ZL H H H High ZReadL H H L DOUTWreite L H L X DINX: H or LABSOLUTE MAXIMUM RATINGSRating Symbol Value Unit ConditionsSupply Voltage VCC -0.3 to 7.0 VI nput Voltage VIN -0.3 to VCC + 0.3 VRespect to GNDOperating Temperature Topr o to 70 °cStorage Temperature T stg -55 to 150 °cPower Dissipation Po 1.0 W Ta = 25°CRECOMMENDED OPERATING CONDITIONSupply VoltageParameter Symbol Min. Typ. Max. Unit ConditionsVCC 4.5. 5 5.5 V 5V ± 10%VSS0 VData Retention Voltage VCCH 2 5 5.5 VVIHInput Voltage2.2 VCC + 0.3 V5V ± 10%VIL -0.3 0.8 VOutput LoadCL 100 pFTTL 1302

-----------------1. STATIC RAM· MSM5165LRS/ JS •DC CHARACTERISTICSParamter SymbolMin.InputLeakage III -1CurrentOutputLeakage ILO -1CurrentOutput VOH 2.4VoltageVOLMSM5165LTyp.UnitTest ConditionMax.1 /lA VIN=OtoVCCCEI = VIH or CE, = VIL or1 /lA OE = VIHVI/a = 0 to VCCV IOH = -1 mA0.4 V IOL = 2.1 mACEI ~ VCC - 0.2V, CE, ~ Vec - 0.2V orIces2100 /lAVIN = 0 to VCCStandbyCE, ~ 0.2VSupplyCurrentOperatingSupplyCurrentIceSlICCA3 mACDVIN = 0 to VCCCEI = VIH, CE, = VILtcyc = Min, cycleT CYC = Min, cyclemA15 TCYC = 1 /lSAC CHARACTERISTICSTest ConditionParameterI nput Pulse LevelInput Rise and Fall TimesInput and OutputTiming Reference LevelOutput LoadConditions10 ns1.5VCL=100pF,1 TTL GateREAD CYCLE(Vee = 5V ± 10%, Ta = O°C to 70°C)ParameterRead Cycle TimeAddress Access TimeCh ip Enable Access TimeOutput Enable to Output ValidChip Selection to Output ActiveOutput Hold Time FromAddress ChangeOutput Enable to Output ActiveOutput 3-state from Output DisableOutput 3-state from Chip DeselectionSymboltRCtACtcotOEtcxtOHAtoxtOTDtCTDMSM5165-12 MSM5165-15 MSM5165-20UnitMin. Max. Min. Max. Min. Max.120 150 200 ns120 150 200 ns120 150 200 ns60 70 90 ns10 10 10 ns10 15 20 ns5 5 5 ns0 40 0 50 0 60 ns0 60 0 70 0 80 ns303

• STATIC RAM· MSM5165LRS/JS •• -----------------READ CYCLE~-----------tRC----------~I/O --------=..:..:.....*«Notes:1. A Read occurs during the overlap of a low CE l' a high CE" a low OE and a high WE.2. tcx is specified from CE l' CE, or OE, whichever occurs last.3. tOTD is specified from CE I' CE, or OE, whichever occurs first.4. tOHA and tOTD are specified by the time when DATA OUT is floating.WRITE CYCLE(Vcc = 5V ± 10%, Ta = O°C to +70°C)MSM5165L-12 MSM5165L-15 MSM5165L-20ItemSymbolMin. Max. Min. Max. Min. Max.Write Cycle Time !WC 120 150 200Address to Write Setup Time tAS 0 0 0Write Time tw 70 90 120Write Recovery Time tWR 15 15 15Data Setup Time tDS 50 60 80Data Hold from Write Time tDH 0 0 0Output 3-State from Write tOTW 0 40 0 50 0 60Chip Selection to End of Write tcw 100 120 150Address Val id to End of Write tAW 100 120 150Output Active from End of Write twx 5 5 5UnitnsnsnsnsnsnsnsnsnsnsNotes: 1. A Write Cycle occurs during the overlap of a low CE I , a high CE, and a low WE.2. OE may be both high and low in a Write Cycle.3. tAS is specified from CE I' CE, or WE, whichever occurs last.4. tw is an overlap time of a low CE I , a high CE, and a low WE.5. tWR, tDS and tDH are specified from CE I , CE, or WE, whichever occurs first.6.7.tOTW is specified by the time when DATA OUT is floating, not defined by output level.When I/O pins are Data output mode, don't force inverse signal to those pins.304

-----------------... STATIC RAM ·MSM5165LRS/JS •WRITE CYCLE~I~~-------------~C--------------~~-----tw------~CE I~--+---+----tAW--------~I+~~--+-----tcw------_~!I/O (DIN) -------1-----1(I/O (DOUT)------_./LOW VCC DATA RETENTION CHARACTERISTICS(Ta = O°C to +70°C, unless otherwise noted)Parameter Symbol Min. Typ. Max. Unit ConditionsVCC for Data Retention VCCH 2 VCEI~ VCC -O.2V, CE,~ VCC-O.2VCE, .s O.2VVCC = 3V, CE I ~ VCC - O.2V,Data Retention Current ICCH 1 50 JJ.A CE,~ VCC - 0.2VVCC = 3V, CE,.s0.2VCS to Data Retention Time tsu 0 nsOperation Recovery Time tR tRC ns305

• STATIC RAM· MSM5165LRS/JS •• ---------------_CE ICONTROLSTANDBY MODECE IovCE , ::::' VCC - 0.2VCE, CONTROL4.5VCE,VCCHVILOVCAPACITANCEna ~ 25°C. f ~ 1 MHz)ParameterSymbolMin.Typ. Max. UnitInput/Output CapacitanceInput CapacitanceCI/OCIN8 pF6 pFNote: This parameter is periodically sampled and not 100% tested.306

o __ K__ I __MSM5188USse_rn_IC_O_nc:I_U_c_._or _____ ~16,384-WORD x 4-BIT HIGH SPEED STATIC CMOS RAMGENERAL DESCRIPTIONThe MSM5188 is a static CMOS RAM organized as 16384 words by 4 bits. It features 5V singlepower supply operation and direct TTL input/output compatibility. Since the circuitry is completelystatic, external clock and refreshing operations are unnecessary which makes this device very easyto use.The MSM5188 is offered in a 22-pin slim package.FEATURES• Single 5V supply (±1 0%)• Access time• Completely static operation45/55/70 ns MAX• Operating temperature range Ta = 0 to 70°C • Direct TTL compatible (Input and output)• Low power dissipation• 3-State outputStandby. . . . . . . . . . . . . . . . . . 11 mW MAX • 22 pin DIP PKG (300 mil width)Operation ................ 605 mW MAXFUNCTIONAL BLOCK DIAGRAMPIN CONFIGURATIONA,A,0---A, I--~A·MEMORY ARRAYA, "

_STATIC RAM ·MSM5188US _.._------------------ELECTRICAL CHARACTERISTICSABSOLUTE MAXIMUM RATINGSRatingSymbolConditionValueUnitSupply VoltageVCCTa = 25DC Respect to VSSInput VoltageVINPower Dissipation PD Ta =25DCOperating Temperature Topr -Storage Temperature Tstg --0.3 to 7.0-0.3 to 7.01.0Oto +70-55 to +150VVWDCDCRECOMMENDED OPERATING CONDITIONSParameter Symbol Conditions Min.Typ.Max.UnitSupply Voltage VCC - 4.55.0 5.5V"H" Input Voltage VIH 2.2VCC =5V ± 10%"L" Input Voltage VIL -0.3- VCC +0.3- 0.8VV-Output LoadCL - -N TTL Load -- 30- 1pF• When pulse width is equal to or smaller than 20 ns, VIH max = VCC + 1.OV, VIL min = -1.OV.DC CHARACTERISTICS(VCC = 5V±1 0%, Ta = ODC to 70DC)Parameter Symbol Conditions Min. Typ. Max.Input Leakage Current III VI =OtoVCC -1 1Unit/LAOutput Leakage CurrentILOCS=VIHVI/O =OtoVCC-1 1/LA"H" Output Voltage VOH IOH=-4mA 2.4"L" Output Voltage VOL IOL =8 mA 0.4CS ~ VCC - 0.2VICCS VIN ~0.2VOR 2Standby Supply Current VIN ~ VCC - 0.2VVVmAICCS1CS =VIHTCYC = min cycle18mAOperating Supply Current ICCA Min cycle 110mA308

--------------------11. STATIC RAM· MSM5188US •CAPACITANCE(Ta = 25°C, f = 1 MHz)Parameter Symbol Condition Min. Max. UnitInput Capacitance CI VI =OV 6 pF1/0 Capacitance CliO VI/O =OV 8 pFAC CHARACTERISTICS TEST CONDITIONSParameterConditionsInput Pulse LevelInput Rise and Fall TimesVIH = 3.0V, VIL = OV5 nsInput/Output Timing Reference Level 1.5VOutput LoadCL = 30 pF, 1 TTL GATEREAD CYCLE(VCC = 5V± 10%, Ta = O°C to 70°C)5188-45 5188-55 5188-70Parameter Symbol UnitMin. Max. Min. Max. Min. Max.Read Cycle Time TRC 45 55 70 nsAddress Access Time TAC 45 55 70 nsChip Select Access Time TCO 45 55 70 nsChip Selection to Output Active TCX 5 5 5 nsOutput Hold Time fromAddress ChangeOutput 3-state fromDeselectionChip Selection to PowerupTimeChip Deselection to PowerDownTimeTOHA 5 5 5 nsTOTO 0 25 0 30 0 30 nsTpU 0 0 0 nsTpD 0 45 0 55 0 70 nsNotes: 1. Read Condition: During the overlap of a low CS and a high WE.2. TCX and TOTD are measured ±200 mV from steady state voltage with specified loadingin Figure 2.309

.STATICRAM·MSM5188US.--------------------------------------5VDOUT------

___________________ • STATIC RAM· MSM5188US •READ CYCLE TIMING 2-----.\:lCO,

OKI semiconductorMSM51257RS/JS32,768-WORD x 8-BIT CMOS STATIC RAMGENERAL DESCRIPTIONThe MSM51257 RS/JS is a 327G8-word by 8-bit CMOS static RAM featuring 5V power supply operation and directTTL input/output compatibility. Since the circuitry is completely static, external clock and refreshing operationsare unnecessary, making this device very easy to use. The MSM51257RS/JS is also a CMOS silicon gate devicewhich requires very low power during standby (standby current of 1 mAl when there is no chip selection.CS and OE signals enable OR ties with the output terminals of other chips, thereby facilitating simple memory expansionand bus line control etc.FEATURES• Single 5V Supply• O"c - 70°C• Low Power DissipationStandby; 5.5 mW MAXOperation; 385mW MAX• High Speed (Equal Access and Cycle Time)85-120 ns MAX• Direct TTL Compatible. (Input and Output)• 3-State Output• 28-pin DIP PKG.32-pin PLCCPIN CONFIGURATIONDA6A,.{ .j(TOP VIEW)J u Z ~ I~ .jPIN CONFIGURATIONA,A,Ao -- A14 Address) NPUTSliD, - liD, ; Data Input/OutputCSChip SelectWE: Write EnableDE i Output EnableVcc, VSS ; Supply VoltageA,A,A,A,g g'" u z>g g gA"Ao-AI4 : Address INPUTSNC 1/0]-1108 : Data INPUT IOUTPUTOE CS : Chip SelectWE ; Write EnableA" 01' : OUTPUT EnableCS Vee, Vss : Supply Voltage1/0,1/07312

-----------------. STATIC RAM' MSM51257RS/JS •FUNCTIONAL BLOCK DIAGRAM~vccE-------O Vsscs~WE~ ~~3{~----------------------------~313

• STATIC RAM· MSM51257RS/JS •• ----------------TRUTH TABLEMode CS WE OE 1/0 OperationStandby H X X High ZL H H High Z·ReadL H L DOUTWreite L L X DINX: H or LABSOLUTE MAXIMUM RATINGSRating Symbol Value Unit ConditionsSupply Voltage VCC -0.3 to 7.0 VI nput Voltage VIN -0.3 to V CC + 0.3VRespect to GNDOperating Temperature Topr o to 70 °cStorage Temperature Tstg -55 to 150 °cPower Dissipation Po 1.0 W Ta = 25°CRECOMMENDED OPERATING CONDITIONSupply VoltageParameter Symbol Min. Typ. Max. Unit ConditionsVCC 4.5 5 5.5 V 5V ± 10%VSS0 VInput VoltageVIH 2.2 VCC + 0.3 V5V ± 10%VIL -0.3 0.8 VOutput LoadCL 100 pFTTL 1314

-----------------. STATIC RAM ·MSM51257RS/JS •DC CHARACTERISTICSParamterSymbolMin.MSM51257Typ.Max.UnitTest ConditionInputLeakage III -1Current1 jjAVIN = 0 to VCCOutputLeakage ILO -1Current1 jjACS = VIH orOE = VIHV I/O = 0 to VCCOutput VOH 2.4VoltageVOLV0.4 V10H = -1 mA10L =2.1 mAStandbySupplyICCS0.02 1 mACS ;::; VCC - 0.2VVIN = 0 to VCCCurrentICCSl3 mACS = VIHtcyc = Min, cycleOperatingSupplyCurrentICCA70mAMIN CYCLEAC CHARACTERISTICSTest ConditionParameterI nput Pulse LevelInput Rise and Fall TimesI nput and OutputTim ing Reference LevelOutput LoadConditionsVIH = 2.4V, VI L = 0.6V5ns1.5VCL=l00 pF, 1 TTL GateREAD CYCLE(Vcc = 5V ± 10%, Ta = O°C to 70°C)ParameterRead Cycle TimeAddress Access TimeChip Enable Access TimeOutput Enable to Output ValidChip Selection to Output ActiveOutput Hold Time FromAddress ChangeOutput 3-state from DeselectionOutput Enable to Output ActiveMSM51257-85SymbolMin. Max.tRC 85tAC 85tco 85tOE 45tcx 10tOHA 5tOTD 0 30tox 5MSM51257-10 MSM51257-12UnitMin. Max. Min. Max.100 120 ns100 120 ns100 120 ns50 60 ns10 10 ns10 10 ns0 35 0 40 ns5 5 ns315

• STATIC RAM ·MSM51257RS/JS •• ----------------READ CYCLE~------------tRC----------~I/O --------:;;.:....*-f-(Notes:1. A Read occurs during the overlap of a low CS, a low OE and ahigh WE.2. tcx is specified from CS or OE, whichever occurs last.3. tOTO is specified from CS or OE, whichever occurs first.4. tOHA and tOTO are specified by the time when DATA OUT is floating.WRITE CYCLE(Vee = 5V ± 10%, Ta = DoC to +70°C)MSM51257·85 MSM51257·10 MSM51257·12Item Symbol UnitMin. Max. Min. Max. Min. Max.Write Cycle Time twc 85 100 120 nsAddress to Write Setup Time tAS 0 0 0 nsWrite Tima tw 65 75 90 nsWrite Recovery Time tWR 5 10 10 nsData Setup Time tDS 35 40 50 nsData Hold from Write Time tDH 0 0 0 nsOutput 3·5tate from Write tOTW 0 30 0 35 0 40 nsChip Selection to End of Write tcw 75 90 100 nsAddress Valid to End of Write tAW 75 90 100 nsOutput Active from End of Write twx 5 5 15 nsNotes:1. A Write Cycle Occurs during the overlap of a low CS, and a low WE.2. OE may be both high and low in a Write Cycle.3. tAS is specified from CS or WE, whichever occurs last.4. tw is an overlap time of a low CS,and a low WE.5. tWR tDS and tDH are specified from CS or WE, whichever occurs first.6. to-rW is specified by the time when DATA OUT is floating, not defined by output level.7. When I/O pins are Data output mode, don't force inverse signal to those pins.316

-----------------. STATIC RAM' MSM51257RS/JS •WRITE CYCLE~-------------~C------------~~------tw------~CS~--+---+----tAW--------~~~.--+-----tcw------~!I/O (DIN) -------4-----1(CAPACITANCE(Ta ~ 25°C, f ~ 1 MHz)ParameterSymbolMin.Typ. Max. UnitInput/Output CapacitanceInput CapacitanceCliOCIN8 pF6 pFNote: This parameter is periodically sampled and not 100% tested.317

OKI semiconductorMSM51257LRS/JS32,768-WORD x 8-BIT CMOS STATIC RAMGENERAL DESCRIPTIONThe MSM51257LRS/JS is a 32768-word by 8-bit CMOS static RAM featuring 5V power supply operation and directTTL input/output compatibility. Since the circuitry is completely static,external clock and refreshing operations areunnecessary, making this device very easy to use. The MSM51257LRS/JS is also a CMOS silicon gate device whichrequires very low power during standby (standby current of 1 OOIlA) when there is no chip selection.CS and OE signals enable OR ties with the output terminals of other chips, thereby facilitating simple memoryexpansion and bus line control etc.FEATURES• Single 5V Supply• rfc - 7rfC• Low Power DissipationStandby; 0.55 mW MAXOperation; 385 mW MAX• High Speed (Equal Access and Cycle Time)85-120 ns MAX• Direct TTL Compatible. (Input and Output)• 3-State Output.28-pin DIP PKG• 32-pin PLCCPIN CONFIGURATION(TOP VIEW).£

----------------1. STATIC RAM· MSM51257LRS/JS •FUNCTIONAL BLOCK DIAGRAM4--------0 Vee-E----OVsses~~Wem ~==~~-------------------------------~319

• STATIC RAM· MSM51257LRS/ JS •• -----------------TRUTH TABLEMode CS WE OE I/O Ope rat ionStandby H X X High ZL H H High ZReadL H LDOUTWreite L L X DINX: H or LABSOLUTE MAXIMUM RATINGSRating Symbol Value Unit ConditionsSupply Voltage VCC -0.3 to 7.0 VI nput Voltage V,N -0.3 to VCC + 0.3VOperating Temperature Topr o to 70 °cStorage Temperature Tstg -55 to 150 °cRespect to GNDPower Dissipation PD 1.0 W Ta ~ 25°CRECOMMENDED OPERATING CONDITIONSupply VoltageParameter Symbol Min. Typ. Max. Unit ConditionsVCC 4.5 5 5.5 V 5V ± 10%VSS 0 VData Retention Voltage VccH 2 5 5.5 VV,HInput Voltage2.2 VCC + 0.3 V5V ± 10%V,L -0.3 0.8 VOutput LoadCL 100 pFTTL 1320

-----------------I.STATICRAM·MSM51257LRS/JS.DC CHARACTERISTICSParamterSymbolMin.MSM51257Typ.Max.UnitTest ConditionInputLeakage III -1Current1 IJAVIN=OtoVCCOutputLeakage ILO -1Current1 IJACS = VIH orOE = VIHVI/O = 0 to VCCOutput VOH 2.4VoltageVOLV0.4 VIOH = -1 mAIOL = 2.1 mAStandbySupplyICCS2 100 IJACS ~ VCC - 0.2VVIN = 0 to VCCCurrentICCS13 mACs = VIH,OperatingSupplyCurrentICCA70mAMIN CYCLEAC CHARACTERISTICSTest ConditionParameterInput Pulse LevelInput Rise and Fall TimesI nput and OutputTiming Reference LevelOutput LoadConditionsVIH = 2.4V, VIL = 0.6V5ns1.5VCL =100 pF, 1 TTL GateREAD CYCLE(Vcc = 5V ± 10%, Ta = O°C to 70°C)ParameterRead Cycle TimeAddress Access TimeChip Enable Access TimeOutput Enable to Output Val idChip Selection to Output ActiveOutput Hold Time FromAddress ChangeOutput 3·state from OeselectionOutput Enable to Output ActiveMSM51257L-85 MSM51257L-l0 MSM51257L-12SymbolUnitMin. Max. Min. Max. Min. Max.tRC 85100 120 nstAC 85100 120 nstco 85100 120 nstOE 4550 60 nstcx 10lQ 10 nstOHA 510 10 nstOTO 0 30 0 35 0 40 nstox 55 5 ns321

.STATICRAM·MSM51257LRS/JS •• ----------------READ CYCLE~-----------tRC----------~1/0 -------......::::.:..:....-K-~Notal:1. A Read occurs during the overlap of a low CS, a low OE and ahigh WE.2. tcx is specified from CS or OE, whichever occurs last.3. tOTO is specified from CS or OE, whichever occurs first.4. tOHA and tOTO are specified by the time when DATA OUT is floating.WRITE CYCLE(Vee = 5V ± 10%, Ta = O°C to +70 0 C)MSM51257L·85 MSM51257L·10 MSM51257L·12Item Symbol UnitMin. Max. Min. Max. Min. Max.Write Cycle Time twc 85 100 120 nsAddress to Write Setup Time tAS 0 0 0 nsWrite Time tw 65 75 90 nsWrite Recovery Time twR 5 10 10 nsData Setup Time tos 35 40 50 nsData Hold from Write Time tOH 0 0 0 nsOutput 3·State from Write tOTW 0 30 0 35 0 40 nsChip Selection to End of Write tcw 75 90 100 nsAddress Valid to End of Write tAW 75 90 100 nsOutput Active from End of Write twx 5 5 15 nsNotes:1. A Write Cycle occurs during the overlap of a low CS, and a low WE.2. OE may be both high and low in a Write Cycle.3. tAS is specified from CS or WE, whichever occurs last.4. tw is anoverlap time of a low CS, and a low WE.5. tWR, tos and tOH are specified from CS or WE, whichever occurs first.6. tOTW is specified by the time when DATA OUT is floating, not defined by output leve\.7. When 110 pins are Data output mode, don't force inverse signal to those pins.322

----------------... STATIC RAM· MSM51257LRS/JS •WRITE CYCLE~-------------~C------------~CSI/O (DIN) ------~I----~I/O (DOUT) _______ JLOW VCC DATA RETENTION CHARACTERISTICS(Ta = O°C to +70°C, unless otherwise noted)Parameter Symbol Min. Typ. Max. Unit ConditionsVCC for Data Retention VCCH 2 V C S ~ VCC - 0.2VData Retention Current ICCH 1 50 p.A VCC = 3V, CS ~ VCC - 0.2VCS to Data Retention Time tsu 0 nsOperation Recovery Time tR tRC ns323

.STATICRAM·MSM51257LRS/JS •• ----------------CS CONTROLVCC4.5VCS ~ VCC - O.2VCAPACITANCE(Ta = 25°C, f = 1 MHz)ParameterSymbolMin.Typ. Ma~. UnitInput/Output CapacitanceInput CapacitanceCliOCIN8 pF6 pFNote: This parameter is periodically sampled and not 100% tested.324

MOSMASKROMS

OKI semiconductorMSM3864RS8,192 WORD x 8 BIT MASK ROMGENERAL DESCRIPTIONThe MSM3864RS is an N-channel silicon gate MOS device MASK ROM with a 8,192 word x 8 bit capacity. It operateson a 5V single power supply and the all inputs and outputs are TTL compatible. The adoption of an asynchronoussystem in the circuit requires no external clock assuring extremely easy operation. The availability of powerdown mode contributes to the low power dissipation which is as low as 30mA (max) when the chip is not selected.The application of a byte system and the pin compatibility with standard UV EPROMs make the device mostsuitable for use as a large-capacity fixed memory for microcomputers and data terminals.As it provides CE, OE, and CS as the control signal, the connection of output terminals of other chips with the wiredOR is possible ensuring an easy expansion of memory and bus line control.FEATURES• 5V single power supply.8,192 words x 8 bits• Access time: 250 ns MAX• Input/output TTL compatible• 3-state output• Power down mode• 28-pin DIPFUNCTIONAL BLOCK DIAGRAMPIN CONFIGURATION(Top View)NC 1 \,J 28 v"A" 2 27 CS2 (CS2)(NCIA, 3 26 CSlICS111NCIA,•25 A,A, 5 2. A,A, 6 23 A"A, 7 22 OE (OE)A, 8 21 A"A, 9 20 CEAo 10 19 0,Do"18 0,0, 12 17 D,0, 13 16~D4v" 14 15ho,DEOutput enableVee, Vss Power supplyAo""-'A12 Address input00-07 Data outputCECh ip enableCS1, CS2 Chip selectNote: Please specify the OE activelevel and CS active level oropen in ordering this IC.AoA,A,A"A,A,A,A,A,A,A"A"A"Addressbuffer326

--------------------------------------_._MASKROM·MSM3864RS_ABSOLUTE MAXIMUM RATINGS(Ta = 25'C)RatingPower Supply VoltageInput VoltageOutput VoltagePower DissipationOperating' TemperatureStorage TemperatureSymbolVeeVIVoPDT oprT stgValue Unit Conditions-0.5 to 7 V Respect to V 55-0.5 to 7 V Respect to V 55-0.5 to 7 V Respect to Vss1 W Per packagea to 70 °c-55 to 150 °cOPERATING CONDITION AND DC CHARACTERISTICSRatingParameter Symbol Measuring ConditionUnitMin. Typ. Max.Power Supply VoltageI nput Signal LevelOutput Signal LevelVee - 4.5 5 5.5 VVss - a a a VVIH - 2 5 6 VVIL - -0.5 a 0.8 VVOH 10H = -4001J.A 2.4 - Vee VVOL 10L = 2.1 mA - 0.4 VInput Leakage Current III VI = OV or Vee -10 - 10 IJ.AOutput Leakage Current ILOVo = OV or VeeChip not selected-10 - 10 IJ.AIcc Vee = Max. 10 = a mA - - 100 mAPower Supply CurrentIces Vee= Max. CE = VIH, 10= OmA - - 30 mAPeak Power ON Current IpoVee = GND - Vee Min.CE = Vee or VIH- - 60 mAOperating Temperature T opr - a - 70 °cAC CHARACTERISTICSTIMING CONDITIONSParameterConditionsInput Signal LevelInput Rising, Falling TimeTiming Measuring Point VoltageLoading Conditiontr=tf=15 nsInput Voltage=1.5VOutput Voltage=0.8V & 2.0V327

• MASK ROM . MSM3864RS .1-------------------READ CYCLE(VCC = 5V ±10%, VSS = OV, Ta = O°C to +70 0 C)ParameterCycle TimeAddress Access TimeChip EnableAccess TimeOutput Delay TimeOutput Setting TimeOutput Disable TimeOutput Retaining TimePower Up TimePower Down TimeSpecification ValueSymbolMin. Typ. Max.Unittc 250 - nstAA - - 250 nstACE - - 250 nstco - - 100 nstLZ 10 - - nstHZ 10 - 100 nstOH 10 - - nstpu 0 - nstPD - - 100 nsRemarks1) READ CYCLE-1 (1)~------------------tc------------------AddressCS DE (3)(CS) or (DE)(4)i------tHZDout2) READ CYCLE-2(2)i------------------tc---------------~1~------tACE------~CS DE (3)(CS) or (DE)DoutVccsupplycurrenttpu328

------------------___ • MASK ROM . MSM3864RS •Notes: (1) el: is "L" level.(2) The address is decided at the same time as or ahead ofCE"L" level.(3) The OE and CS are shown in the negative logic here, however the active level is freely selected.(4) tLz is determined by the later level, CE "L"tCS "L" or ~ "L".tHz is determined by the earlier CE "H"tCS "H" or OE "H".While, tHz shows the time until floating and it is therefore not determined by the output level.INPUT/OUTPUT CAPACITANCEITa = 25°C, f = 1 MHz)SpecificationParameter Symbol Value Unit RemarksMin. Max.Input Capacitance CI 8 pF VI=OVOutput Capacitance Co 10 pF VO=OV329

OKI semiconductorMSM38128ARS16,384 WORD x 8 BIT MASK ROM (E3-5-028-32)GENERAL DESCRIPTIONThe MSM38128ARS is an N-channel silicon gate MOS device MASK ROM with a 16,384 word x 8 bit capacity. Itoperates on a 5V single power supply and the all inputs and outputs are TTL compatible. The adoption of an asyn·chronous system in the circuit requires no external clock assuring extremely easy operation. The avaUability of powerdown mode contributes to the low power dissipation which is as low as 30mA (max) when the chip is not selected.The application of a byte system and the pin compatibility-with standard UV EPROMs make the device most suitablefor use as a large-capacity fixed memory for microcomputers and data terminals.As it provides CE, OE, and CS as the control signal, the connection of output terminals of other chips with the wiredOR is possible ensuring an easy expand operation of memory and bus line control.FEATURES• 5V single power supply• 16384 words x 8 bits• Access time: 250 ns MAX• Input/output TTL compatible.3-state output• Power down mode• 28-pin DIPFUNCTIONAL BLOCK DIAGRAMPIN CONFIGURATION11NC(Top View)1 '--" 28 VeeA" 2 27 CS(CSJfNCiA, 3 26 A"A. 4 25 A,A, 5 24 A,A. 6 23 A"A, 7 22 OE (OE)A, 8 21 A"A, 9 20 CEA. 10 19 0,Do 11 18 D.0, 12 17 0,A.A,A,A,A.A,A.A, bufferA,A,A"A"A"A"OE CEControl--0 Vee-...oVssCSorCS orNCDEarOE0, 13 16 D.V .. 14 15 0,OE Output enableVee, Vss Power supplyAo"'" Au Address input~- 07 Data outputCEChip enableCh ip sel actesNote: Please specify the OE activelevel and CS active level oropen in ordering this IC.330

-----------------__._ MASK ROM ·MSM38128ARS _ABSOLUTE MAXIMUM RATINGS(Ta = 25°CIRatingPower Supply VoltageInput VoltageOutput VoltagePower DissipationOperating TemperatureStorage TemperatureSymbolVccVIVoPoToprT stgValue Unit Conditions-0.5 to 7 V Respect to V ss-0.5 to 7 V Respect to V ss-0.5 to 7 V R espeet to V ss1 W Per paekageoto 70 °c-55 to 150 °cOPERATING CONDITION AND DC CHARACTERISTICSRatingParameter Symbol Measuring Condition UnitMin. Typ. Max.Power Supply VoltageI nput Signal LevelOutput Signal LevelVee - 4.5 5 5.5 VVss - 0 0 0 VVIH - 2 5 6 VVIL - -0.5 0 0.8 VVOH 10H =-400/J.A 2.4 - Vee VVOL 10L = 2.1 mA - 0.4 VInput Leakage Current ILl VI =OVorVee -10 - 10 /J.AOutput Leakage CurrentPower Supply CurrentPeak Power ON CurrentILOVo = OVor VeeCh ip not selected-10 - 10 /J.Alee Vee = Max. 10 = 0 mA - - 100 mAlees Vee = Max. - - 30 mAIpoVee = GND - Vee Min.- - 60 mACE = Vee or VIHQperating Temperature Topr - 0 - 70 °cAC CHARACTERISTICSTIMING CONDITIONSParameterI nput Signal LevelInput Rising, Falling TimeTiming Measuring Point VoltageLoading ConditionConditionstr=tf=15 nsInput Voltage=15VOutput Voltage=0.8V & 2.0VCL =100 pF + 1 TTL331

.MASKROM·MSM38128ARS •• -------------------------------------READ CYCLECycle TimeParameterAddress Access TimeChip EnableAccess TimeOutput Delay TimeOutput Setting TimeOutput Disable TimeOutput Retaining TimePower Up TimePower Down Time(VCC = 5V ±10%, VSS = OV, Ta = O°C to +70°C)SymbolMin.Specification ValueTyp.tc 250 -tAA - -tACE - -tco - -tLZ 10 -tHZ 10 -tOH 10 -tpu 0 -tpD - -Max.Unitns250 ns250 ns100 ns- ns100 ns- nsns100 nsRemarks1) READ CYCLE-1 (1)AddressCS OE (3)(CS) or (OE)(4)i-----tHZDout2) READ CYCLE-2(2)i-----------tc--------------~1~----tACE------~CS OE (3)(CS) or (OE)DoutVccsupplycurrent332

------------------------------------___ MASKROM·MSM38128ARS_Notes: (1) CE is "L" level.(2) The address is decided at the same time as or ahead o(CE "L" level.(3) The 0 E and CS are shown in the negative logic here, however the active level is freely selected.(4) tLz is determined by the later level, CE "L",CS "L" or 01: "L".tHz is determined by the earlier CE "H",CS "H" or OE "H".While, tHz shows the time until floating and it is therefore not determined by the output level.INPUT/OUTPUT CAPACITANCE(Ta = 25°C, f = 1 MHz)ParameterInput CapacitanceOutput CapacitanceSymbolCICoMin.SpecificationValue Unit RemarksMax.8 pF V,=OV10 pF VO=OV333

OKI semiconductorMSM38256RS32768 WORD x 8 BIT MASK ROM (E3-S-029-321GENERAL DESCRIPTIONThe MSM38256RS is an N-channel silicon gate MOS device ROM with a 32,768 word x 8 bit capacity. It operateson a 5V single power supply and the all inputs and outputs are TTL compatible. The adoption of an asynchronoussystem in the circuit requires no external clock assuring extremely easy operation. The availability of powerdown mode contributes to the low power dissipation which is as low as 30mA (max) when the chip is not selected.The application of a byte system and the pin compatibility with standard UV EPROMs make the device most suitablefor use as a large-capacity fixed memory for microcomputers and data terminals.Since it provides CE, CS and OE signals, the connection of output terminals of other chips with the wired OR ispossible ensuring an easy expand operation of memory and bus line control.FEATURES• 32768 words x 8 bits• 5V single power supply• Access time: 250 ns MAX• Input/output TTL compatible.3-state output• Power down mode• 28-pin DIPFUNCTIONAL BLOCK DIAGRAMIIPIN CONFIGURATION(Top View) A.ICS)(NCI CS 1 28 v""A,A,A" 2 27 A ..A,A, 3 26 A" A.A. 4 25 A. A,A, 5 24 A, A.A. 6 23 AllA,A.A, 7 22 OE 10E)A,A, 8 21 A"A, 9 20 CEAllA. 10 19 D,Do 11 18 D.D, 12 17 D, A I4 O---D, 13 16 D.Vss 14 15 0 3CSChip Select~ Output enableVee, VIS Power supply voltageA.-A,. Address input~-07 Oata outputChip anable--aVe

------------------.... MASK ROM . MSM38256RS •ABSOLUTE MAXIMUM RATINGS(Ta = 25·C)RatingPower Supply VoltagaInput VoltagaOutput VoltageOperating TemperatureStoraga TemperatureSymbolVeeVIVoToprT stgValue Unit Conditions-0.5 to 7 V-0.5 to 7 V Respect to V SS-0.5 to 7 VOto 70 ·C-55 to 150 ·COPERATING CONDITION AND DC CHARACTERISTICSParameter Symbol Measuring ConditionPower Supply VoltagaI nput Signal LevelOutput Signal LevelRatingMin. Typ. Max.Vee 4.5 5 5.5Vss 0 0 0VIHI 2 5 6VIL -0.5 0 0.8VOH 10H = -400 IlA 2.4 VeeVOL 10L = 2.1 mA0.4Input Leakage Current III VI =OVorVee -10 10Output Leakage CurrentPower Supply CurrentPeak Power ON CurrentILOVo = OVor VeeCh ip not selected-10 10lee Vee = Max. 10 = 0 mA 120lees Vee = Max. 30IpoVee = GND - Vee Min.CE = VCC or VIHOperating Temperature Topr 0 7060UnitVVVVVVIlAIlAmAmAmA·CAC CHARACTERISTICSTIMING CONDITIONSParameterInput Signal LevelInput Rising, Falling TimeTiming Measuring Point VoltageLoading ConditionConditionstr=tf=15 nsInput Voltage=I.5VOutput Voltage=0.8 & 2.0VCL=100 pF + 1 TTL335

.MASKROM·MSM38256RS •• ------------------------------------READ CYCLE(VCC = 5V ±10%, VSS = OV, Ta = O°C to +70° C)ParameterSymbolCycle TimetcAddress Access TimetAAChip EnabletACEAccess TimeOutput Delay Time tcoOutput Setting TimetLZOutput Disable TimetHZOutput Retaining Time tOHPower Up TimetpuPower Down TimetpDSpecification ValueMin. Typ.2501010100Max.Unitns250 ns250 ns100 nsns100 nsnsns100 nsRemarks1) READ CYCLE-1 (1 )Address~(3)(4)i----tHZDout2) READ CYCLE-2(2)i----------tc-------~OE (3)CSDoutVccsupplycurrentIccIcestpu336

------------------.... MASK ROM . MSM38256RS •Notes:(1) 'CE is "L"level.(2) The address is decided at the same time as or ahead of CE "L" level.(3) or: and CS are shown in the negative logic here, however the active level is freely selected.(4) tco and tLZ are determined by the later CE "L", OE "L" or CS "L".tHz is determined by the earlier CE "H", OE "H" or ~ "H".tHz shows time until floating therefore it is not determined by the output level.INPUT IOUTPUT CAPACITANCE(Ta = 2S·C, f = 1 MHz)SpecificationParameter Symbol Value Unit RemarksMin. Max.Input Capacitance CI 8 pF VI=OVOutput Capacitance Co 10 pF VO=OV337

OKI semiconductorMSM38256ARS32768 WORD x 8 BIT MASK ROM (E3-S-030-32)GENERAL DESCRIPTIONThe MSM38256ARS is an N·channel silicon gate E/DMOS device ROM with a 32,768 word x 8 bit capacity. Itoperates on a 5V single power supply and the all inputs and outputs are TTL compatible. The adoption of an asyn·chronous system in the circuit requires no external clock assuring extremely easy operation. The availability of powerdown mode contributes to the low power dissipation which is as low as 6mA (max) when the chip is not selected. Theapplication of a byte system and the pin compatibility with standard UV EPROMs make the device most suitable foruse as a large-capacity fixed memory for microcomputers and data terminals.Since it provides CE, DE, CS signals, the connection of output terminals of other chips with the wired OR is possibleensuring an easy expand operation of memory and bus line control.FEATURES• 32768 words x 8 bits• 5V single power supply• Access time: 150 ns MAX• Input/output TTL compatible• 3-5ta18 output• Power down mode• 28-pin DIPFUNCTIONAL BLOCK DIAGRAMPIN CONFIGURATION(Top View)ICSICSINCI I 28 VeeCEDE(CS) CSVee, VssA.-A,.De-D,(NC)A" 2 27 A ..A, 3 26 A"A" 4 25 A.A, 5 24 A,A,. 6 23 AuA, 7 22 DEA, 8 21 A"A, 9 20 crAo to 19 0,Do 11 18 0,0, 12 17 0,0, 13 16 D.VSS 14 15 D3Chip enableOutput enableChip selectPower supply voltageAddress inputData outputNo ConnectionNote: CS active level is specifiedby customers.A.A,A,A,A.A,A,A,A.A,A"AuA"A"A I4o--bufferCE.OE,CSControl--0 Vec--0 V ..DEL-__ .r~cs0,CSmNC338

-----------------_____ MASK ROM· MSM38256ARS _ABSOLUTE MAXIMUM RATINGS(Ta = 25°C)Rating Symbol Value Unit ConditionsPower Supply Voltage Vee -0.5 to 7 VInput Voltage VI -0.5 to 7 V Respect to V SSOutput Voltage Vo -0.5 to 7 VOperating Temperature Topr Oto 70 °cStorage Temperature T stg -55 to 150 °cPower Dissipation PD 1.0 W Per packageOPERATING CONDITION AND DC CHARACTERISTICSRatingParameter Symbol Measuring Conditions UnitMin. Typ. Max.Power Supply VoltageVee 4.5 5 5.5 VVss 0 0 0 V"H" Input Signal Level VIH 2.2 5 6 V"L" Input Signal Level VIL -0.5 0 0.8 V"H" Output Signal Level VOH 10H = -400p,A 2.4 Vee V"L" Output Signal Level VOL 10L = 2.1 mA 0.4 VInput Leakage Current III VI =OVor Vee -10 10 p,AOutput Leakage CurrentPower Supply CurrentPeak Power On CurrentILOVo=OVorVeeChip not selected-10 1:> p,AIcc Vee = Max. 10 = 0 mA 60 mAIces Vee = Max. 6 mAIpoVee = GND - Vee Min.CE = Vee or VIH60 mAOperating Temperature Topr 0 70 °cLoad Capacitance CL 100 pFFan Out N TTL Load 1 PieceAC CHARACTERISTICSTIMING CONDITIONSParameterInput Signal LevelInput Rising, Falling TimeTiming Measuring Point VoltageLoading ConditionConditionstr=tf=15 nsInput VOltage=1.5VOutput Voltage=0.8 & 2.0V339

.MASKROM·MSM38256ARS.I-------------------------------------READ CYCLEParameterCycle TimeAddress Access TimeChip EnableAccess TimeOutput Delay TimeOutput Setting TimeOutput Disable TimeOutput Retaining TimePower Up TimePower Down TimeSpecification ValueSymbolMin. Typ. Max.Unittc 150 nstAA 150 nstACE 150 nstco 50 nstLZ 10 nstHZ 10 50 nstOH 10 nstpu 0 nstpD 100 nsRemarks1) READ CYCLE-1 (1)~-----------------~-------------~~AddressCS __ (3)CS or OE(4)i------tHZDout2) READ CYCLE-2(2)~CEtccs en:: (3)CS or 0DoutVccsupplycurrentIccIccstpu340

-----------------____ MASK ROM . MSM38256ARS _Notes: (1) cr is "L" level.(2) The address is decided at the same time as or ahead of CE "L" level.(3) CS are shown in the negative logic here, however the active level is freely selected.(4) teo and tLZ are determined by the later CE "L", OE "L" Or CS "L".tHz is determined by the earlier CE "H", OE "H" or CS "H".tHz shows time until floating therefore it is not determined by the output level.INPUT/OUTPUT CAPACITANCEITa ~ 25°C, f = 1 MHz)ParameterSymbolSpecificationValueUnitRemarksMin.Max.Input Capacitance C,8 pFV,~OVOutput CapacitanceCo6 pFVO=OV341

_O_K __ I __ se __ rn_i_c_O_ncl __MSM38512RS ~65536 WORD x 8 BIT MASK ROMU_c_._o_r _____ ~GENERAL DESCRIPTIONThe MSM3851:?RS is an N-channel silicon gate E/DMOS device ROM with a 65,536 word x 8 bit capacity. Itoperates on a 5V single power supply and the all inputs and outputs are TTL compatible. The adoption of an asynchronoussystem in the circuit requires no external clock assuring extremely easy operation. The availability of powerdown mode contributes to the low power dissipation which is as low asl0mA(max) when the chip is not selected. Theapplication of a byte system and the pin compatibility with standard UV EPROMs make the device most suitable foruse as a large-capacity fixed memory for microcomputers and data terminals.Since it provides CE, OE, signals, the connection of output terminals of other chips with the wired OR is possibleensuring an easy expand operation of memory and bus line control.FEATURES• 512k bits: 65,536 words x 8 bit• high speed: access time 200 ns maX• low power: active current 60 mA maxstandby Current lamA max• wide tolerance operating: Vcc ~ 5 V ± 10%• fully static operating: using no clock• fully TTL compatible• pin compatible to 512k EPROM• packaged to 28 pins plastic• fabricated with 2um NMOS silicon gate technologyFUNCTIONAL BLOCK DIAGRAM[JPIN CONFIGURATION(Top View)A" 1 28 VeeA" 2 21 A ..A, 3 26 A"A. 4 25 A.A, 5 24 A.A,A,A,A,A,A. 6 23 A" A,Memorv cellMatrix65536 x 8 bit--0 Vee--oVssDEVee, VssA.-A,sCED.- D7A, 7 22 6E A.A, 8 21 A"A,A, 9 20 CE A.A, 10 19 0,A.00 11 18 D.A"0, 12 11 0,A"A"0, 13 16 0,A"v .. 14 15 D) A"Output enablePower supply voltageAddress inputChip enableData outputA"buffer342

------------------..... MASK ROM ·MSM38512RS •ABSOLUTE MAXIMUM RATINGS(Ta = 25"C)RatingPower Supply VoltageI nput VoltageOutput VoltagePower DissipationOperating TemperatureStorage TemperatureSymbolVeeVIVoPDToprTstgValue Unit Conditions-0.5 to 7 V Respect to VSS-0.5 to 7 V Respect to VSS-0.5 to 7 V Respect to VSS1 W Par packageo to 70 °c-55 to 150 °cOPERATING CONDITION AND DC CHARACTERISTICSParameterPower Supply VoltageInput Signal LevelOutput Signal LevelSymbolVeeVssVIHVILVOHVOLMeasuring Condition----10H = -400 !LA10L = 2.1 mARatingMin. Typ. Max.4.5 5 5.50 0 02.2 - 6-0.3 - 0.82.4 - -- - 0.4UnitVVVVVVInput Leak CurrentIIIVI =OVorVcc-10 - 10!LAOutpl/t Lea k CurrentIt.:OVO= OVor VCCCh ip not selected-10 - 10!LAPower Supply CurrentIccIces- - 60- - 10mAmAAC CHARACTERISTICSTIMING CONDITIONSParameterI nput Signal LevelInput Rising, Falling TimeTiming Measuring Point VoltageLoading ConditionConditionsVIH2.4V,VIL 0.6Vtr = tf = 15 nsInput Voltage = 1.5VOutput Voltage = O.BV & 2.0VCL= 100pF + 1 TTL343

• MASK ROM ·MSM38512RS ... ------------------READ CYCLECycle TimeParameterAddress Access TimeChip EnableAccess TimeOutput Delay TimeOutput Setting TimeOutput Disable TimeOutput Retaining TimePower Up TimePower Down TimexxxxxxValueSymbolUnitMin. Typ. Max.tc 200 - - nstAA - - 200 nstACE - - 200 nstco - - 50 nstLZ 10 - - nstHZ 10 - 50 nstOH 10 - - nstpu 0 - - nstPD - - 100 nsRemarks1) READ CYCLE-1 (1)~~----------------tc--------------~Address(Note 4)tHZDout2) READ CYCLE-2(2)~-----------------~-----------------1-___ tACE (Note 2)DoutVccsupplycurrentIccIcestpu344

------------------------------------__._MASKROM·MSM38512RS_Notes: (1) CE is "L" level(2) The address is decided at the same time as or ahead of CE "L" level.(3) tLZ is determined by the later level, CE "L" or OE "L".(4) tHZ is determined by the earlier CE "H" or OE "H".While, tHZ shows the time until floating and it is therefore not determined by the output level.INPUT/OUTPUT CAPACITANCE(Ta: 2S'C, f: 1 MHz)ParameterInput CapacitanceOutput CapacitanceSymbolCICoMin.SpecificationValue Unit RemarksMax.8 pF VI: OV10 pF VO: 0'(1345

OKI semiconductorMSM28101AASJAPANESE-CHARACTER GENERATING 1M BIT MASK ROM (E3-S-032-32lGENERAL DESCRIPTIONThe MSM 28101 AAS is aIM Bit Mask ROM using the N-channel silicon gate MOS process which stores 3,760 charactersof numeric characters, Japanese cursive and square syllabarys, JIS 1st standard Japanese-characters, etc., in onechip.Because of its large capacity, Japanese-character pattern of 3,760 characters can be generated with only one chip.Furthermore, since the dot matrix character form of 18 lines x 16 strings is available from the data out pin by onlyinputting the J IS Japanese-character code into the address pin, the MSM28101 AAS is efficient and optimum forconstituting the Japanese-character terminal.The power supply voltage is of 5 V single power supply, the input level is of TTL compatible, the data output is of3-state output, the data valid is the output of the open collector and is packaged on the 40-pin DIP.FEATURES• Function 18 x 16 chinese-character fontoutput• Configuration Duplex configuration of cellarrayusing the defect permissibletechnique• Storage capacity 1082880 Bits• Number of 3,418 charactersgeneratingcharacters• Storagecharacter range• Address input• Data output• Output mode• Address enablePartition 0 - 7 and partition16 - 47 of Japanese-charactercode system for JIS informationprocessing14 Bits (A.-Au)16Bits (D.-D 15 ,3-state)16 Bits x 18 times transfer1 each (AE)• Data valid• Clock• Used temperature• Access time• Data transferrate• Interface• Power supplyvoltage• Power consumption• Package• Memory cell1 each (DV, open collector output)1 each (T) DC - 1.5MHzTa ~ 0 - 70°C10 IJS MAX22 IJs/characterTTL level5V single power supply (±5%)700 mWTYPSide-brazed 40-pin DIPMulti-gate ROMThis specification is subject to change without notice(Top View)PIN CONFIGURATIONAo"'A13: Addroess inputDo ...... ~: Data outputAE: Address enableDV: Data valid outputT: Clock inputVCC: Power supply voltage (5V)VSS: GND (OV)(Note) Connect all VCC and VSS terminals.346

-----------------_____ MASK ROM· MSM281 01 AAS _FUNCTIONAL BLOCK DIAGRAM1lVAEI>rA"A, I>.DataA, Decoder1M Bit cell arraylatchA, 14bitA.A,A,A,A,AddressBufferA, rr.AlODecoder 1M Bit cell array DataA" latchA" 14 bitA"D";Ir,Ir,D";ll,I>.D";I>.OWI),;I),;rr,;rr,;lJ,;ABSOLUTE MAXIMUM RATINGS(Ta = 25·C)Rating Symbol Conditions Value UnitPower Supply Voltage Vcc Respect to Vss -0.5 -7· VInput Terminal Voltage VIN Respect to Vss -0.5 -7 VOutput Terminal Voltage VOUT Respect to Vss -0.5 -7 VPower Dissipation PD 2 WOperating Temperature Topr 0-70 ·CStorage Temperature Tstg -35 - 125 ·CRECOMMENDED OPERATING CONDITIONSSpecification valueParameter Symbol ConditionsMin. Typ. Max.UnitPower Supply Voltage Vcc 5V ± 5% 4.75 5 5.25 VPower Supply Voltage Vss 0 0 0 VInput Signal LevelVIH Respect to Vss 2.0 5 6 VVIL Respect to V ss -0.5 0 O.S VOperating Temperature Topr 0 70 ·C347

.MASKROM·MSM28101AAS.I-------------------------------------DC CHARACTERISTICS(Vcc = 5V ±5%, Ta = o°c to + 70°C)Output Signal LevelParameter Symbol ConditionsVOHVOLIOH=-0.2 mAIOL =1.6 mAInput Leakage Current III VIN=O -VccOutput Leakage CurrentILOVOUT=O -VccVAE=0.8VtRC=22/LSAverage Power Supply Current ICCA tC=650 mstAR=300 nsSteady State Power Supply Current ICCS V AE=0.8VSpecification valueUnitMin. Typ. Max.2.4 Vcc V0.4 V-10 10 p.A-10 10 p.A170 mA170 mAAC CHARACTERISTICSTIMING CONDITIONSParameterInput Signal LevelInput Rising, Falling TimeInput Timing LevelLoading ConditionConditionstr = tf = 15 ns1.5VCL = 50 pF, 1TTL GateREAD CYCLE(Vcc = 5V ±5%, Ta = O°C to +70°C)Parameter Symbol ConditionsMin.Specification ValueTyp.Max.UnitRead Cycle TimetRC22p.SAddress Setti ng Ti metAS0nsAE Pulse WidthtAE300nsAddress Retaining TimetAH100nsDV Access TimetvA10 p.SDV Delay TimetvD150 nsDV Retaining TimetVH100 ns¢T Pulse Width tH200ns¢T Delay Time tL450nsOutput Retaining TimetDH50nsAE Setting TimetAES0ns348

------------------___ MASK ROM· MSM28101 AAS _i r ADDRESS VALID DON'T CARE(Ao -A 13 )-]'-tAS--tAHC------AE------I~---------------------tRC------------------~DOUT(0.-0-;-,)High ImpedanceHigh Impedance(Note 1)(Note 2)(Note 3)(Note 4)(Note 5)(Note 6)DV is determined by the falling of qn-.DV changes with the falling of qn-.qn- and On DATA are repeated 18 times during DV is Low.The On timing levels are 2.0 V and 0.8 V.Sometimes it will not normally operate unless input is made at least once withAE as the dummy after input of power supply.DV is an open collector output and On is a 3·stage output.INPUT/OUTPUT CAPACITANCE(Ta = 25°C, f = 1 MHz)Specification val ueParameter Symbol ConditionsMin. Typ. Max.Input Capacitance (excluding AE) CIN VIN = OV 8Input Capacitance (AE terminal! CIN VIN = OV 15Output Capacitance COUT VOUT = OV 8UnitpFpFpF349

_ MASK ROM· MSM281 01 AAS _____-----------------FUNCTIONAL CHARACTERISTICSParameter Specification Unit RemarksFont Type18 lines x 16 strings dot matrixOutput Mode 16 bits x 18 times transfer (Note 11Number of Generatingcharacters3418 WordStorage Character Rangeo - 7 (Non chinese-character area)16 - 47 (JIS -1st standard)Partition (Note 2)(Note 11The correspondence of the 181ines x 16 strings matrix and the data out pins are as shown in the diagrambelow_Output for the character portion will be Low (VOLI and the output for the background portion will beHigh (VoHI-4_-------16Iines--------18-II-l-~+--l t=AT17............... .1.-...... .1 t= AT 18ttftfffttt'fttftData out pins Do 0; 0; 0.0::; Os 0. D., D. D.D,oDIID12D'30,.lJ,";DV~I ----~11~------------------~qyr~I I II- .1- .1AT, AT.(Note 2)The correspondence of the 1st and 2nd bytes of JIS C 6226 and the address pins are as shown below.JIS C 6226Second byteFirst byteb, I b. I bs I b. I b3 I b. I b, b, I b. I bs I b. I b3 I b. I b,Address Pin A'3 I A,. I All I A,o I A. I A. I A, A. I As I A. I A3 I A. I A, I A.350

OKI semiconductorMSM28201AAS1M BIT MASK ROM FOR JAPANESE-CHARACTER PATTERN (E3-S-033-32)GENERAL DESCRIPTIONThe MSM28201 AAS is aIM-bit mask ROM employing an N-channel silicon gate MOS process, and with 3760 Japanese-characters(kanji conforming with JIS No.2 standards) incorporated in single chip.With this large capacity, 3760 Japanese-character patterns can be generated in a single chip. And by only a singleinput of JIS Japanese-character code via the address pin, 18-row x 16-column dot matrix character forms can beobtained from the data output p.in, making this device ideal for construction of functionally versatile Japanese-characterterminals.The power supply voltage is 5V single, the input level TTL compatible, outputs are tri-state data out, and data validis denoted by open collector. The device is mounted in a 40-pin DIP.FEATURES• Function ....... 18 x 16 chinese-character fontoutput• Configuration .... Duplex configuration employingdefect permissible technique• Storage capacity. . . 1082880 bits• Number of generatedcharacters . . . . . . 3384 characters• Accommodation. _ . Japanese-character encodedcharacter region partitions 48 to 87 for JISdata processing.• Address input .... 14 bits (Ao to All)• Data output _.... 16 bits (Do to 0", tristate)• Output mode . . . . 16 bit x 18 transfers• Address enable ... 1 (AE)• Data valid ...... 1 (DV, open collector output)• Clock ......... 1 (4)T) DC to 1.5MHz• Operating temperature....... _.. Ta=O·C to 70·C• Access time ..... 10 lotS MAX.• Data transfer rate . . 22 lots/character• Interface ....... TTL level• Power supply voltage 5V si ngle (± 5%)• Power consumption. 700 mW TYP• Package. . . . Side-brazed 40-pin DIP• Memory cell ..... Multi-gate ROM(Top View)PIN CONFIGURATIONAo - Au: Address inputsDo - t>.,: Data outputsA E: Address enableDV: Data valid output4>T: Clock inputVcc: Power supply voltage (5 V)Vss: GND (0 V)Note: All Vss pins are to be connected351

• MASK ROM . MSM28201AAS •• -------------...,-------FUNCTIONAL BLOCK DIAGRAM1WAE...A"A,J:iODataDecoder1M 81teel1 array1),A, latchn;A,14bitn;A,1),A,AddressJ:iOA.BufferD:A,n;A.--00;A,0;DataDecoder1M Biteell artayA" latch0-;;;0;;AI:14 bit0;;A"0;;D;

------------------------------------___ MASKROM·MSM28201AAS_DC CHARACTERISTICS(Vcc= SV ±S%, Ta= O°Cto +70°C)Parameter"H" Output Voltage"L" Output VoltageInput Leakage CurrentSymbolVOHVOLIIIRange ValueConditionsUnitMin. Typ. Max.IOH --0.2 mA 2.4 VCC VIOL = 1.6 mA 0.4 VVI = 0 - VCC -10 10 p.AOutput Leakage CurrentILOVo = 0 - VCCVAE = 0.8V-10 10 p.AAverage Power Supply CurrentICCAtRC = 22p.S, tc = 6S0 nstAE = 300ns170 mARated Power Supply CurrentICCSVAE = 0.8V 170 mAAC CHARACTERISTICSTIMING CONDITIONSParameterInput Signal LevelInput Rise/Fall TimeInput Timing LevelOutput LoadConditionstr=tf=lSns1.SVCL =SOpF, lTTL GateREAD CYCLE(VCC = SV ±S%, Ta = o°c to +70°C)ParameterSymbolConditionsSpecification ValueMin. Typ. Max.UnitRead Cycle TimeAddress Setting TimeAE Pulse WidthAddress Retaining TimeDV Access TimeDV Delay TimeDV Retaining TimeT Pulse WidthT Delay TimeOutput Retaining TimeAE Setting TimetRCtAStAEtAHtvAtVDtVHtHtLtDHtAES22 p.S0 ns300 ns100 ns10 p.SISOns100 ns200 ns4S0nsSOns0 ns353

.MASKROM·MSM28201AAS •• -----------------------------------Address(A. -AnI ___ JVALIDDON'T CAREAEtVA(Note 31o OUT ----------r---------

-------------------------------------.MASKROM·MSM28201AAS.FUNCTIONAL CHARACTERISTICSFont FormatParameter Range Unit Remarks18-row x 16-column dot matrixOutput Mode 16 bit x 18 transfers (Note 1)Number of Characters Generated 3384 WordCharacter Accommodation Region 48~87 (JIS No.2 standard) Partition (Note 2)Note 1. The relation between the 18-row x 16-eolumn matrix and the data output pins is outlined below. The outputis low (VOL) for the character portion. and high (VOH) for the background area ..... -------16 columns ------.~~t=6.7 118t=6'1'2IIIIIIIIIIIIIIIttf::i;t::;~~;ttOataoutputpins 0;; 0, Dz 0,0. 0, D. D, 0. D. 0'00.,0120.,0..0"t=6T 18Note 2. The address pins are related to the JIS C6226 no.l and no.2 bytes in the following way.JIS C 6226No.2 byteNo.1 byteb, I b. I bs I b. I b, I bz 1 b, b, I b, I b, I b. I b. I bz I b,Address Pin Au I Au I A" I A,. I A. I A. I A, A. I As I A. I A. I A. I A, I A.355

OKI semiconductorMSM53256RS32,768 WORD x 8 BIT MASK ROMGENERAL DESCRIPTIONThe MSM53256RS is a silicon gate CMOS devic.e ROM with 32,768 words x 8 bit capacity. It operates on a 5Vsingle power supply and all inputs and outputs are TTL compatible. The adoption of an asynchronous system in thecircuit requires no external clock assuring extremely easy operation. The availability of power down mode contributesto the low power dissipation when the chip is not selected. The application of a byte system is most suitablefor use as a large capacity fixed memory for microcomputers and data terminals.Since it provides signals, the connection of output terminals of other chips with the wired OR is possible ensuring aneasy expand operation of memory and bus line control.FEATURES• 256k bits: 32,768 words x 8 bits• High speed: access time 150 ns max• Low power: active current 15 mA maxstandby current 0.1 mA max• Wide tolerance operating: Vcc = 5V ± 10%• Fully static operating: using no clock• Fully TTL compatible• Pin compatible to 256k EPROM• Packaged to 28 pins plastic• Fabricated with CMOS silicon gate technologyFUNCTIONAL BLOCK DIAGRAMPIN CONFIGURATION(Top View)(NClleS) cs28 VeeA" 2 27 A"A, 3 26 A"A,•25 A,A, 5 2. A,A. 6 23 A"A, 7 22 OEA, 8 21 A"A, 9 20 CEA. 10 19 0,D. n 18 0,0, 12 17 0,D2 (13 16 D.Vssl14 15 0,A.A,A,A,A.A,A,A,A,A,A"A"A"A"L..--0 Vee--0 VssDCDEtoo- cs0'csNCCSOEVcc, VssAo-A'30 0 -0,CE: Chip selectOutput enablePower supply voltageAddress inputData output: CHip enableNote: CS active level is specifiedby customer.356

--------------------------------------.MASKROM·MSM53256RS.ABSOLUTE MAXIMUM RATINGS(Ta = 25°C)RatingPower Supply VoltageInput VoltageOutput VoltagePower DissipationOperating TemperatureStorage TemperatureSymbolVeeVIVoPoT oprT stgValue Unit Conditions-0.3 to 7 V Respect to Vss-0.3 to Vee + 0.3 V Respect to V ss-0.3 to Vee + 0.3 V Respect to Vss1 W Per packageo to 70 °c --55 to 150 °c -OPERATING CONDITION AND DC CHARACTERISTICSRatingParameter Symbol Measuring Condition UnitMin. Typ. Max.Power Supply VoltageInput Signal LevelOutput Signal LevelVee - 4.5 5 5.5 VVss -0 0 0 VVIH - 2.2 5 Vee +0.3 VVIL - -0.3 0 0.8 VVOH 10H = -4001J.A 2.4 - - VVOL 10L = 2.1 mA - - 0.4 VInput Leakage Current III VI = OV or Vee -10 - 10 IJ.AOutput Leakage CurrentILOICCAVo = OV or VeeChip not selectedVee = Max. 10 = 0 mA,tc = 150 ns-10 - 10 IJ.A- - 15 mAPower Supply Current ICCS Vee = Max. CE = Vee - 0.2V - - 0.1 mAICCSlVee = Max.CE = VIH min.- -0.5 mAOperating Temperature Topr - 0 - 70 °cAC CHARACTERISTICSTIMING CONDITIONSParameterConditionsInput Signal Level VIH = 2.4V, VI L = 0.6VInput Rising, Falling Timetr=tf=15 nsInput Voltage=1.5VTiming Measuring Point VoltageOutput Voltage=0.8V & 2.0VLoading ConditionCL=100pF + 1 TTL357

.MASKROM·MSM53256RS •• ------------------------------------READ CYCLE(Vee = 5V ±10%, VSS = OV, Ta = oOe to +70 0 e)Specification ValueParameter Symbol UnitMin. Typ. Max.Cycle Time tc 150 nsAddress Access Time tAA 150 nsChip EnableAccess TimetACE 150 nsOutput Delay Time tco 50 nsOutput Setting Time tLZ 10 nsOutput Disable Time tHZ 10 50 nsOutput Retaining Time tOH 10 nsRemarks1) READ CYCLE-1 (1) ,~----------------tc-------------~Address(4)1------tHZDout2) READ CYCLE-2(21~----------------tc--------------"""es >= (31es or u

________________________________________ MASKROM·MSM53256RS-Notes: (1) CE" is U L" level.(2) The address is decided at the same time as or ahead 01 CE uLu level.(3) CS are shown in the negative logic here, however the active level is freely selected.(4) teo and tLZ are determined by the later CE "L", OE "L" or CS "L".tHz is determined by the earlier CE uH", OE "H" or CS uH".tHz shows time until floating therefore it is not determined by the output level.INPUT/OUTPUT CAPACITANCE(Ta ~ 25°C, 1 ~ 1 MHz)ParameterSymbolMin.SpecificationValueMax.UnitRemarksInput CapacitanceOutput CapacitanceCICo8 pF6 pFVI~OVVO~OV359

OKI semiconductorMSM531000RS131,072 WORD x 8 BIT MASK ROM (E3-S-031-32lGENERAL DESCRIPTIONThe MSM531000RS is a silicon gate CMOS device ROM with 131,072 words x 8 bit capacity. It operates on a 5Vsingle power supply and all inputs and outputs are TTL compatible. The adoption of an asynchronous system in thecircuit requires no external clock assuring extremely easy operation. The availability of power down mode contributesto the low power dissipation when the chip is not selected. The application of a byte system is most suitablefor use as a large capacity fixed memory for microcomputers and data terminals.Since it provides signals, the connection of output terminals of other chips with the wired OR is possible ensuring aneasy expand operation of memory and bus line control.FEATURES• 131 ,072 words x 8 bits • I nput/output TTL compatible • 28-pin DIP• 5V single power supply• 3-state output• Access time: 250 ns MAXFUNCTIONAL BLOCK DIAGRAMPIN CONFIGURATION~(Top View) A,---0 VeeA,A" 1 28 vocA, --OVssA" 27 A" A,A, 26 A" A,A.•25 A • A,A, 5 2. A, A.A, bufferA, 6 23 A"A.A, 7 22 A"A,A, 8 21 A"CEA"A, 9 20 CEA" ControlA, 10 19 D,A"D,18 D. A""D, 12 17 D, A"D, 13 16 D, A"V""15 D,A"Vee, VssAo.-..;AI3~-D7Power supply voltageAddress inputData outputChip enable360

-------------------------------------.MASKROM·MSM531000RS.ABSOLUTE MAXIMUM RATINGS(Ta = 25°C)RatingPower Supply VoltageI nput VoltageOutput VoltagePower DissipationOperating TemperatureStorage TemperatureSymbolVeeVIVaPDT oprTstgValue Unit Conditions-0.3 to 7 V Respect to V ss-0.3 to Vee + 0.3 V Respect to V ss-0.3 to Vee + 0.3 V Respect to V ss1 W Per packageo to 70 °c --55 to 150 °c -OPERATING CONDITION AND DC CHARACTERISTICSParameter Symbol Measuring ConditionPower Su pply VoltageInput Signal Levelau tput Signal LevelRatingMin. Typ. Max.Vee - 4.5 5 5.5 VVss -0 0 0 VVIH - 2.2 5 Vee +0.3 VVIL --0.3 0 0.8 VVOH 10H = -400/iA 2.4 - - VVOL 10L = 2.1 mA - -Unit0.4 VInput Leakage Current III VI = OV or Vee -10 - 10 /iAOutput Leakage CurrentILOICCAVa = OV or VeeChip not selectedVee = Max. 10 = 0 mA,-10 - 10 /iA- - 15 mAtc = 250 nsPower Supply Current ICCS Vee = Max. CE = Vee - 0.2V - - 0.1 mAICCSlVee = Max.CE = VIH min.- -0.5 mAOperating Temperature Topr - 0 - 70 °cAC CHARACTERISTICSTIMING CONDITIONSParameterConditionsInput Signal Level VIH = 2.4V, VI L = 0.6VInput Rising, Falling Timetr=tf=15 nsInput Voltage=1.5VTiming Measuring Point VoltageOutput Voltage=0.8V & 2.0VLoading ConditionCL =100 pF + 1 TTL361

• MASK ROM· MSM531000RS •• ------------------READ CYCLEParameter(VCC = 5V ±10%, vss = OV, Ta = o°c to +70°C)SymbolSpecification ValueMin. Typ. Max.CyCle Time tc 250 - -Address Access Time tAA - - 250Chip EnableAccess TimetACE - - 250Address Setti ng Time tAS 0 - -Output Setting Time tLZ 10 - -Output Disable Time tHZ 10 - 80Output F'letaining Time tOH 10 - -UnitnsnsnsnsnsnsnsRemarksREAD CYCLEtcAddress-tOH--CENote 1tHZDoutValid DataNote: tHZ shows the time until floating and it is therefore not determined by the output level.362

-----------------____ MASK ROM . MSM531000RS _INPUT/OUTPUT CAPACITANCE(Ta = 25°C. f = 1 MHz)ParameterInput CapacitanceOutput CapacitanceSymbolCICoSpecificationValue Unit RemarksMin. Max.- 8 pF VI=OV.- 6 pF VO=OV363

MOSEPROMS

OKI semiconductorMSM2764AS8192 x 8 BIT UV ERASABLE ELECTRICALLY PROGRAMMABLEREAD-ONLY MEMORYGENERAL DESCRIPTIONThe MSM2764 is a 8192 words x 8 bit ultraviolet erasable and electrically programmable readonlymemory. Users can freely prepare the memory content, which can be easily changed, so theMSM2764 is ideal for microprocessor programs, etc. The MSM2764 is manufactured by the N channeldouble silicon gate MOS technology and is contained in the 28 pin package.FEATURES• +5V single' power supply• 8192 words x 8 bit configuration• Access time:MAX200 ns (MSM2764-20)MAX250 ns (MSM2764-25)MAX300 ns (MSM2764-30)• Power consumption:MAX525 mW (during operation)MAX184 mW (during stand-by)• Perfect static operation• INPUT/OUTPUT TTL level(three state output)FUNCTIONAL BLOCK DIAGRAMPIN CONFIGURATION(Top View)PGMCE---vee-vppDEOE---GNDAoA1 ______ A12This specification may be changed without notification.366

____________________________ ~ __________ ~.EPROM·MSM2764AS.FUNCTION TABLE~eE OE PGM Vpp vee(20) (22) (27) (1 ) (2B)OutputsModeRead VIL VIL VIH +5V +5V DoutOutput Disable VIL VIH VIH +5V +5V High impedanceStand-by VIH - - +5V +5V High impedanceProgram VIL - VIL +21V +6V DINProgram Verify VIL VIL VIH +21V +6V DoutProgram Inhibit VIH - - +21V +6V High impedance-; ean be either VIL or VIHABSOLUTE MAXIMUM RATINGSTemperature Under BiasStorage TemperatureAlllnputlOutput VoltagesVee Supply VoltageProgram VoltagePower Assembly VoltageThe voltage with respect to GND.Ta .........................-1 ooe - BOoeTstg .......................-55°e - 125°eVIN. VOUT ................. -0.6V - 13.5VVee ....................... -0.3V - 7VVpp ....................... -0.6V - 23VPo ........................ 1.5WELECTRICAL CHARACTERISTICSRECOMMENDED OPERATION CONDITIONLimitOperatingParameter Symbol Remarks SymbolMin. Typ. Max.TemperatureVee Power SupplyVoltageVee 4.75 5.0 5.25 VVpp Voltage Vpp 4.15 5.0 5.B5 VVee=5V±O.25Vooe -70oe"H" Level InputVIH 2.00 -Vpp=Vee±0.6VVoltage6.25V"L" Level InputVoltageVIL -0.1 - O.B VThe voltage with respect to GND367

.EPROM·MSM2764AS •• -----------------------------------------DC CHARACTERISTICS(VCC = 5V±5%, Vpp = VCC±0.6V, Ta = O°C -70°C)LimitsParameter Symbol Conditions UnitMin. Typ. Max.Input Leakage Current III VIN =5.25V - - 10 /LAOutput Leakage Current ILO VOUT =5.25V - - 10 /LAVCC Power Current (Stand-by) ICC, CE =VIH - - 35 mAVCC Power Current (Operation) ICC2 CE =VIL - - 100 mAProgram Power Current Ipp, Vpp = VCC±0.6V - - 5 mAInput Voltage "H" Level VIH - 2.0 - VCC+1 VInput Voltage "L" Level VIL - -0.1 - 0.8 VOutput Voltage "H" Level VOH IOH = -400 /LA 2.4 - - VOutput Voltage "L" Level VOL IOL = 2.1 mA - - 0.45 VAC CHARACTERISTICS(VCC = 5V±5%, Vpp = VCC±0.6V, Ta = O°C -70°C)2764-20 2764-25 2764-30Parameter Symbol Conditions UnitMin. Max. Min. Max. Min. Max.Address Access TimetACCCE =OE =VIL,PGM =VIH- 200 - 250 - 300 nsCE Access TimetCEOE =VIL,PGM =VIH- 200 - 250 - 300 nsOE Access TimetOECE =VIL,PGM =VIH- 70 - 100 - 120 nsOutput Disable TimetDFCE =VIL,PGM =VIH0 60 0 85 0 105 nsMeasurement conditionInput pulse level .......................... 0.45V and 2.4VInput timing reference level ............... 0.8V and 2.0VOutput load .............................. 1 TTL GATE + 100pFOutput timing reference level .............. 0.8V and 2.0V368

----------------------------------------____ EPROM·MSM2764AS_TIME CHARTAddress inputCEData output369

.EPROM·MSM2764AS.I----------------------------------------DC CHARACTERISTICS(VCC = 6V±0.25V, Vpp = 21 V±0.5V, Ta = 25°C±5°C)Parameter Symbol ConditionsLimitsMin. Typ. Max.UnitInput Leakage Current III VIN =5.25VVpp Power Current Ipp CE =PGM =VILVCC Power Current ICC -Input Voltage "H" Level VIH -Input Voltage "L" Level VIL -Output Voltage "H" Level VOH IOH = -400 JLAOutput Voltage "L" Level VOL IOL=2.1 mA- - 10 JLA- - 30 mA- - 100 mA2.0 - VCC+1 V-0.1 - 0.8 V2.4 - - V- - 0.45 VAC CHARACTERISTICS(VCC = 6V±0.25V, Vpp = 21 V±0.5V, Ta = 25°C±5°C)Parameter Symbol ConditionsLimitsMin. Typ. Max.UnitAddress Set-up Time tAS -OE Set-up Time tOES -Data Set-up Time tos -Address Hold Time tAH -Data Hold Time tOH -2 - - JLs2 - - JLs2 - - JLs0 - - JLs2 - - JLsOutput Enable to OutputFloat DelaytOFP -0 - 130 nsVpp Power Set-up Time tvs -PGM Initial Program Pulse Width tpw -PGM Overprogram Pulse Width topw -CE Set-up Time tCES -Data Valid from OE tOE -2 - - JLs0.95 1.0 1.05 ms3.8 - 63 ms2 - - JLs- - 150 ns370

------------------------------------------.EPROM·MSM2764AS.TIME CHARTADDRESS NData ---{input/outputVppPGM------,OECAPACITANCE(Ta = 25°C, f = 1 MHz)ParameterInput CapacitanceOutput CapacitanceSymbolCINCOUTConditions Min. Typ. Max. Unit.VIN =OV - 4 6 pFVOUT =OV - 8 12 pF371

OKI semiconductorMSM27128AS16384 x 8 BIT UV ERASABLE ELECTRICALLY PROGRAMMABLEREAD-ONLY MEMORYGENERAL DESCRIPTIONThe MSM27128 is a 16834 words x 8 bit ultraviolet erasable and electrically programmable readonlymemory. Users can freely prepare the memory content, which can be easily changed, so theMSM27128 is ideal for microprocessor programs, etc. The MSM27128 is manufactured by the Nchannel double silicon gate MOS technology and is contained in the 28 pin package.FEATURES• +5V single power supply• 13834 words x 8 bit configuration• Access time:MAX200 ns (MSM27128-20)MAX250 ns (MSM27128-25)MAX300 ns (MSM27128-30)• Power consumption:MAX525 mW (during operation)MAX184 mW (during stand-by)• Perfect static operation• INPUT/OUTPUTTTL level(three state output)FUNCTIONAL BLOCK DIAGRAMPIN CONFIGURATION(Top View)PGMCE+--VCC-vppOeDE-GNDAoAl------A13This specification may be changed without notification.372

______________________________________ _._EPROM·MSM27128AS-FUNCTION TABLE~eE OE PGM Vpp vee(20) (22) (27) (1) (2B)OutputsModeRead VIL VIL VIH +5V +5V DoutOutput Disable VIL VIH VIH +5V +5V High impedanceStand-by VIH - - +5V +5V High impedanceProgram VIL - VIL +21V +6V DINProgram Verify VIL VIL VIH +21V +6V DoutProgram Inhibit VIH - - +21V +6V High impedance-; ean be either VIL or VIHABSOLUTE MAXIMUM RATINGSTemperature Under BiasStorage TemperatureAlllnputlOutput VoltagesVee Supply VoltageProgram VoltagePower Assembly VoltageThe voltage with respect to GND.Ta ......................... -1O o e - BOoeTstg ....................... -55°e - 125°eVIN. VOUT ................. -0.6V - 13.5VVee ....................... -0.3V - 7VVpp ....................... -0.6V - 23VPD ........................ 1.5WELECTRICAL CHARACTERISTICS< READ OPERATION>RECOMMENDED OPERATION CONDITIONLimitOperatingParameter Symbol Remarks SymbolMin. Typ. Max.TemperatureVee Power SupplyVoltageVee 4.75 5.0 5.25 VVppVoltage Vpp 4.75 5.0 5.25 VVee=5V±5%ooe -70oe"H" Level InputVpp=Vee±0.6VVIH 2.00 - 6.25VVoltage"L" Level InputVoltageVIL -0.1 - O.B VThe voltage with respect to GND373

.EPROM·MSM27128AS •• ---------------------------------------DC CHARACTERISTICS(VCC = 5V±5%, Vpp = VCC±0.6V, Ta = O°C -70°C)LimitsParameter Symbol Conditions UnitMin. Typ. Max.Input Leakage Current III VIN =5.25V - - 10 /LAOutput Leakage Current ILO VOUT =5.25V - - 10 /LAVCC Power Current (Stand-by) ICC, CE =VIH - - 35 mAVCC Power Current (Operation) ICC2 CE =VIL - - 100 mAProgram Power Current Ipp, Vpp = VCC±0.6V - - 5 mAInput Voltage "H" Level VIH - 2.0 - VCC+1 VInput Voltage "L" Level VIL - -0.1 - 0.8 VOutput Voltage "H" Level VOH IOH = -400 /LA 2.4 - - VOutput Voltage "L" Level VOL IOL =2.1 mA - - 0.45 VAC CHARACTERISTICS(VCC = 5V±5%, Vpp = VCC±0.6V, Ta = O°C -70°C)27128-20 27128-25 27128-30Parameter Symbol Conditions UnitMin. Max. Min. Max. Min. Max.Address Access TimetACCCE =OE =VIL,PGM =VIH- 200 - 250 - 300 nsCE Access TimetCEOE =VIL,PGM =VIH- 200 - 250 - 300 nsOE Access TimetOECE =VIL,PGM =VIH- 75 - 100 - 120 nsOutput Oisable TimetOFCE =VIL,PGM =VIH0 60 0 60 0 105 nsMeasurement conditionInput pulse level .......................... 0.45V and 2.4VInput timing reference level ............... 0.8V and 2.0VOutputload .............................. 1 TTL GATE + 100pFOutput timing reference level .............. 0.8V and 2.0V374

--------------------------------------___ EPROM·MSM27128AS_TIME CHARTAddress inputData output375

.EPROM·MSM27128AS •• ---------------------------------------DC CHARACTERISTICS(VCC = 6V±0.25V. Vpp = 21 V±0.5V. Ta = 25°C±5°C)LimitsParameter Symbol Conditions UnitMin. Typ. Max.Input Leakage Current III VIN =5.25V - - 10 /LAVpp Power Current Ipp CE=PGM =VIL - - 30 rnAVCC Power Current ICC - - - 100 rnAInput Voltage "H" Level VIH - 2.0 - VCC+1 VInput Voltage "L" Level VIL - -0.1 - 0.8 VOutput Voltage "H" Level VOH IOH = -400 /LA 2.4 - - VOutput Voltage "L" Level VOL IOL =2.1 rnA - - 0.45 VAC CHARACTERISTICS(VCC = 6V±0.25V. Vpp = 21 V±0.5V. Ta = 25°C±5°C)LimitsParameter Symbol Conditions UnitMin. Typ. Max.Address Set-up Time tAS - 2 - - /LsOE Set-up Time tOES - 2 - - /LsData Set-up. Time tDS - 2 - - /LsAddress Hold Time tAH - 0 - - /LsData Hold Time tDH - 2 - - /LsOutput Enable to OutputFloat Delay tDFP - 0 - 130 nsVpp Power Set-up Time tvs - 2 - - /LsPGM Initial Program Pulse Width tpw - 0.95 1.0 1.05 msPGM Overprogram Pulse Width topw - 3.8 - 63 msCE Set-up Time tCES - 2 - - /LsData Valid from OE tOE - - - 150 ns376

--------------------1. EPROM ·MSM27128AS •TIME CHARTADDRESS NData ---

OKI semiconductorMSM27256AS32768 x 8 BIT UV ERASABLE ELECTRICALLY PROGRAMMABLEREAD-ONLY MEMORYGENERAL DESCRIPTIONThe MSM27256 is a 32768 words x 8 bit ultraviolet erasable and electrica"y programmable readonlymemory. Users can freely prepare the memory content, which can be easily changed, so theMSM27256 is ideal for microprocessor programs, etc. The MSM27256 is manufactured by the Nchannel double silicon gate MOS technology and is contained in the 28 pin package.FEATURES• +5V single power supply• 32768 words x 8 bit configuration• Access time:MAX150 ns (MSM27256-15)MAX200 ns (MSM27256-20)MAX250 ns (MSM27256-25)• Power consumption:MAX525 mW (during operation)MAX184 mW (during stand-by)• Perfect static operation• INPUT/OUTPUT TTL level(three state output)FUNCTIONAL BLOCK DIAGRAMPIN CONFIGURATION(Top View)PGMCE-Vcc-Vpp-GNDOEOEAoA1 ______ A14This specification may be changed without notification.378

--------------------1. EPROM· MSM27256AS •FUNCTION TABLE~eE OE Vpp vee(20) (22) (1 ) (28)ModeRead VIL VIL +5V +5V DoutOutputsOutput Disable VIL VIH +5V +5V High impedanceStand-by VIH - +5V +5V High impedanceProgram VIL VIH +12.5V +6V DINProgram Verify litH VIL +12.5V +6V DoutProgram Inhibit VIH VIH +12.5V +6V High impedance-; Can be either VIL or VIHABSOLUTE MAXIMUM RATINGSTemperature Under BiasStorage TemperatureAll Input/Output VoltagesVee Supply VoltageProgram VoltagePower Assembly VoltageThe voltage with respect to GND.Ta ........................ -10o e - 800 eTstg .... . . . . . . . . . . . . . . . . .. -55°e - 1250 eVIN. VOUT .............. " -0.6V - 13.5VVee············· ......... -0.3V -7VVpp ...................... -0.6V - 13.5VPD ....................... 1.5WELECTRICAL CHARACTERISTICSRECOMMENDED OPERATION CONDITIONLimitParameter Symbol OperatingRemarks SymbolMin. Typ. Max.TemperatureVee Power SupplyVoltageVee 4.75 5.0 5.25 VVpp Voltage Vpp 4.75 5.0 5.25 V"H" Level Input aoc -70o e Vee=5V±5%Voltage VIH 2.00 - 6.25Vpp=VeeV"L" Level InputVoltage VIL -0.1 - 0.8 VThe voltage with respect to GND379

.EPROM·MSM27256AS •• ----------------------------------------DC CHARACTERISTICS(VCC = 5V±5%, Vpp = VCC, Ta = O°C -70°C)LimitsParameter Symbol Conditions UnitMin. Typ. Max.Input Leakage Current III VIN =5.25V - - 10 /-lAOutput Leakage Current ILO VOUT =5.25V - - 10 /-lAVCC Power Current (Stand-by) ICC, CE =VIH - - 35 mAVCC Power Current (Operation) ICC2 CE =VIL - - 100 mAProgram Power Current Ipp, Vpp=VCC - - 5 mAInput Voltage "H" Level VIH - 2.0 - VCC+1 VInput Voltage "L" Level VIL - -0.1 - 0.8 VOutput Voltage "H" Level VOH IOH =-400/-lA 2.4 - - VOutput Voltage "L" Level VOL IOL =2.1 mA - - 0.45 VAC CHARACTERISTICS(VCC = 5V±5%, Vpp = VCC, Ta = O°C -70°C)27256-15 27256-20 27256-25Parameter Symbol Conditions UnitMin. Max. Min. Max. Min. Max.Address Access Time tACC CE =OE =VIL - 150 - 200 - 250 nsCE Access Time tCE OE =VIL - 150 - 200 - 250 nsOE Access Time tOE CE =VIL - 70 - 75 - 100 nsOutput Oisable Time tOF CE =VIL 0 50 0 55 0 60 nsMeasurement conditionInput pulse level .......................... 0.45V and 2.4VInput timing reference level ............... 0.8V and 2.0VOutput load .............................. 1 TTL GATE + 100pFOutput timing reference level .............. 0.8V and 2.0V380

----------------------------------------~.EPROM·MSM27256AS.TIME CHARTAddress inputOEData output381

.EPROM·MSM27256AS •• ---------------------------------------DC CHARACTERISTICS(VCC = 6V±0.25V, Vpp = 12.5V±0.5V, Ta = 25°C±5°C)LimitsParameter Symbol Conditions UnitMin. Typ. Max.Input Leakage Current III VIN =5.25V - - 10 JA-AVpp Power Current Ipp CE =VIL,OE =VIH - - 50 rnAVCC Power Current ICC - - - 100 rnAInput Voltage "H" Level VIH - 2.0 - VCC+1 VInput Voltage "L" Level VIL - -0.1 - 0.8 VOutput Voltage "H" Level VOH IOH =-400JA-A 2.4 - - VOutput Voltage "L" Level VOL IOL=2.1 rnA - - 0.45 VAC CHARACTERISTICS(VCC = 6V±0.25V, Vpp = 12.5V±0.5V, Ta = 25°C±5°C)LimitsParameter Symbol Conditions UnitMin. Typ. Max.Address Set-up Time tAS - 2 - - JA-sOE Set-up Time tOES - 2 - - JA-sData Set-up Time tos - 2 - - JA-sAddress Hold Time tAH - 0 - - JA-sData Hold Time tOH - 2 - - JA-sOutput Enable to OutputFloat Delay tOFP - 0 - 130 nsVpp Power Set-up Time tvs - 2 - - JA-sCE Initial Program Pulse Width tpw - 0.95 1.0 1.05 msCE Overprogram Pulse Width topw - 2.85 - 78.75 msData Valid from OE tOE - - - 150 ns382

--------------------------------------___ EPROM·MSM27256AS_TIME CHARTADDRESSNData ---

OKI semiconductorMSM27512AS65536 x 8 BIT UV ERASABLE ELECTRICALLY PROGRAMMABLEREAD-ONLY MEMORYGENERAL DESCRIPTIONThe MSM27512 is a 65536 words x 8 bit ultraviolet erasable and electrically programmable readonlymemory. Users can freely prepare the memory content, which can be easily changed, so theMSM27512 is ideal for microprocessor programs, etc. The MSM27512 is manufactured by the Nchannel double silicon gate MOS technology and is contained in the 28 pin package.FEATURES• +5V single power supply• 65536 words x 8 bit configuration• Access time:MAX150 ns (MSM27512-15)MAX200 ns (MSM27512-20)MAX250 ns (MSM27512-25)• Power consumption:MAX525 mW (during operation)MAX184 mW (during stand-by)• Perfect static operation• INPUT/OUTPUT TTL level(three state output)FUNCTIONAL BLOCK DIAGRAMPIN CONFIGURATION(Top View)PGM-VccCEOE-GNDAoAl ~ _____ A15This specification may be changed without notification.0403384

-----------------------------------------.EPROM·MSM27512AS.FUNCTION TABLEModePinsCE OElVpp VCC(20) (22) (28)OutputsRead VIL VIL +5V DoutOutput Disable VIL VIH +5V High impedanceStand-by VIH - +5V High impedanceProgram VIL Vpp +6V DINProgram Inhibit VIH Vpp +6V High impedance-; Can be either VIL or VIHABSOLUTE MAXIMUM RATINGSTemperature Under BiasStorage TemperatureAlllnputiOutput VoltagesVCC Supply VoltageProgram VoltagePower Assembly VoltageThe voltage with respect to GND.Ta ......................... -10°C - 80°CTstg ....................... -55°C - 125°CVIN. VOUT ................. -0.6V - 13.5VVCC ....................... -0.3V - 7VVpp ....................... -0.6V - 13.5VPD ........................ 1.5WELECTRICAL CHARACTERISTICSRECOMMENDED OPERATION CONDITIONLimitParameter SymbolOperatingRemarks SymbolMin. Typ. Max.TemperatureVCC Power SupplyVoltage VCC 4.75 5.0 5.25 V"H" Level InputVoltage"L" Level InputVoltageVIH 2.00 - 6.25 O°C -70°C VCC=5V±5% VVIL -0.1 - 0.8 VThe voltage with respect to GND385

.EPROM·MSM27512AS •• ----------------------------------------DC CHARACTERISTICS(VCC = 5V±5%, Ta = O°C -70°C)LimitsParameter Symbol Conditions UnitMin. Typ. Max.Input Leakage Current III VIN =5.25V - - 10 J.tAOutput Leakage Current ILO VOUT =5.25V - - 10 J.tAVCC Power Current (Stand-by) ICC, CE =VIH - - 35 rnAVCC Power Current (Operation) ICC2 CE =VIL - - 100 rnAInput Voltage "H" Level VIH - 2.0 - VCC+1 VInput Voltage "L" Level VIL - -0.1 - 0.8 VOutput Voltage "H" Level VOH IOH =-400J.tA 2.4 - - VOutput Voltage "L" Level VOL IOL = 2.1 rnA - - 0.45 VAC CHARACTERISTICS(VCC = 5V±5%, Ta = O°C -70°C)27512-15 27512-20 27512-25Parameter Symbol Conditions UnitMin. Max. Min. Max. Min. Max.Address Access TimetACCCE =OElVpp =VIL- 150 - 200 - 250 nsCE Access Time tCE OElVpp =VIL - 150 - 200 - 250 nsOE Access Time tOE CE =VIL - 70 - 75 - 100 nsOutput Disable Time tDF CE =VIL 0 50 0 55 0 60 nsMeasurement conditionInput pulse level .......................... 0.45Vand 2.4VInput timing reference level ............... 0.8V and 2.0VOutput load .............................. HTL GATE + 100pFOutput timing reference level .............. 0.8V and 2.0VTIME CHARTAddress inputData output386

_________________________________________ I.EPROM·MSM27512AS.DC CHARACTERISTICS(VCC = 6V±S%, Vpp = 12.5V±0.SV, Ta = 2S 0 C±SOC)LimitsParameter Symbol Conditions UnitMin. Typ. Max.Input Leakage Current III VIN =5.25V - - 10 p.AVpp Power Current Ipp CE =VIL - - 50 mAVCC Power Current ICC - - - 100 mAInput Voltage "H" Level VIH - 2.0 - VCC+1 VInput Voltage "L" Level VIL - -0.1 - 0.8 VOutput Voltage "H" Level VOH IOH = -400 p.A 2.4 - - VOutput Voltage "L" Level VOL IOL = 2.1 mA - - 0.45 VAC CHARACTERISTICS(VCC = 6V±0.25V, Vpp = 12.5V±0.5V, Ta = 25°C±5°C)LimitsParameter Symbol Conditions UnitMin. Typ. Max.Address Set-up Time tAS - 2 - - p'sData Set-up Time tDS - 2 - - p'sAddress Hold Time tAH - 0 - - p'sData Hold Time tDH - 2 - - p'sCE Enable to OutputFloat DelaytDFP - 0 - 130 nsVpp Power Set-up Time tvs - 2 - - p's-CE Initial Program Pulse Width tpw - 0.95 1.0 1.05 msCE Overprogram Pulse Width topw - 2.85 - 78.75 msOElVpp Hold Time tOEH - 2 - - p'sData Valid from CE tDV - - - 1 p'sOElVpp Recovery Time tVR - 2 - - p's387

.EPROM·MSM27512AS.--------~------------------------------TIME CHARTAddressinputADDRESS NDatainput/outputOElVppCEtpwtopwCAPACITANCE(Ta = 25°C, f = 1 MHz)ParameterInput CapacitanceOutput CapacitanceSymbolCINCOUTConditions Min. Typ. Max. Unit.VIN =OV - 4 6 pFVOUT =OV - 8 12 pF388

OKI semiconductor ~~---------------------------------------------------------------------~~~MSM271000AS131072 x 8 BIT UV ERASABLE ELECTRICALLY PROGRAMMABLEREAD-ONLY MEMORYGENERAL DESCRIPTIONThe MSM271 000 is a 131072 words x 8 bit ultraviolet erasable and electrically programmableread-only memory. Users can freely prepare the memory content, which can be easily changed, sothe MSM271 000 is ideal for microprocessor programs, etc. The MSM271 000 is manufactured by theN channel double silicon gate MOS technology and is contained in the 32 pin package.FEATURES• +5V single power supply• 131072 words x 8 bit configuration• Access time:MAX120 ns (MSM271 000-12)MAX150 ns (MSM271 000-15)MAX200 ns (MSM271 000-20)• Power consumption:MAX525 mW (during operation)MAX184 mW (during stand-by)• Perfect static operation• INPUT/OUTPUTTTLlevel(three state output)PIN CONFIGURATIONFUNCTIONAL BLOCK DIAGRAMA" NC000, 0,A'3AsAe+---VccA11PGMOEA2 AlO CEPGMCE+---Vpp~A, CEAo 0,06OEOE""""--GNOAoA, - - - -- A16ThiS specification may be changed without notification389

.EPROM·MSM271000AS •.--------------------------------------FUNCTION TABLEModePinseE OE PGM Vpp Vee(22) (24) (31) (1 ) (32) OutputsRead VIL VIL VIH +5V +5V DoutOutput Disable VIL VIH VIH +5V +5V High impedanceStand-by VIH - - +5V +5V High impedanceProgram VIL - VIL +12.5V +6V DINProgram Verify VIL VIL VIH +12.5V +6V DoutProgram Inhibit VIH - - +12.5V +6V High impedance-; ean beeitherVILorVIHABSOLUTE MAXIMUM RATINGSTemperature Under BiasStorage TemperatureAll Input/Output VoltagesVee Supply VoltageProgram VoltagePower Assembly VoltageThe voltage with respect to GND.Ta .........................-1 oDe - 80DeTstg .......................-55De - 125DeVIN. VOUT ................. -0.6V -13VVee ....................... -0.3V - 7VVpp ....................... -0.6V -13.5VPo ........................ 1.5WELECTRICAL CHARACTERISTICSRECOMMENDED OPERATION CONDITIONLimitParameter SymbolOperatingRemarksMin. Typ. Max.TemperatureSymbolVee Power SupplyVoltageVee 4.75 5.0 5.25VVpp Voltage Vpp 4.75 5.0 5.25"H" Level InputVoltage VIH 2.00 - 6.25oDe -70DeVee=5V±0.25VVpp=VeeVV"L" Level InputVoltageVIL -0.1 - 0.8VThe voltage with respect to GND390

--------------------------------------____ EPROM·MSM271000AS_DC CHARACTERISTICS(VCC = 5V±5%, Vpp = VCC, Ta = ovc - 70°C)LimitsParameter Symbol Conditions UnitMin. Typ. Max.Input Leakage Current III VIN =5.25V - - 10 /LAOutput Leakage Current ILO VOUT =5.25V - - 10 /LAVCC Power Current (Stand-by) ICC, CE =VIH - - 35 rnAVCC Power Current (Operation) ICC2 CE =VIL - - 100 rnAProgram Power Current Ipp, Vpp=VCC - - 5 rnAInput Voltage "H" Level VIH - 2.0 - VCC+1 VInput Voltage "L" Level VIL - -0.1 - 0.8 VOutput Voltage "H" Level VOH IOH = -400 /LA 2.4 - - VOutput Voltage "L" Level VOL IOL = 2.1 rnA - - 0.45 VAC CHARACTERISTICS(VCC = 5V±5%, Vpp = VCC, Ta = O°C -70°C)271000-12 271000-15 271000-20Parameter Symbol Conditions UnitMin. Max. Min. Max. Min. Max.Address Access TimetACCCE =OE =VIL,PGM =VIH- 120 - 150 - 200 nsCE Access TimetCEOE =VIL,PGM =VIH- 120 - 150 - 200 nsOE Access TimetOECE =VIL,i5GM =VIH- 50 - 60 - 75 nsOutput Oisable TimetOFCE =VIL,PGM =VIH0 40 0 50 0 55 nsMeasurement conditionInput pulse level .......................... 0.45V and 2.4VInput timing reference level ............... 0.8V and 2.0VOutput load .............................. 1 TTL GATE + 100pFOutput timing reference level .............. 0.8V and 2.0V391

.EPROM·MSM271000AS •• -------------------------------------­TIME CHARTAddress inputData output392

--------------------------------------____ EPROM·MSM271000AS_DC CHARACTERISTICS(VCC = 6V±0.25V, Vpp = 12.5V±0.5V, Ta = 25°C±5°C)Parameter Symbol ConditionsLimitsMin. Typ. Max.UnitInput Leakage Current III VIN =5.25VVpp Power Current Ipp CE = PGM =VILVCC Power Current ICC -Input Voltage "H" Level VIH -Input Voltage "L" Level VIL -Output Voltage "H" Level VOH IOH = -400 p.AOutput Voltage "L" Level VOL IOL =2.1 mA- - 10 p.A- - 50 mA- - 100 mA2.0 - VCC+1 V-0.1 - 0.8 V2.4 - - V- - 0.45 VAC CHARACTERISTICS(VCC = 6V±0.25V, Vpp = 12.5V±0.5V, Ta = 25°C±5°C)Parameter Symbol ConditionsLimitsMin. Typ. Max.UnitAddress Set-up Time tAS --OE Set-up Time tOES -Data Set-up Time tos -Address Hold Time tAH -Data Hold Time tOH -2 - - p's2 - - p's2 - - p's0 - - p's2 - - p'sOutput Enable to OutputFloat DelaytOFP -0 - 130 nsVpp Power Set-up Time tvs -PGM Initial Program Pulse Width tpw -PGM Overprogram Pulse Width topw -CE Set-up Time tCES -Data Valid from OE tOE -2 - - p's0.95 1.0 1.05 ms2.85 - 78.75 ms2 - - p's- - 150 ns393

.EPROM·MSM271000AS •• --------------------------------------TIME CHARTADDRESSNData ----

OKI semiconductorMSM271024AS65536 x 16 BIT UV ERASABLE ELECTRICALLY PROGRAMMABLEREAD-ONLY MEMORYGENERAL DESCRIPTIONThe MSM271024 is a 65536 words x 16 bit ultraviolet erasable and electrically programmableread-only memory. Users can freely prepare the memory content, which can be easily changed, sothe MSM271 024 is ideal for microprocessor programs, etc. The MSM271 024 is manufactured by theN channel double silicon gate MOS technology and is contained in the 40 pin package.FEATURES• +5V single power supply• 65536 words x 16 bit configuration• Access time:MAX120 ns (MSM271 024-12)MAX150 ns (MSM271 024-15)MAX200 ns (MSM271 024-20)• Power consumption:MAX525 mW (during operation)MAX184 mW (during stand-by)• Perfect static operation• INPUT/OUTPUT TTL level(three state output)PIN CONFIGURATIONFUNCTIONAL BLOCK DIAGRAMNCA14A13A"AllAlOo. A,VssVssA.PGMCEPGMCE...-----..- Vee4------ Vpp...-----GNDA,OfOEThis specificatIOn may be changed without nOTification395

.EPROM·MSM271024AS.--------------------------------------FUNCTION TABLEModePinseE OE PGM Vpp Vee(2) (20) (39) (1 ) (40)OutputsRead VIL VIL VIH +5V +5V DoutOutput Disable VIL VIH VIH +5V +5V High impedanceStand-by VIH - - +5V +5V High impedanceProgram VIL - VIL +12.5V +6V DINProgram Verify VIL VIL VIH +12.5V +6V DoutProgram Inhibit VIH - - +12.5V +6V High impedance-; ean be either VIL or VIHABSOLUTE MAXIMUM RATINGSTemperature Under BiasStorage TemperatureAlllnputiOutput VoltagesVee Supply VoltageProgram VoltagePower Assembly VoltageThe voltage with respect to GND.Ta ......................... -10°C - BOoeTstg ....................... -55°C - 125°eVIN, VOUT ................. -0.6V - 13VVee ....................... -0.3V - 7VVpp ....................... -0.6V - 13.5VPD ........................ 1.5WELECTRICAL CHARACTERISTICSRECOMMENDED OPERATION CONDITIONParameterSymbolMin.LimitTyp.Max.OperatingTemperatureRemarksSymbolVee Power SupplyVoltageVee 4.75 5.05.25VVpp Voltage Vpp 4.75 5.0"H" Level InputVoltage VIH 2.00 -5.256.25ooe -70oeVee=5V±0.25VVpp=VceVV"L" Level InputVoltageVIL -0.1 -0.8VThe voltage with respect to GND396

----------------------------------------.EPROM·MSM271024AS.DC CHARACTERISTICS(VCC = 5V±5%. Vpp = VCC. Ta = O°C -70°C)LimitsParameter Symbol Conditions UnitMin. Typ. Max.Input Leakage Current III VIN =5..25V - - 10 /LAOutput Leakage Current ILO VOUT =5.25V - - 10 /LAVCC Power Current (Stand-by) ICC, CE =VIH - - 35 rnAVCC Power Current (Operation) ICC2 CE =VIL - - 100 rnAProgram Power Current Ipp, Vpp =VCC - - 5 rnAInput Voltage "H" Level VIH - 2.0 - VCC+1 VInput Voltage "L" Level VIL - -0.1 - 0.8 VOutput Voltage "H" Level VOH IOH = -400 /LA 2.4 - - VOutput Voltage "L" Level VOL IOL =2.1 rnA - - 0.45 VAC CHARACTERISTICS(VCC = 5V±5%. Vpp = VCC. Ta = O°C -70°C)271024-12 271024-15 271024-20Parameter Symbol Conditions UnitMin. Max. Min. Max. Min. Max.Address Access TimetACCCE =OE =VIL.PGM =VIH- 120 - 150 - 200 nsCE Access TimetCEOE =VIL.PGM =VIH- 120- 150 - 200 nsOE Access TimetOECE =VIL.PGM =VIH- 50- 60 - 75 nsOutput Disable TimetDFCE =VIL.PGM =VIH0 40 0 50 0 55 nsMeasurement conditionInput pulse level .......................... 0.45V and 2.4VInput timing reference level ............... 0.8V and 2.0VOutput load .............................. 1TTL GATE + 100pFOutput timing reference level .............. 0.8V and 2.0V397

.EPROM·MSM271024AS.I---------------------------------------­TIME CHARTAddress inputCEData output398

--------------------------------------•• EPROM·MSM271024AS.< PROGRAMMING OPERATION>DC CHARACTERISTICS(VCC = 6V±0.25V, Vpp = 12.5V±0.5V, Ta = 25°C±5°C)Parameter Symbol ConditionsLimitsMin. Typ. Max.UnitInput Leakage Current III VIN =5.25VVpp Power Current Ipp CE =PGM =VILVCC Power Current ICC -Input Voltage "H" Level VIH -Input Voltage "L" Level VIL -Output Voltage "H" Level VOH IOH = -400 p.AOutput Voltage "L" Level VOL IOL=2.1 mA- - 10 p.A- - 50 mA- - 100 mA2.0 - Vce+1 V-0.1 - 0.8 V2.4 - - V- - 0.45 VAC CHARACTERISTICS(Vee = 6V±0.25V, Vpp = 12.5V±0.5V, Ta = 25°C±5°C)Parameter Symbol ConditionsLimitsMin. Typ. Max.UnitAddress Set-up Time tAS -OE Set-up Time tOES -Data Set-up Time tos -Address Hold Time tAH -Data Hold Time tOH -2 - - p's2 - - p's2 - - p's0 - - p's2 - - p'sOutput Enable to OutputFloat DelaytOFP -0 - 130 nsVpp Power Set-up Time tvs -PGM Initial Program Pulse Width tpw -PGM Overprogram Pulse Width topw -CE Set-up Time tCES -Data Valid from OE tOE -2 - - p's0.95 1.0 1.05 ms2.85 - 78.75 ms2 - - p's- - 150 ns399

.EPROM·MSM271024AS •• ----------------------------------------TIME CHARTADDRESSNData -----

g~~-------------~,semiconductor MSM27C64AS8192 x 8 BIT UV ERASABLE ELECTRICALLY PROGRAMMABLEREAD-ONLY MEMORYGENERAL DESCRIPTIONThe MSM27C64 is a 8192 words x 8 bit ultraviolet erasable and electrically programmable readonlymemory. Users can freely prepare the memory content, which can be easily changed, so theMSM27C64 is ideal for microprocessor programs, etc. The MSM27C64 is manufactured by theCMOS double silicon gate technology and is contained in the 28 pin package.FEATURES• +5V single power supply• 8192 words x 8 bit configuration• Access time:MAX200 ns (MSM27C64-20)MAX250 ns (MSM27C64-25)MAX300 ns (MSM27C64-30)• Power consumption:MAX165 mW (during operation)MAXO.55 mW (during stand-by)• Perfect static operation• INPUT/OUTPUT TTL level(three state output)FUNCTIONAL BLOCK DIAGRAMPIN CONFIGURATION(Top View)PGMCE-Vcc-Vpp-GNDDEDEThis specification may be changed without notification.401

.EPROM·MSM27C64AS •• ----------------------------------------FUNCTION TABLE~eE OE PGM vpp vee(20) (22) (27) (1) Outputs(2B)ModeRead VIL VIL VIH +5V +5V DoutOutput Disable VIL VIH VIH +5V +5V High impedanceStand-by VIH - - +5V +5V High impedanceProgram VIL - VIL +21V +6V DINProgram Verify VIL VIL VIH +21V +6V DoutProgram Inhibit VIH - - +21V +6V High impedance-; ean be either VIL or VIHABSOLUTE MAXIMUM RATINGSTemperature Under BiasStorage TemperatureAlllnputiOutput VoltagesVee Supply VoltageProgram VoltagePower Assembly VoltageThe voltage with respect to GND.Ta ......................... -1 ooe - BOoeTstg .......................-55°e - 125°eVIN, VOUT ................. VIN = -0.6V - 13.5V,VOUT = -0.3V - Vee + 1 VVee ....................... -0.3V -7VVpp ....................... -0.6V - 23VPD ........................ 1.5WELECTRICAL CHARACTERISTICSRECOMMENDED OPERATION CONDITIONLimitParameter SymbolOperatingRemarksMin. Typ. Max.TemperatureSymbolVee Power SupplyVoltageVee 4.5 5.0 5.5VVpp Voltage Vpp 3.B 5.0 6.2"H" Level InputVoltageVIH 2.00 - 6.5ooe -70oeVee=5V±10%Vpp=Vee±0.7VVV"L" Level InputVoltageVIL -0.1 - 0.8VThe voltage with respecllo GND402

----------------------------------------~.EPROM·MSM27C64AS.DC CHARACTERISTICS(VCC = 5V±1 0%, Vpp = VCC±0.7V, Ta = O°C -70°C)LimitsParameter Symbol Conditions UnitMin. Typ. Max.Input Leakage Current III VIN =5.5V - - 10 JLAOutput Leakage Current ILO VOUT=5.5V - - 10 JLAVCC Power Current (Stand-by) ICC, CE =VIH =VCC - - 100 JLAVCC Power Current (Operation) ICC2-CE =VIL - - 30 rnAVpp Power Current Ipp, Vpp = VCC±0.7V - - 100 JLAInput Voltage "H" Level VIH - 2.0 - VCC+1 VInput Voltage "L" Level VIL - -0.1 - 0.8 VOutput Voltage "H" Level VOH IOH = -400 JLA 4.0 - - VOutput Voltage "L" Level VOL IOL = 2.1 rnA - - 0.45 VAC CHARACTERISTICS(VCC =5V±10%, Vpp =VCC±0.7V, Ta =O°C -70°C)27C64-20 27C64-25 27C64-30Parameter Symbol Conditions UnitMin. Max. Min. Max. Min. Max.Address Access TimetACCCE =OE =VIL,PGM =VIH- 200 - 250 - 300 nsCE Access TimetCEOE =VIL,PGM =VIH- 200 - 250 - 300 nsOE Access TimetOECE =VIL,PGM =VIH- 75 - 100 - 120 nsOutput Disable TimetDFCE =VIL,PGM =VIH0 60 0 85 0 105 nsMeasurement conditionInput pulse level .......................... 0.45V and 2.4VInput timing reference level ............... 0.8V and 2.0VOutput load .............................. 1 TTL GATE + 100pFOutput timing reference level .............. 0.8V and 2.0V403

_EPROM·MSM27C64AS ___ ---------------------------------------TIME CHARTAddress inputData output404

----------------------------------------~.EPROM·MSM27C64AS.DC CHARACTERISTICS(VCC = 6V±0.25V, Vpp = 21 V±0.5V, Ta = 25°C±5°C)LimitsParameter Symbol Conditions UnitMin. Typ. Max.Input Leakage Current III VIN =5.5V - - 10 /LAVpp Power Current Ipp CE =PGM =VIL - - 30 mAVCC Power Current ICC - - - 30 mAInput Voltage "H" Level VIH - 2.0 - VCC+1 VInput Voltage "L" Level VIL - -0.1 - 0.8 VOutput Voltage "H" Level VOH IOH = -400 /LA 2.4 - - VOutput Voltage "L" Level VOL IOL =2.1 mA - - 0.45 VAC CHARACTERISTICS(VCC = 6V±0.25V, Vpp = 21 V±0.5V, Ta = 25°C±5°C)LimitsParameter Symbol Conditions UnitMin. Typ. Max.Address Set-up Time tAS - 2 - - /LSOE Set-up Time tOES - 2 - - /LsData Set-up Time tDS - 2 - - /LsAddress Hold Time tAH - 0 - - /LsData Hold Time tDH - 2 - - /LsOutput Enable to OutputFloat Delay tDFP - 0 - 130 nsVpp Power Set-up Time tvs - 2 - - /LsPGM Initial Program Pulse Width tpw - 0.95 1.0 1.05 msPGM Overprogram Pulse Width topw - 3.8 - 63 msCE Set-up Time tCES - 2 - - /LsData Valid from OE tOE - - - 150 ns405

_EPROM·MSM27C64AS_._--------------------------------------TIME CHARTADDRESSNData -----

~OKI semiconductorC\I~~---------------------------------------------------------------------- ~~MSM27C1 28AS16384 x 8 BIT UV ERASABLE ELECTRICALLY PROGRAMMABLEREAD-ONLY MEMORYGENERAL DESCRIPTIONThe MSM27C128 is a 16384 words x 8 bit ultraviolet erasable and electrically programmableread-only memory. Users can freely prepare the memory content, which can be easily changed, sothe MSM27C128 is ideal for microprocessor programs, etc. The MSM27C128 is manufactured bythe CMOS double silicon gate technology and is contained in the 28 pin package.FEATURES• +5V single power supply• 16384 words x 8 bit configuration• Access time:MAX200 ns (MSM27C128-20)MAX250 ns (MSM27C128-25)MAX300 ns (MSM27C128-30)• Power consumption:MAX165 mW (during operation)MAXO.55 mW (during stand-by)• Perfect static operation• INPUT/OUTPUT TTL level(three state output)FUNCTIONAL BLOCK DIAGRAMPIN CONFIGURATION(Top View)-VCCPGM-VppCE-GNDOEOEAoA, ______ A13This specification may be changed without notification.407

.EPROM·MSM27C128AS .--------------------------------------•FUNCTION TABLE~CE 01; PGM Vpp VCC(20) (22) (27) (1) (28)OutputsModeRead VIL VIL VIH +5V +5V DoutOutput Disable VIL VIH VIH +5V +5V High impedanceStand-bY VIH - - +5V +5V High impedanceProgram VIL - VIL +21V +6V DINProgram Verify VIL VIL VIH +21V +6V DoutProgram Inhibit VIH - - +21V +6V High impedance-; Can be either VIL or VIHABSOLUTE MAXIMUM RATINGSTemperature Under BiasStorage TemperatureAlllnputiOutput VoltagesVCC Supply VoltageProgram VoltagePower Assembly VoltageThe voltage with respect to GND.Ta ......................... -10°C - 80°CTstg ....................... -55°C - 125°CVIN, VOUT ................. VIN = -0.6V - 13.5V,VOUT = -0.3V - VCC + 1 VVCC ....................... -0.3V - 7VVpp ....................... -0.6V - 23VPo ........................ 1.5WELECTRICAL CHARACTERISTICSRECOMMENDED OPERATION CONDITIONLimitOperatingParameter Symbol RemarksMin. Typ. Max.TemperatureSymbolVCC Power SupplyVoltageVCC 4.5 5.0 5.5VVpp Voltage Vpp 3.8 5.0 6.2"H" Level InputVoltageVIH 2.00 - 6.5O°C -70°CVCC=5V±10%Vpp=V CC±O. 7VVV"L" Level InputVoltageVIL -0.1 - 0.8VThe voltage with respect to GND408

-------------------......... _ EPROM 'MSM27C128AS _DC CHARACTERISTICS(VCC = 5V±1 0%, Vpp = VCC±0.7V, Ta = O°C -70°C)LimitsParameter Symbol Conditions UnitMin. Typ. Max.Input Leakage Current III VIN =5.5V - - 10 !LAOutput Leakage Current ILO VOUT=5.5V - - 10 !LAVCC Power Current (Stand-by) ICCl CE =VIH =VCC - - 100 !LAVCC Power Current (Operation) ICC2 CE=VIL - - 30 mAVpp Power Current IPPl Vpp =VCC±0.7V - - 100 !LAInput Voltage "H" Level VIH - 2.0 - Vce+1 VInput Voltage "L" Level VIL - -0.1 - 0.8 VOutput Voltage "H" Level VOH IOH = -400 !LA 4.0 - - VOutput Voltage "L" Level VOL IOL =2.1 mA - - 0.45 VAC CHARACTERISTICS(Vec = 5V±1 0%, Vpp = Vce±0.7V, Ta = ooe -70°C)27C128-20 27C128-25 27C128-30Parameter Symbol ConditionsMin. Max. Min. Max. Min. Max.UnitAddress Access TimetACCCE =OE =VIL,PGM =VIH- 200 - 250 - 300 nsCE Access TimetCEOE=VIL,PGM =VIH- 200 - 250 - 300 nsOE Access TimetOECE =VIL,PGM =VIH- 75 - 100 - 120 nsOutput Disable TimetDFCE =VIL,PGM =VIH0 60 0 85 0 105 nsMeasurement conditionInput pulse level .......................... 0.45V and 2.4VInput timing reference level ............... 0.8V and 2.0VOutput load .............................. 1 TTL GATE + 100pFOutput timing reference level .............. 0.8V and 2.0V409

.EPROM·MSM27C128AS.I-------------------------------------­TIME CHARTAddress inputCEData output410

--------------------------------------I.EPROM·MSM27C128AS.DC CHARACTERISTICS(VCC = 6V±0.25V, Vpp = 21 V±0.5V, Ta = 25°C±5°C)LimitsParameter Symbol Conditions UnitMin. Typ. Max.Input Leakage Current III VIN =5.5V - - 10 p.AVpp Power Current Ipp CE = PGM =VIL - - 30 mAVCC Power Current ICC - - - 30 mAInput Voltage "H" Level VIH - 2.0 - VCC+1 VInput Voltage "L" Level VIL - -0.1 - 0.8 VOutput Voltage "H" Level VOH IOH = -400 p.A 2.4 - - VOutput Voltage "L" Level VOL IOL =2.1 mA - - 0.45 VAC CHARACTERISTICS(VCC = 6V±0.25V, Vpp = 21 V±0.5V, Ta = 25°C±5°C)LimitsParameter Symbol Conditions UnitMin. Typ. Max.Address Set-up Time tAS - 2 - - p'sOE Set-up Time tOES - 2 - - p'sData Set-up Time tDS - 2 - - p'sAddress Hold Time tAH - 0 - - p'sData Hold Time tDH - 2 - - p'sOutput Enable to OutputFloat DelaytDFP -0 - 130 nsVpp Power Set-up Time tvs - 2 - - p'sPGM Initial Program Pulse Width tpw - 0.95 1.0 1.05 msPGM Overprogram Pulse Width topw - 3.8 - 63 msCE Set-up Time tCES - 2 - - p'sData Valid from OE tOE - - - 150 ns411

.EPROM·MSM27C128AS •• ---------------------------------------TIME CHARTADDRESS NData ---

._D_._K __ I __MSM27C1024ASse_ITI_I_c_O_ncl_u_c_.or ______ ~65536 x 16 BIT UV ERASABLE ELECTRICALLY PROGRAMMABLEREAD-ONLY MEMORYGENERAL DESCRIPTIONThe MSM27C1 024 is a 65536 words x 16 bit ultraviolet erasable and electrically programmableread-only memory. Users can freely prepare the memory content, which can be easily changed, sothe MSM27C1 024 is ideal for microprocessor programs, etc. The MSM27C 1024 is manufactured bythe CMOS double silicon gate technology and is contained in the 40 pin package.FEATURES• +5V single power supply• 65536 words x 1 6 bit configuration• Access time:MAX1 00 ns (MSM27C1 024-1 0)MAX150 ns (MSM27C1 024-15)MAX200 ns (MSM27C1 024-20)• Power consumption:MAX175 mW (during operation)MAXO.55 mW (during stand-by)• Perfect static operation• INPUT/OUTPUT TTL level(three state output)PIN CONFIGURATIONFUNCTIONAL BLOCK DIAGRAM4----- VeePGMCE+-----------GNODEOEThis specification may be changed without notification.413

_EPROM·MSM27C1024AS ___ -------------------------------------FUNCTION TABLE~eE OE PGM Vpp vee(2) (20) (39) (1) (40) OutputsModeRead VIL VIL VIH +5V +5V DoutOutput Disable VIL VIH VIH +5V +5V High impedanceStand-by VIH - - +5V +5V High impedanceProgram VIL - VIL +J2.5V +6V DINProgram Verify VIL VIL VIH +12.5V +6V DoutProgram Inhibit VIH - - +12.5V +6V High impedance-; ean be either VIL or VIHABSOLUTE MAXIMUM RATINGSTemperature Under BiasStorage TemperatureAlllnputiOutput VoltagesVee Supply VoltageProgram VoltagePower Assembly VoltageThe voltage with respect to GND.Ta ......................... -1 ooe - BOoeTstg ....................... -55°e - 125°eVIN, VOUT ................. VIN = -0.6V - 13V,VOUT = -0.3V - Vee + 1 VVee· ...................... -0.3V - 7VVpp ....................... -0.6V - 13.5VPD ........................ 1.5WELECTRICAL CHARACTERISTICSRECOMMENDED OPERATION CONDITIONLimitParameter SymbolOperatingRemarksMin. Typ. Max.TemperatureSymbolVee Power SupplyVoltageVee 4.5 5.0 5.5VVpp Voltage Vpp 4.5 5.0 5.5"H" Level InputVoltage VIH 2.00 - 6.5ooe -70oeVee=5V±0.5VVpp=VeeVV"L" Level InputVoltageVIL -0.1 - O.BVThe voltage with respect to GND414

---------------------------------------.EPROM·MSM27C1024AS.DC CHARACTERISTICS(VCC = 5V±1 0%. Vpp = VCC. Ta = O°C -70°C)LimitsParameter Symbol Conditions UnitMin. Typ. Max.Input Leakage Current III VIN =5.25V - - 10 J-tAOutput Leakage Current ILO VOUT =5.25V - - 10 J-tAVCC Power Current (Stand-by) ICCl CE =VIH =VCC - - 50 J-tVCC Power Current (Operation) ICC2 CE =VIL - - 30 mAProgram Power Current IPPl Vpp =VCC - - 50 J-tInput Voltage "H" Level VIH - 2.0 - VCC+1 VInput Voltage "L" Level VIL - -0.1 - 0.8 VOutput Voltage "H" Level VOH IOH =-400J-tA 2.4 - - VOutput Voltage "L" Level VOL IOL = 2.1 mA - - 0.45 VAC CHARACTERISTICS(VCC = 5V±1 0%. Vpp = VCC. Ta = O°C -70°C)Parameter Symbol Conditions27C1000- 27C1000- 27C1000-10 15 20Min. Max. Min. Max. Min. Max.UnitAddress Access TimetACCCE =OE =VIL.PGM =VIH- 100 - 150 - 200 ns- OE =VIL.CE Access Time tCEPGM =VIH- 100 - 150 - 200 nsOE Access TimetOECE = VIL.PGM =VIH- 45 - 60 - 75 nsOutput Disable TimetDFCE =VIL.PGM =VIH0 35 0 50 0 55 nsMeasurement conditionInput pulse level .......................... 0.45V and 2.4VInput timing reference level ............... O.BV and 2.0VOutput load .............................. 1 TTL GATE + 100pFOutput timing reference level .............. O.BV and 2.0V415

.EPROM·MSM27C1024AS.------------------------------------­TIME CHARTAddress inputData output416

---------------------------------------I.EPROM·MSM27C1024AS.DC CHARACTERISTICS(VCC = 6V±0.25V, Vpp = 12.5V±0.5V, Ta = 25°C±5°C)LimitsParameter Symbol Conditions UnitMin. Typ. Max.Input Leakage Current III VIN =5.25V - - 10 p.AVpp Power Current Ipp CE =PGM =VIL - - 50 mAVCC Power Current ICC - - - 30 mAInput Voltage "H" Level VIH - 2.0 - VCC+1 VInput Voltage "L" Level VIL - -0.1 - 0.8 VOutput Voltage "H" Level VOH IOH =-400p.A 2.4 - - VOutput Voltage "L" Level VOL IOL = 2.1 mA - - 0.45 VAC CHARACTERISTICS(VCC = 6V±0.25V, Vpp = 12.5V±0.5V, Ta = 25°C±5°C)LimitsParameter Symbol Conditions UnitMin. Typ. Max.Address Set-up Time tAS - 2 - - p'sOE Set-up Time tOES - 2 - - p'sData Set-up Time tDS - 2 - - p'sAddress Hold Time tAH - 0 - - p'sData Hold Time tDH - 2 - - p'sOutput Enable to OutputFloat DelaytDFP - 0 - 130 nsVpp Power Set-up Time tvs - 2 - - p'sPGM Initial Program Pulse Width tpw - 0.95 1.0 1.05 msPGM Overprogram Pulse Width topw - 2.85 - 78.75 msCE Set-up Time tCES - 2 - - p'sData Valid from OE tOE - - - 150 ns417

_EPROM·MSM27C1024AS-.-------------------------------------TIME CHARTADDRESSNData ---

MOSE 2 ROMS

OKI semiconductorMSM2816ARS2K x 8 BIT ELECTRICALLY ERASABLE PROMGENERAL DESCRIPTIONThe MSM2816A is a 2,048 word x 8 bit electrically erasable programmable read·only memory (E' PROM). TheMSM2816A operates from a single 5V power supply, has a static standby mode, and features easiest programming.Though the MSM2816A requires no high voltage during reading or writing, it is still operable in the high·voltage modeas well.The process of updating byte data in the 5V programming mode is initiated by setting the write signal at the TTL low(L) level for 200 ns. Address and data bus information is latched within the Ie, and the system is made available toother tasks during the write cycle.The MSM2816A erases a selected byte automatically before writing new information to it. The erase/write cyclecompletes within a maximum period of 10 ms. In addition to the byte erase/write function, the MSM2816A supportsa mode permitting the entire chip to be cleared at 10 ms or less.The MSM2816A is ideally suited for applications involving the use of a nonvolatile memory to make modificationsto a system. Typical applications include self·controllable equipments, memorizing ratio of tariffs at terminals on thesales counter, storing keywords' for encoding data, programmable character generators, and storing map informationin air navigation systems.FEATURES• Single 5V power supply• High·speed access time.250 ns MAX.300 ns MAX.350 ns MAX.450 ns MAX.• TTL level byte write. . . . . . . . . .. 10 ms MAX.• Internally latched address data during write• Automatic erase before write• Automatic completion of write• Inadvertent write protection• Input and output TTL compatible• JEDEe·compliance pin configuration• Pin compatible to Xicor 2816A, Intel 2816/2816APIN CONFIGURATION (Top View)DA, vee Pin names FunctionA, A,A,Ao 'V A IO Address i npu ts1/° 0 'V 1/07 Data inputs/outputsDEA"CE"Chip enableCE DE Output enableA, lID,1100 1/06WEWrite enable1/0 1 1/°5 Vee +5V1/°2 1/04vss 12 13 II0aVSSGround420

---------------------------------------I.EEPROM·MSM2816ARS.FUNCTIONAL BLOCK DIAGRAMx buffers,latch anddecoder16,384 bitE' PROM arrayA. 'VA,.AddressinputsY buffers,latch anddecoderI/O buffersand latchControllogicI/O. 'V I/O,Data inputs/outputsMODE SELECTION~ O"l: WEModeI/OPowerV IH X XStandbyHigh ZStandbyV IL VIL V IHV IL V IH LSV IL V IH V IHRead5V byte writeProgram (READ ANDWRITE) inhibitDOUTDINHigh ZActiveActiveActiveV IL V IH VppV IL V IH VppV IL V OE VppByte eraseByte writeChip eraseDIN=VIHDINDIN-VIHActiveActiveActiveHigh-voltage programmingmodeNote: X;Don'tcare(VIHorVIL)421

.EEPROM·MSM2816ARS.I--------------------------------------DEVICE OPERATIONRead ModeData in the MSM2816A can be read by applying a TTLhigh signal to WE:, and a low signal to C'E and ~. Thedata for tAA time from address inputs; for tCE timefrom a low on DE, and for tOE from a low on 01:,whichever occurs last, is valid. Once a TTL high signalis applied to DE or CE, the I/O pins are in a high impedancestate to prevent data bus contention withinthe system.Write ModeThe MSM2816A has two write modes:• 5V programming mode (standard)In this mode, a write cycle is initiated by applyinga TTL low signal to WE and CE and a high signal toDE. Address inputs are latched on the trailing edgeof WE or C'E whichever is the slower. Data on theI/O pins is latched on the leading edge of WE orCEo The address and data are latched for 200 nsby using TTL level write signal. Once the data islatched, the MSM2816A erases the byte that is selectedwithin 10 ms automatically and writes new datato it.In the meantime, the system is available to other tasks,but the I/O pins are in a high impedance state whilewriting is in progress. The system recognizes the completionof a write operation by comparing the datalast written against previous data. When this methodof verification is to be used, the output may bepulled up to V CC with a resistor so that all read dataprior to the completion of the write operation shouldbe '1'.• High-voltage programming modeWhile the MSM2816A merely requires a single 5Vpower supply to write, it is also operable in the highvoltagemode to remain compatible with existingE2 PROMs. In this mode, all selected bytes must beerased before new data can be written to them. Thebyte erase operation can be initiated the same way asa high-voltage write operation, except that a TTLhigh level is applied to every I/O pin. To be able towrite new data to a byte in the high-voltage mode, itis necessary to apply a TTL high level to DE and aTTL low level to CE before WE is raised to a voltage(Vpp) between 12V and 22V. The MSM2816A hasno constrain on Vpp rising or falling edges, and datapresent on the I/O pins is written to memory withina maximum period of 9 ms from address inputs.High-voltage Chip EraseThe data in all memory cells is erased within 9 ms whenDE is initially raised to 12-22V, then WE is raised to12-22V while applying a TTL high signal to every I/Opin. After the erasure, all data bits in the device are setto TTL high level (logic '1 ').Standby ModeThe 2816A has a standby mode which reduces theactive power dissipation by about 55% when a TTLhigh level is applied to CEo• Number of repetitive write cyclesThe MSM2816A is designed to support applicationsrequiring up to 10,000 write cycles per byte.• Inadvertent write protectionThe MSM2816A has following four functions toprevent inadvert write during power up, power down,and during line noise occurrence.(1) VCC level detectionWriting to the device· is automatically inhibitedwhen VCC has fallen to 3.0V or below.(2) Time delayAny write operation is automatically inhibitedwhile VCC is 5-20 ms in the Vwl state when theMSM2816A is being powered up.This features allows sufficient time for the systemto apply a TT L high signal to WE or C E beforewrite occurs.(3) OE gatingThe MSM2816A inhibits all write operations whileDE is low.(4) WE noise protectionNo write cycle may be initiated by write pulsesfor 20 ns or shorter.ELECTRICAL CHARACTERISTICS• Absolute Maximum Ratings (Note 1)Ambient temperature under bias ...Storage temperature .................. .Voltage on any pin with respect to ground (Note 2) .DC output current ............ .DE and WE voltage in high-voltage mode ...... .-10°C "v +85°C-65°C "v +125°C-0.5V"v +6V5mA22.5VNotes:1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to thedevice. This is a stress rating only and functional operation of the device at these or other conditionsabove those indicated in the operational sections of this specification is not implied. Exposure to absolutemaximum rating conditions for extended periods may affect device reliability.2. The device incorporates a special circuit to sat"eguard it against electrostatic damage. For added assurance,avoid operating the device above the maximum ratings indicated.422

---------------------------------------.EEPROM·MSM2816ARS.DC OPERATING CHARACTERISTICSParameter Symbol ConditionLimitsInput low voltage VIL - 0.8 VInput high voltage VIH 2.0 - VOutput low voltage VOL IOL=2.1.mA - 0.4 VOutput high voltage VOH 10H = -400 "A 2.4 - VWrite inhibit VCC voltage VWI 3.0 3.5 VWE voltage (erase/write) (Note 1) VPP 12 22 VOE voltage (chip erase) (Note 1) VOE 12 22 VVPP current (byte erase/write) Ipp(W) CE = VIL - 10 "A(Note 1)Vpp current !inhibit) (Note 1) Ipp(J) Vpp = 22V, CE = VIH - 10Vpp current (chip erase) (Note 1) Ipp(C) - 10VOE current (chip erase) (Note 1) 10E VOE = Vpp = 22V - 10 "AI nput leakage current ILl VIN = 0 'V 5.25V - 10 "AOutput leakage current ILO VOUT = 0 'V 5.25V - ±10 "AOperating supply current ICC CE = OE = VIL - 110 mAAll I/O S = OPENOther pins = 5.25VStandby supply current ISB CE = VIH, OE = VIL - 40 mAAll I/O S = OPENOther pins = 5.25VMINMAXUnit"A"ANote 1:These parameters apply only in the high-voltage programming mode.CAPACITANCEITA = 25°C, f = 1.0 MHz, VCC = 5V)Parameter Symbol Conditions MAX UnitInput/output capacitance CliO VI/O = OV 10 pFI nput capacitance CIN VIN =OV 6 pF423

.EEPROM·MSM2816ARS.---------------------------------------AC CHARACTERISTICS (Note 1)(1) Read cycleParameterSymbolMSM2816A-250MINRead cycle time tRC 250Chip enable access time tCE -Address access time tAA -Output enable access tOE -timeOutput set time (CE) tLZ 10Output disable time tHZ 10(C1':)Output set time (OE) tOLZ 10Output disable time tOHZ 10(OE)Output hold time tOH 20MAX-250250100-100-70-MSM2816A-300MIN300---1010101020MAX-300300120-100-80-MSM2816A MSM2816A-350 -450UnitMIN MAX MIN MAX350 - 450 - ns- 350 - 450 ns- 350 - 450 ns- 135 - 150 ns10 - 10 - ns10 100 10 100 ns10 - 10 - ns10 100 10 100 ns20 - 20 - ns~Addre.,CE~OEWEData OutNote 1:AC test conditionsInput pulse voltage levelPu Ise rise/fall timeInput/output timing levelLoad conditionso 'V 3V10 ns1.5V1 TTL, CL = 100 pF.424

--------------------------------------_..EEPROM·MSM2816ARS.(2) Write cycle (5V programming mode)LimitsParameterSymbolMIN MAXUnitWrite cycle time twc 10 - msAddress setup time tAS 10 - nsAddress hold time tAH 70 - nsWrite setup time tcs 0 - nsWrite hold time tCH 0 - nsWrite pulse width (IT) tcw 150 - nsOutput enable setup time tOES 10 - nsOutput enable hold time tOEH 10 - nsWrite pulse width (WE) (Note 1 ) twp 150 - nsData latch time tDL 50 - nsData valid time (Note 2) tDV - 1 IlSData setup time tDS 50 - nsData hold time tOH 10 - nsWrite inhibit time during power-up tlNIT 5 20 ms• WE control write cycleAddressData OutData InHigh Z~ ~Data Valid ~~tDs-l-tDH-'425

·EEPROM·MSM2816ARS.I---------------------------------------• CE control write cycleAddress.. twcCEOE%0'WE~Data OuttDV-Data In Data Valid)000tDS-J...-tDHNotes: 1. WE is noise protected. No write cycle may be initiated by write pulses for 20 ns or shorter.2. Data must be set valid within 1 liS after the start of a write cycle.(3) Write/erase cycle (High-voltage programming mode)(V CC = 5V ±5%, Ta = DoC "v 70° C)LimitsParameter Symbol ConditionsMIN MAXUnitVpp address setup time tAS 10 - nsVpp CE setup time tcs 10 - nsVpp data setup time tDS 0 - nsData hold time tCH Vpp = 6V 50 - nsWrite pulse width twp Vpp = 12V 9 70 msWrite recovery time tWR Vpp = 6V 50 - nsChip erase setup time tos Vpp=6V, VOE= 12V 10 - nsChip erase hold time tOH Vpp=6V, VOE= 12V 10 - nsVpp OE setup time taos Vpp = 6V 10 - nsVpp OE hold time taoH Vpp = 6V 10 - nsWrite inhibit time during power-up tlNIT VCC > VWI 5 20 ms426

---------------------------------------.EEPROM·MSM2816ARS •• Byte erase/write cycleAddress )K KVpp(WE Pin)Data In'".. tAS twpVppV~V IH/ I\.-- --tDS ~......Data ValidtDHI---tcstWRr-}-_IWR_I--.....r-tBOSXXXxxxx xY xx XtBOHII~• Ch ip erase cycleCEVpp(WE Pin)Data In"f+-tcs twpJtWR IVppV~V IH / ""--/tDS--- -V IHtDH '\V OE/OE/"-"-... tOS .... ,.tOH-"PRODUCT INFORMATIONModel name Access time Operating temperature PackageMSM2816A AS-250 250MSM2816A AS-300 300MSM2816A AS-350 350MSM2816A AS-450 450MSM2816A RS-250 250MSM2816A RS-300 300MSM2816A RS-350 350MSM2816A RS-450- 450o "v 70°Co "v 70°CCerdipPlastic427

IIi) CROSS REFERENCE LIST1. DYNAMIC RAM ............................................................. 4312. STATIC RAM ............................................................... 4363. MASK ROM ................................................................. 4384. EPROM .................................................................... 4395. E2P ROM ................................................................... 441

(Note) I. Type No.'--.--'-_---'1.Package Material1. DYNAMIC RAM'---------Access Time (ns) max.P: PLASTICG: CERDIPC; SIDE-BRAZEDJ: PLCCYS: SIMMKS: SIPOr- NumtureBitStruc- Totalgani- ber of Okization PinHitachi Intel TexasMostek Motorola NEC Toshiba MitsubishiFujitsuMSM3764-15HM4864-22164-15 TMS4164-15MK4164-15 MCM6665-15 IlPD4164-3 TMM4164C-3 M5K4164-15MB8264-15150 Ip.C1501 C 1501 C 150 1 C1501 C 150 1C 1501 C 150 1 P.C 150 1 C150 l CMSM3764-20HM4864-3MK4164-20 MCM6665-20 IlPD4164-2 TMM4164C-4 M5K4164-20MB8264-20200 1 P.C2001 C200 1 C 200 1C 2001 C 150 1 P.c 200 1 C200 1C65536NMOS 64kxl16M5K4164A-l0 MB8264A 10100 1 P.C 1001 P.GMSM3764A-12 HM4864A-lTMS4164A-12MCM6665A-12 IlPD4164A-4 TMM4164A-2 M5K4164A-12 MB8264A-12120 Ip.C1201 P.G 120 1 P.C120 1 C 120Ip·G.C 120 I P 120 I P.C1201 P GMSM3764A-15HM4864A-2TMS4,164A-15MK4564MCM6665A-15 IlPD4164A-3 TMM4164A-3 M5K4164A-15 MB8264A-15150 jP.C1501 P.G 150 1 P_C150 I P 150 1 C 150Ip·G.c 150 1 P 1501 P.C1501 P.G....U)~~MSM3764A-20200 1 P.CMSM37S64-15150 I PMSM37S64-20200 1 P150 I PMSM37S64A-15NMOS 128k 131072 16xlMSM37S64A-20200 1 PHM4864A-3TMS4164A-202001 P.G 200 1 P.CMCM6665A-20 IlPD4164A-2M5K4164A-20 MB8264A-20200 1 C 200Ip·G.c 200 I P.C 200 I P.GI--o •::Doenen::Dmm '"::DmZomr-iii-f•

....Co)I\JStructureTotalBit§ori_\ Numgani- ber 0zation PinOkiMSM41256-12120 I P.C.JMSM41256-15150 I P.C.JHitachi Intel Texas MostekHM50256-12 TMS4256-12 MK4556-12120 I P.G 120 I P 120 I PHM50256-15 TMS4256-15 MK4556-15150 1 P.G 150 1 P 150 1 PMotorola NEC ToshibaMCM6256-10100 I P_CMCM6256-12"PD41256-12 TMM41256C-12120 1 P.C 120 Ip.G.c 120 I P.GMCM6256-15 "PD41256-15 TMM41256C-·151501 P.C 150 Ip.G.c 150 -1 P.GMitsubishiM5M42565-12120 I P.CMSM4256S-15150 1 P.CFujitsuMB81256-10100 I PMB81256-12120 I PMB81256-15150 1 P• n:Doenen:Dm"IIm:DmZnmr-iii-IMSM41256-20HM50256-20 TMS4256-20 MK4556-20"PD41256-20M5M4256S-20200 I P.C200 1 P.G 200 1 P 200 1 P200 Ip.G.C200 1 P.CMSM41256A-10MCM6256-10MB81256-10100 I P.C100 I P.C100 I PNMOS 256k 262144 16 MSM41256Axl12120 I P.CHM50256-12TMS4256-12120 I P.G 120 1 PMCM6256-12"PD41256-12 TMM41256C-12120 T P.C 120 Ip.G.C 1201 P.GM5M4256S-121201 P.CMB81256-12120 1 PMSM41256-15HM50256-15TMS4256-15MCM6256-15"PD41256-15 TMM41256C-15MSM4256S-15MB81256-15150 I P.C150 I P.G 150 I P150 I P.C 150 Ip.G.c 150 I P.G150 I P.C150 I PMSM41257A-10"PD41257-10MB81257-10100 I P.C1001 P.c100 1 P.CMSM41257A-12HM50257-12TMS4257-12MCM6257-12 "PD41257-12TMM41257-12M5M41257-12MB81257-12120 1 P.C1201 P.C 120 I P120 I P.C 120 I P.C 120 I P.C120 I P.C120 I P.CMSM41257A-15HM50257-15TMS4257-15MCM6257-15 "PD41257-15TMM41257-15M5M41257-15MB81257-15150 I P.C150 I P.C 150 T P150 T P.C 150 T P.C 150 T P.C150 I P.C150 I P.C

TotalBitStructureOr- Numgani-ber 0 Okization PinHitachi Intel Texas Mostek Motorola NECToshibaMitsubishiFujitsuMSM41464-10H M50464P-l 0/lPD41464C-l0MB81464-10100 I P100 I P 100 I P100 I P256k65536 18x4MSM41464-12120 I PHM50464P-12/lPD41464C-12120 I P 120 I PTMM41464P-12120 I PMB81464-12120 I PMSM41464-15150 I PHM50464P-15 /lPD41464C-l 5150 I P 1501 PTMM41464P-151501 PMB81464-15150 I PMSC2301-12MH2560912NMOS 512k 65536 30x81201vs.KSMSC2301-151501vs.KS120 I VSMSC2301-12TM4164-12576k65536 30x9120 IVS.KSMSC2301-15120 I KSTM4164-15150 IVS.KS150 I KS.I>­WW2304kMSC2304-121201vs.KS2048k 30262.144 I MSC2304-15x81501vs.KS262,lrx930E3MSC2304-12120 IVS.KSMSC2304-15150IVS.KSHM561003-121201vs.KSHM561003-15150 [VS.KSMH25609-12120 I VSMH25609-15150 I VS!o •:Doenen:Dm'TIm:DmZomr-Cii-I•

~c.J~NMOSTotalBit1M§StructureOr- Numgani-ber of Okization Pin1048576 18xlMSM411000100 I PMSM411000120 I PMSM411001100 I PMSM411001Hitachi Intel Texas Mostek Motorola NEC"PD4110001001 P"PD411000120 I PToshibaMitsubishiFujitsuMB8ll00120 I PMB8ll00ln •:Dornrn:Dm;A:DmZnmI"'"iii....120 I P120 I PMSM414256-10262144 20x4100 I PMSM414256-12120 I PMSM511000-10100 I PMSM511000-12 HM511000-12TC511000-101001 PTC511000-12120 I P120 I P120 I PCMOS10485761Mxl 18~M511000-15150 I PMSM511001-10TC511001-10100 I P100 r pMSM511001-12 HM511001-12TC51100i-12120 I P120 I PHM511001-15150 I P120 I P

TotalBitStructureOr- Numgani-ber of Okization PinMSM514256-10100 I PMSM514256-12Hitachi Intel Texas Mostek Motorola NEC Toshiba Mitsubishi FujitsuCMOS1M 262144 20x4120 I PMSM514257-10100 I PMSM514257-12120 I P~W01Elo •::uo(/)(/)::um"'IIm::umzomr-en-I•

.l>e,)Ol§2. STATIC RAMStruc- TotalOr- NumtureBitgani- ber ofzation Pin2048NMOS 16k 24x8OkiMSM2128-12120 I PMSM2128-15150 I PHitachi Intel Texas Mostek MotorolaNEC ToshibaTMM2016P-l100 I PI'PD4016C-3 TMM2016P150 I P 150 I PMitsubishi58725-15150 I P.CFujitsuMB8178100 I PMB8178150 I Pn •::Doenen::Dmm "'"::DmZnm,...en....MSM2128-20I'PD4016C-2 TMM2016P-258725200 I P200 1 P 200 1 P200 I P.CMSM5114-2I'PD444-3200 I P200 I PI'PD444-2250 I PCMOS4k1024x418MSM5114-3300 I PHM4334-3300 I PI'PD444-1300 I PMSM5114HM4334-4I'PD444TC5514M58981-45450 I P450 I P450 J P 450 1 P450 I GTC5514-1650 PTC5514-2800 I PII

TotalBitStructureOrganizationNumberof Oki Hitachi Intel Texas MostekPinMotorola NEC ToshibaMitsubishiFujitsuMSM5128-12HM6116L-2M5M5117-12120 I P 120 I P120 I PMSM512815HM6116L-3/LPD446-3M5M5117-15MB8416-15150 I P 150 I P150 I P150 I P150 I PCMOS16k2048x824MSM5128-20HM6116L-4200 I P 200 IP/LPD446-2 TC5517-2200 I P 200 I PMB8416-20200 I P/LPD446-1TC5517M5M5117MSM5126-20 HM6116L-4200 I P 200 I PMSM5126-25250 I P250 I P 250 I P/LPD446-7 TC5517-2200 I P 200 I P/LPD446-1 TC5517250 I P 250 I P/LPD445450 I P250 I PMSM5165-12HM6264-12M5M5165-12~w"'"CMOS64k8192x816384x42822120 I P 120 I PMSM5165-15HM6264-15150 I P 150 I PMSM5165-20200 I PMSM5188-4545 I PMSM5188-5555 I PMSM5188-7070 I PEm/LPD4364-15 TC5565-1150 I P 150 I P/LPD4364-20200 I P/LPD4362-4545 I P/LPD4362-5555 I P/LPD4362-7070 I P120 I PMB8464-15150 I P•(')::Dot/)t/)::Dm"TIm::DmZ(')mr-ei)-I•

.....U)(Xl3. MASK ROM§Or- NumtureBitStruc- Totalgani- ber ofzation PinNMOS64k8192x8242816384128k 28x8OkiMSM2965300 I PMSM3864250 I PMSM38128A250- I PHitachi Intel Texas Mostek MotorolaMK36000-5 MCM68A-364300 I P.G 250 I P.CHN48364MCM68A-364350 I P 350 I P.C2364A4501p·GNEe ToshibaI'PD2364 TMM2364450 I P.G 250 I PTMM23128200 I PMitsubishiM58334650 I PFujitsuo •:uo:um'TIm:umzomr-iii-I•MSM38256MK38000M5M2325632768256k 28x8250 I PMSM3a256A250 I P.G250 1 PNMOS512k65536x828150 I PMSM38512200 I PI256kCMOS1M3276828x8131072 28x8 IMSM53256150 I PMSM531 000250 I P

4. EPROMOrtureBitNumberofStruc· TotalganizationPinOkiHitachiIntelTexas Mostek Motorola NEG ToshibaMitsubishiFujitsuMSM2764-20200 I GHN482764G- 02764-220200 I G 200lGIlP027640 2 TMM27640-2200 I G 200 I GMBM2764-20200 J GMSM2J64-25HN482764G 02764IlP027640TMM27640MBM276425250 I G250 I G 250lG250 I G 250 I G250 I G64k8192x828MSM276430300 I GHN482764G 02764-330300 I G 300lGIlP027640-3300 I GMEM2764-30300 I GNMOS02764AGP2764A250 I PTMM2764API GTMM2764AP200 IpMSM27128-20200 I GIlP0271280-2 TMM271280-20200 I G 200 I GM5L27128K-2200 I G.l>e.>

~~oNMOSTotaLBit256k512k§StructureOr- Numgani-ber of Oki Hitachization Pin32768x8~5536x828MSM27256-15150 I GMSM27256-20200 [ GMSM27256-25 HN27256G-25250 I G 250 I G28 MSM27512-15150 I GMSM27512-20Intel Texas Mostek Motorola NEG ToshibaP27256TMM27256D-15'150 I GTMM27256AD-20200 I GTMM24256AP250 I P 200 I P27256250 I GI'PD27256DTMM27256D200 I G 150 I GMitsubishiM5L27256K-2200 I GM5L27256K250 I GM5L27512K-2FujitsuMBM27256-20200 I GMBM27256-25250 I G• o:Doenen:Dm"'IIm:DmZomrUi-I•1M200 I GMSM27512-25 HN27512G-25250 I G 250 I GMSM271 000-12120 I G131072 32 MSM271 000-x8 15150 I GMSM271 000-20200 I G27512250 I G27010-200V05200 I G200 I GM5L27512K200 I GMBM27512-25250 I G

OrtureNumberofStruc- Totalgani-Bit"ation PinOkiHitachi Intel Texas MostekMotorola NEC ToshibaMitsubishiFujitsuMSM271 024-12120 I GNMOS 1M65536x 1640MSM271024-15150 I G27210-150/05150 I G27210-170/051701 GMSM271024-20200 I G27210-200/05200 I G--5. E 2 P ROMStruc- Totalture BitOr-ganizationNumberofPinOkiHitachi Intel Texas MostekMotorola NEC ToshibaMitsubishiFujitsu.....NMOS 16k2048x8MSM2816A-25250 I PMSM2816A3024 300 I P~MSM2816A-35350 I PMSM2816A-45450 I P2816A250 I P2816A-3350 I Pn:Doenen:Dm"'IIm:DmZnmr-en-I•

m APPLICATIONS64K BIT DYNAMIC RAM APPLICATIONS NOTES ................................... 4451. MEMORY DRIVER .......................................................... 4452. DECOUPLING CAPACITORS ................................................ 4463. PRINTED CIRCUIT BOARD .................................................. 4464. PERIPHERAL CONTROL CIRCUIT ........................................... 4475. NOTES ON MOUNTING 1 MB MEMORY ON A BOARD ......................... 4486. MEMORY SYSTEM RELIABILITY ............................................ 4497. MEMORY COMPARISON STANDARD ........................................ 451CMOS RAM BATTERY BACK-UP ................................................... 4541. SYSTEM POWER AND BATTERY SWITCHING CIRCUIT ...................... 4542. SWITCHING CIRCUIT MODIFiCATIONS ...................................... 4543. DATA RETENTION MODE ................................................... 4564. INTERFACiNG .............................................................. 4575. MISCELLANEOUS .......................................................... 457MASK ROM KANJI GENERATION MEMORY DESCRIPTION ................. , ....... 4571. KANJI GENERATION MEMORIES ............................................ 4582. MSM38256 SERIES ......................................................... 459m

64K BIT DYNAMIC RAM APPLICATION NOTES1. MEMORY DRIVERThere are problems in driving MOS ICs by a TTL driver:increase of driver delay time due to capacitive load andringing waveform at the falling edge.An example of the increase of delay time due to capacitiveload is shown in the following figure.The number of load memory elements must be takeninto consideration when designing the timing.In case of LS type2018..s 16..E 14i=i;" 12~ 108642oPROPAGATION DELAY TIMEvsLOAD CAPACITANCEVCC= 5VRL = 25nTa = 25°CV/' ~ VyV ---/V Vo 10 20 30 40 50 60 70 80 90 100CL - Load Capacitance - pFelf the number of load memory el&ments is 20 - 40(150 - 300pF} on a two layer board, an undershootof -2 to -3V (peak voltage} occurs. Therefore, measuresagainst ringing must be taken as described in thefollowing.e Measures against ringing(1) No consideration is required for the rising edgesince there is a margin.(2} Since ringing may be considered as a reflectiondue to mismatching between the driver outputimpedance and signal line impedance, it can beprevented by line matching (termination}.For memory arrays, however, termination withpull up or bleeder resistance is not effective.Instead, series resistance (damping resistance} issuitable for memory arrays.(3} The optimal value of series resistance differsdepending upon the speed, pattern status, anddriver. Experience will help in determining theoptimal series resistance .As a general ru Ie, a resistance of 10 - 100n issuitable.However the speed will be lowered if the resistanceis too large. An example is shown inattached drawing 3.(4} Make the signal lines as short as possible. Multilayerboard design is effective in reducing theundershoot (as the signal line impedance islowered}.In case of L type'5112, '5113, '5114AVERAGE PROPAGATION DELAY TIMECLOCK TO OUTPUTvsLOAD CAPACITANCE16i;"a;14Cc:o12.~ 10§r:t..~~I...J::t:~+N::t:...J~8642o oVCC= 3VRL = 280nTa = 25°C/' V.....- .....-V V25 50 75 100 125 150 175200CL - Load Capacitance - pFill445

• APPLICATIONS •• -----------------------iII2. DECOUPLING CAPACITORSThe dynamic MOS RAM is featured by the- greatpower current at the active time in comparisonto that at the standby time.For example, the rated value (Icc!) of the meanpower current of the MSM3764 is 4SmA, whilethe standby current (lcc2) of the MSM3764-1S(150ns version) is SmA. The former is approximately10 times greater than the latter. The peak currentof the MSM3764 approaches 90mA in the worst case.It is approximately 20 times as great as the standbycurrent Icc2.Therefore,. the power circuit must be designed soas to prevent the above current variation fromcausing an erroneous operation of the memory.A by-pass capacitor must be inserted for thispurpose. There are two types of by-pass capacitors:high frequency capacitor and low frequencycapacitor.2.1 High Frequency CapacitorIn the Icc current waveform, the peak currentrises at a high speed such as 10ns, and a highfrequency noise represented by thl! followingexpression is caused to occur by the L componentof the current applied to the capacitor:To reduce the fluctuation AV, the value of Lmust be reduced.For this purpose, the capacitor must be placed asclose as possible to the power pin of the IC. Further,sufficient capacity for supplying the peakcurrent is required. The standard capacity for adouble sided circuit board (two layer circuitboard) is O.OS - O.lI'F or more. The capacitymay be less than this value for a multi layercircuit board since the L component is less thanthe former.When designing a board, mount one capacitorwith excellent high frequency characteristics forevery two or three MOS IC memory chips, nearthe power pins of these IC chips.2.2 Low Frequency CapacitorA low frequency capacitor is required for supthepower fluctuation due to a suddenpressingcurrent variation (for example, current variationcaused by a status change from the standbystatus to the continuous access status or concurrentrefreshment of the entire board) in a boardunit. The power fluctuation in this case is a slowvariation of several handred ns.For this reason, the low frequency capacitormust have a capacity larger than the high frequencycapacitor.Though the capacity requirement depends uponthe number of memories which operate simultaneously(bit width), SOI'F is enough for a 16-32 bit system in a practical use.As an example of capacitor which satisfies therequirements in both 2.1 and 2.2 above, asmall-sized tantalum capacitor with excellenthigh frequency characteristics is shown in thefollowing table. It is desirable to mount a lowfrequency capacitor near the power input pin inorder to suppress the fluctuation of power suppliedfrom outside, even if this capacitor ismounted.Manufacturer Model Capacity (I'F)Oki Ceramic Co.Model CAtantalum. capacitorModel CB0.1 - 20l'FThe frequency characteristics of the abovecapacitor and the power bus bar are illustratedin attached figure 1 .3. PRINTED CIRCUIT BOARD3.1 Number of LayarsConsidering the measures against power noise which wasdescribed in 2. above and the routing to be described in3.2, two layers are enough in principle.3.2 RoutingAn example of routing on a two-layer circuit board isshown in attached drawing 2. In designing the routing,note the following four points:(I) The MOS drive line based on the TTL must be asshort as possible to prevent ringing (reflection) andreduce crosstal k.(III Considerations are required to lower the impedanceof the power line (including the ground). (Forexample, make a solid or grid-formed power linepattern. It is desirable that the power line patternhas width of at least 1.27mm.)(1111 If a signal line is to be branched for multi drive,the line must be branched at the driving end.(See the following figure.) And, the memorymatrix must be designed in an integrated form, andperipheral drivers must be placed near the memorymatrix.Memory element446

-----------------------.APPLICATIONS.4. PERIPHERAL CONTROL CIRCUITThe three types of dynamic RAM control ICs shown inthe following teble are available at present.IntelMotorolaManufacturerTexas Instruments(T. IlAdvanced MicroDevice (AMD)Inteli·3242ModelMC-324274 LS601603Am2964Ai-8203Functionso Seven·bit address multiplexer (for 16K bitdynamic RAM)o Seven·bit refresh address count functiono Direct dirving capability of memory elements (forapprox. 20 elements. 250 pF/25 ns 15 pF/9 ns)o Application to a 64K bit dynamic RAM, example(see the following figure)o Refresh timer using an RC multivibratoro Timing generationo Refresh address (7-bit address)o Address latch/multiplex function (16-bit address)o Refresh address countero RAS decoder (2 - 4)o 8-bit address multiplexer (for 16K/64K DRAM)o Direct dring capability of memory elemento Including timing controlREFENABLEAo------.--1--L-----~----------------r_~3242A,.------~---L __ ~-----1---------------------L--lMSM3764A,A,. ______ ---.JA .. --------iROW ENABLEHI447

_APPLICATIONS __ -------------________ _5. NOTES ON MOUNTING 1 MBMEMORY ON A BOARDThe advent of a 64K bit dynamic RAM such as theMSM3764 has made it extremely easy to mount 1 M8memory on a board from the viewpoint of mountingspace. In this case, however, note the following pointssince the number of memory elements mounted is solarge as 128 - 176 (when redundant bits are provided).Point to be noted Consideration Practical exampleMounting ofmemoryelementsMemory elements may be integrated ordivided.(Design the memory array(s) to makethe drive lines shortest.)81 I I I I I I II MemoryarrayEmEBrEmEMemory array Memory arrayMemory Take care about the delay time and Drive elementelementundershoot noise of the drive element.drivi ng method (If the condition VILmin =IS::-lV recom·Delaymended for the MOS dynamic RAMtimeoperation is satisfied, the memory elements Elementwill display the full reliability.)7404 Mediumspeed(mA)NoiseIOL16 074S04Highspeed20 XMeasuresagainst noiseo Two layers are enough for a board.(Pay attention to the power line pattern.)o High frequency noise Mount a 0.1 - 1 "F capacitor for every twomemory elements.o Low frequency noise Mount a tantalum capacitor etc. of 50 "For more near the power input pin of thememory package.Timing design o Prevent skew between each timing in order Use ICs of the same tipe for racing timingto enhance the system access speed.(for example, RAS or CAS).o Make a sufficient margin in timing design.Skew and mounting delayThermal design Thermal design under the worst condition Operation at a case temperature of 70°Cis required.must be guaranteed.m448

-'-"-----"1-----------------------.APPLICATIONS.6. MEMORY SYSTEM RELIABILITY6.1 Reliability O_mination FactoRThe memory system reliability depends upon the fourfactors shown in the left column of the following table.These factors are determined as shown in the rightcolumn of this table.Memory systemreliability factorSystem·requ iredreliabilityUnit capacityParts reliabilityCost6.2 Hard Error and Soft ErrorFactor determinationDetermined by the user-requiredspecifications (MTB F).'" [MB] = [word depth] x[bit count]Logic element :::::::z: Hard errorMemory element Soft error(I) Hard errorA hard error is a permanent error which occurs eachlime a certain address is accessed.(I il Soft errorA soft error is a transient error that does not repeat. Thefollowing are the three causes for soft errors:(1) I nsufficient power margin(2) Insufficient system noise margin(3) Particle failure(4) I nsufficient power margin(5) Insufficient system noise margin(6) particle failureItems (1) through (5) are largely influenced by thesystem design. For item (6), it is required to considerwhether a remedy such as ECC should be taken or notto satisfy the system-required reliability based on theperts reliability (pertaining to hard errors and softerrors). See 1.3 and 1.4 for details.6.3 Measures for Reliability EnhancementThe following are the two typical means for the enhancementof system reliability.(1) Parity..(2) ECC.. Error detection only (makes nocontribution to the MTBF enhancement).The SEC-OED" is used in general• Jiingle.s.rror .correct - .Qouble ~rror Qetect(one bit error correction and two bit error detection)6.4 Reliability Calculation MethodMT B F for a hard error and a soft error(1) Memory element reliabilityHard errorSoft errorrH = e -XH·t (XH: Hard error rate)rS = e -XS·t (XS: Soft error rate)Aeliabilityn n-l)A = (rH) + nC, • (rH"rs) ·(1 - rHCD ~

• APPLICATIONS •• -----------------------o 12Bkbyteo 256kbyteElementAH AS MTBF(Fit) (Fit) (years)ElementAH AS MTBF(Fit) (Fit) (years)64k 100 1000 5.B200 5.3100 100 7.964k 100 1000 2.9200 2.6100 100 4.016k50 10.6200 6.316k50 5.3200 3.250 100 10.650 100 5.350 15.950 7.9Notes:1. The bit width is 9 bits for each case.2. 1 bit is used for parity error detection.(2) Comparison of 1 M byte configurations (with ECC)Element AH (Fit) AS (Fit)Bit width: 22 bitsReliability (years)Bit width: 39 bits64k100(100%)100(50% 50%)10001000B.2 (0.76) 7.9 (0.79)13.9 (0.76) 14.5 (0.79)16k100(100%)100(50% 50%)100100B.3 (1.05) 6.B (1.0B)13.0 (1.05) 10.7 (1.0B)Notes:1. When the bit width is 22 bits, six bits areused for the ECC.2. When the bit width is 39 bits, seven bits areused for the ECC.3. Values in parentheses are the reliabilities inthe case of parity error detection withoutECC.4. The (50%, 50%) in the AH column meansthat 50% of th-e hard error rate AH is han·died as the total bit hard error rate and theremaining 50% is handled as the one bithard error rate (which reflects the harderror mode analysis result confirmed so far!.450

_______________________ • APPLICATIONS.7. MEMORY COMPARISONSTANDARDIn general, power, speed, and usability are required formemory elements. At present, 64K bit dynamic RAMscan be supplied by a lot of manufacturers, and theseelements have almost unified specifications.In designing a circuit board to achieve stable systemoperation, however, considerations must be given to thespecification values and margins against the spacificationvalues, pertaining to the points shown in the followingtable. Factors that will affact the stable system opera·tion are power, tempereture, aging, clock skew, unevenoperation of peripheral ICs, and so forth.Pointto be notedActual item to be consideredReasonPower o Currents (lcc1, Icc3, and Icc4) at the operating The power system must be noted.time and current (lcc2) at the standby time (example: with battery backup)TimingmarginVoltagemargino Current waveform (especially the peak currentvalue)o Address setup (tASR, tASe) and hold (tRAH,tCAH) timingo Data setup (tOS) timing and write pulse width(tyVp)Voltage, temperature, and dependability of eachtiming (especially the tREF and tRAcIIt is impossible to achieve the ideal voltage statuswhen used with ina system.The noise margin must be strict formemories with large peak current.In system designing, these timing pulsesare directly related to the access time.These timing pulses are related to thecycle time in writing.The temperature inclination must belittle for the timing pulses tREF andtRAC·A sufficient voltage margin must beprovided under consideration of variousfactors which will affact the systemoperation stability.Attached drawing 1Frequency characteristics of capacitor and O!PAC50(n)10Z5a/PAC sactional viewJrr.1Pin 3 Pin 1 Pin 2---Model CB tantalum 1.01'Fcapacitor (manufacturedby the Oki Seramic)Model CB(1.0I'F)a·PAC(between pins1 and 2)a·PAC/V'-

• APPLICATIONS •• ----------------------Attached drawing 2Two layer board circuit pattern exampleDAOA2AlVsst--~I~~,t:::""~g,--;~ ,~rCAS -=WE -RASA6-----,--1A7 "v CCIr.~-.-n :::air",,~Ir--e H.ll: I"" "~~ ~ '~~~ ,~' ~,I~ g ~ e ~ I~ ItI t1t IA III~,'~II - ~F- ~Ii ~~tir - ~ !lE-- - ~ 'lM - @'QJ 14(· '@'IG{ &' ~ @iQ()9 ~ )BRIt l49 W ~,~~ 'G' ~~ ~~ - f-6) r@'c-=:"":a;-r"n m fC;;;;:1T;'~;;;- ""'~ =4i In-.. •:"lri. '~ --'=--9- '- ~J•f- ~ ~e-'~;--; ~r= .....Aii .it- ill ,~~ ~'e.- Ii:11- l~ ~-=- l~.~-~~ II [l~ J~ Ie ~10 l:P.~ ~-~ :

----------------------. APPLICATIONS.Attached drawing 3Input waveform exampleHorizontal: 50 ns/div )(Vertical: 1 volt/divD5Hl[[453

CMOS RAM BATTERY BACK-UPA practical example of formation of nonvolatiledata by CMOS static RAM batteryback-up is outlined below.1. System power and battery switchingcircuitThe simplest RAM power supply (CMOS Vcc) is out·lined in Fig. 1. In this case, the CMOS Vcc for normaloperation is kept at a voltage 0.7V below the systemvoltage by the voltage drop across a diode (forwarddirection).SystembatteryBatteryNote: CS floating capabilityPower down possible irrespective of other inputlevels when memory has not been selected (i.e.when CS = H).Consequently, if the TTL Vcc level is greater than theCMOS RAM supply voltage, and the RAM driver is atthe TTL Vcc level, the CMOS RAM input voltage willexceed CMOS Vcc + 0.3V (a situation which must beavoided). Therefore, in order to reduce the voltagedifference between CMOS Vee and TTL Vcc with thebattery voltage set to at least 4.5V or 4.75V (due totl1e RAM operating supply voltage range), the 02 diodemay be added to abtain a system voltage level at leastO.7V above 4.5 - 4.75V (which will keep CMOS Vccand TTL Vcc within the respective CMOS and TTLoperating supply voltage ranges).To cope with (1) and (3), a CMOS driver which will alsooperate at a low voltage Vcc during data hold may beemployed, or else, the open collector and open drainbuffer may be pulled up to CMOS Vcc in order to drivethe RAM.A control circuit for coping with (2) when an abnormalsystem power supply is detected is also required.Fig. 1Fig. 2 is an example of use of a chargeable Ni-Ca batteryas the back-up battery. While the system power is beingemployed, the Ni·Ca battery is gradually charged up viaRc. As in Fig. 1, the diode voltage drop also poses aproblem in this circuit.2. Switching Circuit ModificationsModification of the diode switching circuit can employPNP trans.istors. Voltage drops by PNP transistor V CEare smaller by about 0.2V, and this can lead to thegeneration of a system "power fail" signal.Systembattery02 (optional)r--~--I-.T-TTLVCC01Fig. 2RcCMOS Vcc: Ni·Ca batteryrSystembattery+11'-12N3638V3.9V Rc~ 4701N9141K Y "'-2N222~v' -1~} OptionTTLVeeDThe conditions for formation of non-volatile data (dataretention) by battery back-Up are listed below.(1 r The input signal H level must not exceed Vcc +0.3V when the CMOS RAM Vcc power voltage isdropped.(2) ~ (or CS) must maintain CMOS Vcc "H" level.(3) In order to minimize power consumption, WE,AD, DIN (or 1/0) must be se! to GND level or tothe same "H" level as CMOS Vcc. (This is notnecessary, however, for CMOS RAMs with chipselect floating capability).454Fig. 3Fig. 3 outlines a switching circuit employing a PNPtransistor. The Rc used when a chargeable battery isemployed is replaced by a diode when a non-chargeablebattery is used. In this case, switching occurs at thezener diode voltage, so "power fail" must be detectedby another circuit, and C"E set to CMOS Vcc "high"level.

-----------------------. APPLICATIONS.Figs. 4 and 5 are examples of circuits capable of generatinga POWER FAIL output signal. In these circuits, theC2 capacitance must be rather large, the importantpoint being the need for a smooth gradual change inCMOS Vee when the system power is cut. See next pagefor further details.TTL VeeSystem j 0,CMOS Veebattery 0, : 2N2907 or 2SA495c,l+ V... Rc --l +lc,0, : 2N2222 or 2SC372R, R. --; R. : lK R2 : 100l-POWER D, /0,1 Rs : 500 R4 : 47K... ~FAIL D, : 3.6V Rc : 200R.Ni-Cad : 3.6V0,Rs,l(70mAH)"*'Fig. 4.-------..... POWER FAIL signal.-----~----_r-_+------__+ TTL Vee or system VeeSystem ...--t--.........battery+ C,;;:..=-+-_r--~-~~---t___+ CMOS Vee-=-Ni-Cad1500mAHFig. 55V4.5~ Determined by CTCT = C2 + (another decoupling capacitor)..:.. BatteryI3VCE? 3VGNDt=O2.5V'1------- Example.3V? 2.0V'i------- CMOS Vee-0.1 - 0.2V? 1.5VrnFig_ 6455

• APPLICATIONS •• ----------------------3. Data Retention Mode is cut until it reaches the power voltage for data retention(practically equivalent to the battery voltage, orThe RAM driver (peripheral circuit) is determinedaccording to conditions (1) and (3) required for dataretention. In Oki Electric CMOS RAMs, the powervoltage during data retention is kept at a minimum of2.0V. The CE (or CS) voltage at this time has to be keptat about Vcc -0.2V. And as was mentioned earlier, theCMOS Vee must drop smoothly when the system powerelse reduced by the diode voltage drop). And althoughCE traces the slope of CMOS Vcc reduction at this time,a smooth change in CE is also a necessary condition foractual circuits.(4) When switching to retention mode, or from retentionmode to operation mode, CE must exhibit asmooth change. If noise is generated in CE in this case,the data will be subject to rewriti ng.Cmos Vcc SV ± 10%Operation moder--- Data retention modeCE input VTH =Must be free of noiseVee - 2.0V (RAMP waveform)Other inputs VIL = . +(MIN) 'I ::.......::f,==========~t=======~::2.0V (MIN)I 'F Vcc- 0.2V0.8V(MG~X~-----Jt---~r: ______ I~ _____ O.SV(MAX)t = 0May be longerFig. 7(S) When switching to operation mode, commenceoperation after elapse of tRC (read cycle time) followingVcc reaching the operating power voltage range.Dataretention -tmodeIOperationmode.-/------+--...:.:.;.='--- CMOS Vee = SV ±10%:....t-------.-i, - --- - - ~- V I H = Vee - 2.0VCMOS Vee ' ' I 2.SV = 1/2Vcc (MIN)CE I ' ', j I I C"E VIL = 0.8V (MAX)GND-----~---- -1~-----~-----GNDMay be longertRC min.Fig. 8456

------------------------. APPLICATIONS.4. InterfacingA) TTL InterfaceIn the case of CMOS RAM drive by TTL, use an opencollectortype TTL according to conditions (1) and (3).When the system power line (i.e. TTL Vcc) is cut, theopen-collector TTL 02 in Fig. 9 is turned off, followedby 01 also being turned off, resulting in the CMOSRAM input being pulled-up to CMOS Vcc.TTL Vcc----, lKI1r-~I------~--~INIII________ -.1CMOS VccCMOSRAMISwitching CirCUi~rSystem power lineor TTL VccFig. 9When the power line voltage in LS type TTL is droppedto ground, the output is also dropped to ground,thereby making the pull-up resistors for address linebuffers etc no longer necessary. In this case, however, itwill not be possible to employ this as a control linebuffer which must be switched to "high" during CE (orCS) data retention.(6) I n order to minimize the consumption currentduring data retention, all inputs except CE (or CS, thisbeing designated as either "high" or "low") must bemai ntai ned at either G N D or CMOS V cc_ (Th is doesnot apply, however, for CMOS RAMs equipped with CSfloating function).B) CMOS InterfaceIn systems where the CMOS RAM is driven by CMOSbuffer, operation must be at the data retention powervoltage, and the corresponding output voltage mustsatisfy the requirements indicated in Figs. 7 and 8.---f ~r-Llj -" !l'1 ';"I1 IIVL -;;:-1IVccCMOSRAM.,I"CMOS VceFig. 105. MiscellaneousIn order to further reduce power consumption duringdata retention by even a small margin, the use of aMOSFET as the transistor generating the POWER FAILoutput signal is recommended. This is in order toprevent flow of current from the 14k!l resistor.rn457

MASK ROM KANJI GENERATION MEMORYDESCRIPTION1. KANJI GENERATION MEMORIESIC Number Character storing Config- Character Bit Accessmodels of codes capacity uration style capacity timeMSM38256-19MSM38256-224JIS standard No.13418 characters15 x 16 Gothic style 25yK bits 250ns max"~.§ MSM38256-32J IS standard No.24E3418 charactersMSM38256-35" E15 x 16 Gothic style 256K bits 250ns max"0MSM38256-10" Sl- JISstandard No.19.c 3418 characters.!? MSM38256-18:r:24 x 24 Ming style 256K bits 250ns maxMSM38256-38MSM38256-469JIS standard No.23418 characters24 x 24 Ming style 256K bits 250ns maxMSM38128-00"0 18" ~ MSM38128-17" c. .-~ " ~.!!?~"0" MSM38128-18~E 10MSM38128-27J IS standard No.13418 charactersJIS standard No.13418 characters24 x 24 Ming style 128K bits 450ns max16 x 18 Gothic style 128K bits 450ns max"0 ~ " .-c.~ "MSM28101A 1J IS standard No.11 OMS max16 x 18 Gothic style 1 M bits3418 characters (16 x 18 transfer)~ 0d J IS standard No.2 1 OMS max.5E MSM28201A 116 x 18 Gothic style 1M bits3384 characters(16 x 18 transfer)ill458

-----------------------. APPLICATIONS.2. MSM38256 SE R I ES2·1 15 x 16 Font(1) Model namesMSM3B256-19-22 (four codes); JIS standard No.1 (2,965 characters) + Non-kanji (524 characters)MSM3B256-32-35 (four codes); JIS standard No.2 (3,384 characters)These models are similar in electrical characteristics to the MSM3B256 mask ROM. The CS and OE signals are activelow.(2) Split character patterns, and their storage• Split character patterns• 1•••• The character patterns are standard OK Icharacter patterns .• Each character consists of two chips.• Character data is generated at high level, andbackground data i's generated at low level.• Character data is stored in a 16 x 16 dotpattern area, left-justified.• •• StorageI #3 #4 (K - 1024)• Each group of four chips forms one set tostore about 4K characters.#1 #2/2K characters/2K characte rs#1#2#3 #4J IS standard No.1MSM38256-19MSM3B256-20 MSM38256-21 MSM38256-22J IS standard No.2MSM38256-32MSM38256-33MSM38256-35[II459

_APPLICATIONS _a_------_______________ _13) Address code conversionsThe following address code conversions are required to access character patterns with the JIS C6226 kanji code:Ii) Converting JIS standards Nos. 1 and 2 Ibyte 1 = 50H - 6FH area)C6226DROM addressConversion addressIii) Converting non-kanji and JIS standard No.2 Ibyte 1 = 70H - 74H)C6226DROM addressConversion address• Use A15 as a CE control signal because it is not supported as a ROM address. IFor further details, see the circuitexample.)m460

________________________ • APPLICATIONS.15 x 16 font circuit configuration exampleFont dataj[Byte 1 X, -XlConversionrule choice--+tString addressin a character16 bitChip1 2CE CE4J IS standardNo.1 ROMmoduleCE CE23 4J IS standardNo.2 ROMmoduleY,Q;"0oUco"0'" ~co '""0oU21H-28Hr--..Non-kanjir3,--O,--H_-_4_F_H'-f--'-1K-+-I J I S standard No. 1, ROM select50H-6FH '---JIS standardNo.170H-77HJIS standard No.2 ROM selectI "J IS standardNo.2iII461

• APPLICATIONS •• -----------------------2-1 24 x 24 Font(1 ) Model namesMSM38256-1 0~18 (nine codes); J IS standard No.1 (2,965 characters) + Non·kanji (524 characters) + Half-sizecharacters (159).MSM38256-38~46; J IS standard No.2 (3,384 characters)These models are similar in electrical characteristics to the MSM38256 mask ROM. The CS and DE signals areactive low.(2) Split character patterns, and their storage• Split character patterns• The character patterns are standard J IScharacter patterns.• Each character consists of nine chips.• Character data is generated at high level, andbackground data is generated at low level.• Storage(K = 1024)~J IS standard No.1 J IS standard No.2#1 MSM38256-10 MSM38206-38#2 MSM38256·11 MSM38256-39#3 MSM38256-12 MSM3825640#4 MSM38256-13 MSM3825641#5 MSM38256-14 MSM38256-42'-_--''-_--' __ -.r~4K characters#6 MSM38256-15 MSM38256-43#7 MSM38256-16 MSM38256-44#8 MSM38256·17 MSM3825645m#9 MSM38256·18 MSM38256-46462

----------------------____ APPLICATIONS _(3) Address code conversionsThe following address code conversions are required to access character patterns with the JIS C6226 and C6229kanji code:(i)Converting JIS standards Nos. 1 and 2 (byte 1 = 50H-6FH area)C6226ROM address A,Conversion addressYIIii)Converting non-kanji and JIS standard No.2 (byte 1 = 70H-74H area)C6226ROM address A,Conversion address Y,(iii) Converting half-size characters (C6220 code)C6220 1 z, 1z,l z.1 z, 1 z. 1 z,l Z,I z, IROM address A,Conversion address z,463

• APPLICATIONS ... -----------------------(4) 24 x 24 font circuit configuration exampleByte 1 X.-X,Byte2Y.-Y,-r-_A __ 3-__Font data )1'"2"'-47"' bict-----,1 I",..--.-'----'T:":""::"-iChip ~A_" __ ~}~~-+~:~~:~ ~}-~:-+~:~~:~String add~ess 7 8 9 L,;'---':7,.t--~8...J.--9=--.Jin a character f t --.J )J IS standard ~ J IS standard No.2Chip select No.1 ROM ROM modulemoduleHalf·size fontspecification --Y.=OL/~Half-sizeY X. -X, = " ["'\. characters--!. -----=- 21 H-':-28=-H:-++--++N:-:o-n---;-k-+an--'j~ih~ ~ li; 30H-4FH • I r JIS standard No.1~/ t;;"O ',1./ ROM select, '" 0] ~ 50H-6FH * ~- -JIS standardu"O 70H-77H '"I No.1J IS standard No.2 ROM select,J IS standardNo.2m464

OKI Electric Industry Co .. ltd.10 ~ 3 Shlbaura 4-chome. M inato -ku.Tokyo 108, JapanTel Tokyo 45 4 ~ 21 1 1Telex J22627Fax Tokyo 452 -591 2 (Gill)ElectronICS devIces Group?verseas M arketmg DeptOK I Semiconductor Group650 N Mary AvenueSunnyvale. CalIf 9408 6. USATel 408-720- 1900Tele, 9103380508 OKI SUVLFa' 408-720- 1918 IGIII!OKI Electric Europe GmbHNlederkasseler Lohweg 8D 4000 Dusseldorf 11West GermanyTel 0211-59550Telex 8584312Fa, 02 " -59'669 IGIIIIOKI Electronics (Hong Kong) ltd.16th Floor FaIrmont House.8 Colton Tree Dnve. Hong Kongrei 5 - 26311 1- 3Telex 62 4 59 OKIHK HXFa, 5 -200 1021GIIIJ