Quantifying error in dynamic power estimation of CMOS circuits ...

**Quantify ing** Error

1. Crosstalk noise. This **error** source is dist**in**ct from glitchesaris**in**g from mismatched arrival times. Capacitive coupl**in**gcan cause **power**-draw**in**g voltage glitches on a silentl**in**e. Also, a transition on a victim l**in**e may become nonmonotonedue to coupl**in**g with neighbors. In this case, thesupply has to provide more current than **in** the case **of** amonotone waveform.2. Short-circuit **power** due to crosstalk. Due to capacitive coupl**in**g,the victim receiver may spend a large (small) time **in**the middle transition region – essentially due to **in**creased(decreased) slew time – and the transition waveform may notbe monotone. This can cause a larger (smaller) short-circuit**power** dissipation **in** the victim receiver. Similarly, for thevictim driver the output transition time changes due to capacitivecoupl**in**g and can lead to **in**creased or decreased shortcircuit**power** depend**in**g on the transitions **of** the aggressors.3. Incorrect switch factors. Coupl**in**g capacitances need to betreated differently as their **power** contribution is dependenton two transitions (victim and aggressor) rather than one.The typical approach to account for coupl**in**g capacitancesis to convert them to equivalent grounded capacitances viaa switch factor or Miller factor that depends on the overlapbetween victim and aggressor switch**in**g w**in**dows as well astheir relative slew times. For delay, switch factor is typicallycomputed as 1 − ∆V aV thwhere ∆V a is the change **in** theaggressor voltage for a victim voltage sw**in**g **of** V th (typically50%V dd ) [4]. For **power** computations the switchfactor should be computed for a rail-to-rail victim sw**in**g.This means that delay-based switch factors can overestimatethe **power** consumption: −1 ≤ SF delay ≤ 3 [4, 13] while0 ≤ SF **power** ≤ 2.4. Incomplete voltage sw**in**gs. If slew times are large, thena transition may not be rail-to-rail. In this case the totalcharge drawn from supply, and hence the **power** consumption,is reduced. This consideration is even more relevantfor glitches which may not have enough time for a completesw**in**g. Glitches due to mismatched arrival times **of** **in**put signalsare modeled as logic glitches by both logic simulatorsand probabilistic techniques. This means the **power** drawnby these glitches is computed assum**in**g complete voltagesw**in**gs while **in** most cases they will be smaller than completevoltage sw**in**gs. Only simulative techniques can correctlytake **in**complete voltage sw**in**gs **in**to account. Powercalculation as outl**in**ed **in** the IEEE Delay and Power CalculationSystem [6] has function prototypes to handle partialsw**in**g events.5. Incorrect **estimation** **of** activity factors. Besides the abovementioned**error**s due to approximations, probabilistic determ**in**ation**of** activity factors suffers from **error**s due to ignor**in**g**of** neighbor**in**g transitions. Transition probabilities arefound for each gate **in** isolation while the **power** consumptionalso depends on the neighbor**in**g transitions. As a result,triplet-wise activity factors (e.g., P(000 → 011)) are requiredas opposed to gate activity factors (e.g., P(0 → 1)). Thecalculation **of** these activity factors requires consideraion **of**transitions on **in**terconnect segments rather than just gates.Moreover, switch**in**g w**in**dows and slew rates **of** the transitionsmust be taken **in**to account. **Quantify ing** this

Output W/L I Leakage )Logic-level (NMOS) (nA)0 83 221 83 120 55 151 55 8Table 1: Leakage **power** for typical global buffers used **in** our simulations.t slew W/L Avg. Curr.Transition (ps) (NMOS) (mA)D 100 55 0.085U 100 55 0.026D 200 55 0.11U 200 55 0.055D 100 83 0.126U 100 83 0.039D 200 83 0.165U 200 83 0.082Table 2: Variation **of** short-circuit **power** witht slew and device W/L. Thisis the worst-case short-circuit **power** (zero load capacitance).while L**in**e 2 is the only aggressor. 2• U represents a 0 → V dd transition on the l**in**e.• D represents a V dd → 0 transition on the l**in**e.• 0 represents a static 0 on the l**in**e.• 1 denotes a static 1 on the l**in**e.For example, 0U means that L**in**e 1 is quiet at 0V and L**in**e 2 ismak**in**g an upward transition on the **in**verter output. We measurethe average current drawn over a period **of** 1800ps on the **power**supply **of** the designated victim l**in**e; this measurement **in**terval iskept large to ensure that a rail-to-rail transition occurs. We takecharge drawn from supply as the measure **of** **power** (energy drawncan be obta**in**ed by multiply**in**g the charge drawn byV dd ).4 Assumptions and ConfirmationsThe follow**in**g basic assumptions are implicit **in** our experiments.(1) We assume that leakage and short-circuit current account foronly a small part **of** the total current drawn. Therefore, we approximatetotal current by capacitive switch**in**g current. (2) Weperform experiments with only one slew time. Then, to show thatour results are applicable for a wide range **of** slew times, we showthat the dependence **of** **power** consumption on slew time is weak.(3) F**in**ally, we model **in**terconnect by a lumped model which isalso verified to only **in**significantly affect the current drawn. Inthis section, we provide justifications for these basic assumptions.(For simplicity **of** presentation, we do not present exhaustive simulationresults, but rather show the essential (and representative)data.)Negligible Leakage Power. The leakage component **of** **power** issmall for 180nm technology but can rise rapidly **in** future technologynodes, particularly for high-performance devices as opposedto low operat**in**g-**power** or low standby-**power** devices [11]. Typicalvalues **of** leakage **power** for the **in**verters used **in** our experimentsare summarized **in** Table 1. The leakage current is 3-4 orders**of** magnitude smaller than the switch**in**g current. More important,it is **in**dependent **of** load capacitances. We therefore ignore theleakage component **of** **power** **in** all our experiments.Small and/or Constant Short-circuit Power. To measure theshort-circuit **power**, we measure the current pass**in**g through theground term**in**al **of** the driver. Table 2 tabulates worst-case (zeroload capacitance) values for short-circuit **power**; Table 3 showsthat short-circuit **power** decreases as load capacitance **in**creases.To compute the switch**in**g current (I sw ) we consider the U transitionand subtract I SC from the total current drawn. With respect2 Implicitly, this means that if there are multiple aggressors, their effects on currentdrawn can be summed.C L Avg. I SC Avg. I Total(fF) (mA) (mA)0 0.082 0.17550 0.076 0.219500 0.052 0.64Table 3: Variation **of** short-circuit **power** with load capacitance for NMOSW/L=83 and **in**put slew time=200ps. Note that typical values **of** load capacitancefor drivers **of** buffered global **in**terconnect will exceed 500fF.Input t slew (ps) Avg. Curr. (mA)50 0.73100 0.74200 0.76300 0.80Table 4: Power consumption for an uncoupled l**in**e.C g = C L = 300 fF.to Table 3, we observe that typical values **of** load capacitance fordrivers and repeaters **in** global buffered **in**terconnects are greaterthan 500fF. We further observe that (i) the dependence **of** shortcircuitcurrent on load capacitance is weak, while the switch**in**gcurrent is strongly dependent on load capacitance; and (ii) shortcircuit**power**, can be kept to less than 10% **of** total **dynamic** **power**with proper design (balanced **in**put and output slew times) [27, 20].Our experiments **in**volve the **in**put to the driver switch**in**g muchfaster than its output, result**in**g **in** very small short-circuit **power**.In light **of** these observations, we consider any variation **in** total**power** drawn from the supply to stem from switch**in**g currentalone.Independence **of** Slew Times and Power Estimation. For uncoupledl**in**es, the **power** drawn should depend only on the totalswitched capacitance. Short-circuit **power** is affected by the slewtime but, as discussed above, is a very small component **of** thetotal **dynamic** **power**. Table 4 shows the variation **of** total **power**with vary**in**g slew times for a s**in**gle uncoupled l**in**e. For coupledl**in**es, the effective coupl**in**g capacitance varies with relative slewtimes and switch**in**g w**in**dows **of** the victim and the aggressor. Ifthe aggressor signal arrives after the victim signal, then the effectivecapacitance is almost **in**dependent **of** the slew time, so that**power** is only weakly dependent on slew times. This phenomenonis exam**in**ed **in** greater depth **in** Section 5.2. Table 5 shows resultswith total coupl**in**g capacitance C c = C g +C L = 600 fF, where C gand C L are total ground and load capacitance respectively. We seethat the **power** depends on transition time but not on slew time;thus, below we use only one slew time (100ps) to quantify **error**s**in** **power** **estimation**.Little Effect **of** Distributed Nature **of** Interconnect. S**in**ce the**power** consumption depends only on the total capacitance, it is **in**dependent**of** the **in**terconnect resistance. For an uncoupled l**in**ethere is no effect **of** its distributed nature on **power**. For a coupledl**in**e, there is a small impact **of** its distributed nature: slew timesand arrival times will differ along the aggressor and victim l**in**es,lead**in**g to different switch factors along the victim l**in**e. Table 6compares the **power** consumption **in** a distributed versus lumpedcoupled **in**terconnect. TheUU case, which essentially correspondsto an uncoupled **in**terconnect, shows almost no effect **of** distributionwhile other cases show close to 1% effect. We are concernedtslew Victim (ps) t Aggressorslew (ps) Transition Victim Curr. (mA)100 100 U0 1.3350 100 U0 1.31100 100 UD 1.9150 100 UD 1.90100 100 UU 0.7350 100 UU 0.72Table 5: Power consumption for a coupled l**in**e. Victim and aggressorarrival times are assumed to be equal.Proceed**in**gs **of** the Fourth International Symposium on Quality Electronic Design (ISQED’03)0-7695-1881-8/03 $17.00 © 2003 IEEE

Avg. Curr. (mA)No. **of** SegmentsTransition 1 2 10 20UU 0.731 0.730 0.728 0.728U0 1.307 1.322 1.324 1.324UD 1.884 1.914 1.921 1.921Table 6: Power consumption **in** the victim l**in**e **of** a 2-l**in**e coupled **in**terconnectsystem, shown versus the number **of** segments used **in** the lumpeddistributedmodel.Transition t clock (ps) Energy total (pJ)U0 600 3.79U0 1200 4.24U0 1800 4.29UU 600 2.33UU 1200 2.36UU 1800 2.36UD 600 5.20UD 1200 6.12UD 1800 6.22Table 7: Total energy drawn fromV dd for various transitions with vary**in**gmeasurement **in**tervals. The clock period corresponds to the measurement**in**terval **of** the current. The **in**put slew **in** all the cases is 100ps.with the relative rather than the absolute difference between theUU,U0,UD cases, and our experiments show that this relativedifference rema**in**s almost constant, with or without distribution.Therefore, for simplicity **of** analysis, we use a lumped **in**terconnectmodel for **power** computation. 35 Experimental ResultsWe now seek to quantify the sources **of** **error**s listed **in** Section 2.S**in**ce logic simulation and probabilistic **estimation** **of** switch**in**gprobabilities is beyond the scope **of** this work, we do not presentany results for **error**s 5, 7 and 8 from Section 2. Errors 7 and 8are **in**dependent **of** other **error**s, hence the **in**accuracy due to themwould be beyond any **error** calculated **in** this and the next section.To model **error** 5, we consider expected and worst-case values **of**activity factors **in** Section 6.5.1 Incomplete Voltage Sw**in**gsPartial voltage sw**in**gs can occur if the slew time is large relativeto the clock period. We use a distributed **in**terconnect for this experiment.Table 7 shows the impact **of** clock period on **power** consumption.The UD transition has the largest slew time and thereforerequires more time for the victim transition to settle. Givengood design practices for high-performance designs, the clock periodis about 6 times the **in**put rise time [8]. Therefore, we canconsider the values given **in** Table 7 to represent the energy drawnfor the driver switch**in**g every one (600ps measurement **in**terval),two (1200ps) or three (1800ps) clock cycles. These correspond toaverage activity factors **of** 0.5, 0.33 and 0.25 respectively. 4 If weassume an activity factor **of** 0.15, as **in** the high-performance MPUmodel **of** the 2001 ITRS [11], this **error** becomes essentially negligible.Note that **in** case **of** glitches, the problem **of** partial sw**in**gswould be more pronounced as they are usually short-last**in**g, transientswitch**in**g events. Subject to our ignor**in**g glitch**in**g **in** ouranalysis, we can conclude: The effect **of** **in**complete voltage sw**in**gsis negligible for designs with typical activity factors.5.2 Incorrect Switch FactorsFor delay analyses, the appropriate switch factor is typically computedas [4]SF delay = 1 − ∆V a∆V v(1)3 The lumped **in**terconnect model will overestimate the receiver short-circuit**power** and underestimate driver short-circuit **power**. We ignore this effect becauseshort-circuit **power** is a small component **of** the total **power**.4 Note that a more accurate probabilistic analysis may be performed, as **in** Section6 below, but the impact **of** partial sw**in**g events is likely to be small. Hence, we do notgive a detailed analysis here.Switch Factor for **power**3210−200 −100 0 100 200Victim arrival − Aggressor arrival (ps)Figure 1: Variation **of** SF **power** with the difference between victim and aggressorarrival times. Both victim and aggressor have slew times **of** 100psat the coupl**in**g po**in**t; the l**in**es transition **in** opposite directions.where ∆V a is the change **in** the aggressor voltage for a victim voltagesw**in**g **of** ∆V v (typically 50% **of** V dd )[4]. For **power** computationsthe switch factor should be computed for a threshold **of**100% **of** V dd . Moreover, if the aggressor transition starts after thevictim transition and the clock period is large enough, the victimwill always “see” almost the complete aggressor transition s**in**cethe theoretical 100% threshold delay for an RC network is ∞ andthe voltage waveforms have a “knee” beyond which slope **of** thecurve is very small. Therefore, if the aggressor and victim kneepo**in**ts lie with**in** the clock period and the aggressor signal arrivesafter the victim, we will have SF **power** ∈{0,1,2}. The switch factorfor **power** (UD transition) can hence be approximated bySF **power** = 1 +(1 − tA v −tA ataR ) ∀tv A ≥ taA2 otherwise (2)where tv A and ta A are the arrival times for victim and aggressor, andta R denotes the slew time **of** the aggressor. For the UU transition,the expression for switch factor isSF **power** = 1 − (1 − tA v −taAtaR ) ∀tv A ≥ tA a0 otherwise (3)and when the aggressor is quiet,SF **power** = SF delay = 1 (4)For our experiments, we def**in**e the follow**in**g terms.• Measured SF delay : This is the SF computed experimentallysuch that the delays **in** the coupled and decoupled cases arethe same.• Theoretical SF **power** : This is the SF computed accord**in**g toEquations (2), (3) and (4). As we will see, this accuratelymodels the **power** consumption.Table 8 shows the results for a set **of** simulations for a two-l**in**esystem. Variation **of** SF **power** with the difference between victimand aggressor arrival times is shown **in** Figure 1. From Table 8,we can conclude: Us**in**g delay-based switch factors for ground**in**gcoupl**in**g capacitances **in** **power** calculations leads to **estimation****error**s; furthermore, the proposed **power**-based switch factors accuratelymodel coupl**in**g capacitances for **power** analysis.5.3 Crosstalk Noise PowerA transition**in**g aggressor can cause a **power**-consum**in**g glitch ona quiet victim l**in**e. Moreover, as mentioned above, if the victimtransition is non-monotone, the total charge drawn is greaterthan CV s**in**ce the victim driver has to pull up the switched capacitanceby more than V dd . Capacitive coupl**in**g can cause suchProceed**in**gs **of** the Fourth International Symposium on Quality Electronic Design (ISQED’03)0-7695-1881-8/03 $17.00 © 2003 IEEE

Coupled L**in**es Measured SF delay Theoretical SF **power**Transition Delay (ps) Avg. Curr.(mA) Value Delay (ps) Avg. Curr.(mA) Value Delay (ps) Avg. Curr.(mA)UD 343 1.87 1.7 342 1.72 2 377 1.88UU 214 0.74 0.6 215 1.09 0 145 0.73UD 391 1.88 2.15 393 1.95 2 377 1.88UU 159 0.73 0.15 162 0.82 0 145 0.73Table 8: Switch factor based **estimation** **of** **power**.Victim W/L C c Peak Avg. Curr.(NMOS) (fF) Noise (V) (mA)83 600 0.35 0.578110 600 0.34 0.58083 300 0.23 0.298110 300 0.22 0.298Table 9: Crosstalk noise **power** for the 1D transition.Transition Probability SF**power**ExpectedU0 A(1 − 2A) 1UU A 2 0.25UD A 2 1.75A(1−2A)1D2 + A2 4 0Table 10: Probabilities **of** transition and expectedSF **power** for a given averageactivity factor A.non-monotone transitions. It is difficult to estimate the **power** consumedby such non-monotonicity. Here, we estimate crosstalknoise pulse **power** on a quiet victim only. We consider only the1D transition to be **power**-consum**in**g (draw**in**g current from V dd ,and ignore all other glitches. 5 Compar**in**g values **of** current **in** Table9 with the current drawn for normal logic transitions **in** Table6, we easily conclude: Power consumption due to crosstalk noiseglitches is significant and cannot be ignored **in** **power** calculation.6 Extrapolat**in**g to Full Chip Error EstimateIn this section we give an estimate **of** cumulative **error** **in** **power****estimation**, extrapolated to the whole chip. We stress that this is arough estimate **in** that it does not take **in**to account any switch**in**gcorrelations, and assumes an average activity factor. On the otherhand, our estimate po**in**ts out the significance **of** the **error** sourcesthat we have analyzed above.From the previous sections we may derive an estimate **of** expected**error** for each **of** the **power** consum**in**g transitions (i.e.,U0,UU,UD and 1D 6 ). The basel**in**e **power** is calculated assum**in**ga U0 transition with zero crosstalk noise **power**. As **in** [8, 11],we assume a given average activity factor A. A corresponds tothe averaged transition probability for the 0 → 1 transition. Then,the probabilities **of** transition pairs are as given **in** Table 10. Notethat these probability values are derived assum**in**g spatial and temporal**in**dependence. Table 10 also also gives the correspond**in**gexpected value **of** SF **power** , assum**in**g a uniform distribution **of** relativearrival times **of** the aggressor and the victim. Note that theentry 1D **in** the table corresponds to crosstalk glitches, and we alsotake **in**to account partial glitches when the aggressor arrives beforethe victim **in** the UD case (the aggressor must be transition**in**gdown for the victim to draw **power**). The amplitude **of** the partialglitch is assumed to be proportional to the difference between aggressorand victim arrival times. The expected switch factors **of**0.25 and 1.75 and partial glitch probability **of** A 2 /4 are calculatedassum**in**g the clock period is not much larger than the sum **of** slewtimes **of** victim and aggressor. If the clock period is large, then thecorrespond**in**g values would be 0.5, 1.5 and A 2 /2.For each **of** the transitions, **error** **in** short-circuit **power** mayalso be taken **in**to account. An average-case analysis based onTable 10 yields a very small **error** **in** **power** **estimation** (essentiallydue to crosstalk noise **power**). Similarly, a worst-case analysiscan be performed. The highest **power** consumption **in**volves allU transitions correspond**in**g to UD transitions, while the lowest**power** consumption occurs with all transitions be**in**g UU. Thus, a5 Four transitions 1D,0D,0U,1U can cause glitches. The 0U,1U glitches do notdraw any **power** from the victim supply: an 0U transition causes current to flow tovictim ground through the NMOS while a 1U transition causes current to flow tovictim supply through the PMOS. In the 0D case, current is drawn from the victimground through the NMOS while **in** case **of** 1D glitch, **power** is drawn from the victimsupply through the PMOS. We therefore consider only the 1D transition as **power**consum**in**g.6 We may assume that U1 is subsumed by U0.guardband**in**g range can be constructed. In the follow**in**g, we tryto derive some crude values for **power** consumption with variouslevels **of** accuracy. 7• Conventional non-coupl**in**g aware **estimation**. In this case,coupl**in**g capacitance is treated as ground capacitance withswitch factor **of** 1, i.e.,P conventional = A(C g +C c +C L )V 2 dd (5)• Expected coupl**in**g “aware” **estimation**. This uses either simulationor correct switch factors but ignores crosstalk noise.If we assume neighbor switch**in**g to be completely **in**dependent,we end up with transition probabilities as **in** Table 10.In this case coupl**in**g-aware **power** is the same as the conventional**power** estimate.P coupled = A(C g +C c +C L )V 2 dd (6)• Correct noise-aware estimate. This takes crosstalk glitches**in**to account. It can be approximated asA(1 − 2A)P correct = P conventional +( + A22 4 )P noise (7)• Worst-case estimate. This assumes all U transitions to be UDand all D transitions to be DU. I.e.,P WC = A(C g + 2C c +C L )Vdd 2 (8)• Best-case estimate. This assumes all U transitions to be UUand all D transitions to be DD. I.e.,P BC = A(C g +C L )V 2 dd (9)Assum**in**g A = 0.15 [8, 11] and other values from Sections 5 and4, we get the follow**in**g: 8• We calculate expected **error** as P correct −P conventionalP conventional. From Section5 and Equations (5), (7) we estimate this **error** to be+18%. I.e., conventional **power** **estimation** techniques arelikely to underestimate **power** consumption.• We calculate worst-case **error** as P WC−P conventionalP conventional. From Section5 and Equations (5), (8) we estimate this **error** to be+50%.• Best-case **error** is calculated as P BC−P conventionalP conventional. From Section5 and Equations (5), (9), we **in**fer that the conventional **power****estimation** techniques can overestimate by 50%.7 We assume just one aggressor. The worst (and best) case effect **of** two or moreaggressors can be modeled by simply scal**in**g the coupl**in**g capacitance and assum**in**gvalidity **of** l**in**ear superposition.8 A positive **error** means under**estimation** by the conventional methods, while anegative **error** means over**estimation**.Proceed**in**gs **of** the Fourth International Symposium on Quality Electronic Design (ISQED’03)0-7695-1881-8/03 $17.00 © 2003 IEEE

The above analysis not only suggests that certa**in** guardband**in**gmay be necessary **in** **power** **estimation**, but also guides such guardband**in**g.For example, the above analysis specifically implies thatguardband**in**g the conventional **power** estimate by +18% will leadto zero expected **error**, 27% worst-case **error** and -58% best case**error**.7 Conclusions and Future WorkWe have shown that current **power** **estimation** methods suffer fromvarious **in**accuracies which can result **in** over 50% **error** **in** **estimation**.In the absence **of** switch**in**g correlations (which are hardto compute), the expected **power** estimate given **in** Section 6 canbe used to give more accurate results without be**in**g as pessimisticas the worst-case estimate. Of course, **power** **estimation** **error**scan result from various sources other than the ones highlighted**in** this work (e.g., parasitic extraction, **in**put pattern dependence,etc.). The values **of** the **error**s given above assume zero **error** fromthese “other” sources. We have also given expressions for **power**basedswitch factors as dist**in**ct from delay-based switch factors.These switch factors should be used when coupl**in**g capacitancesare grounded for **power** computation purposes.There are several **in**terest**in**g implications **of** the work that wehave reported, notably the large impact **of** coupl**in**g on **power** consumption.1. All coupl**in**g delay reduction techniques (segment permutation,repeater stagger**in**g, etc.) are also applicable for **power**optimization. Moreover, s**in**ce there is no parallel for holdtimeviolations **in** **power**, any approach which reduces delaydue to coupl**in**g strictly improves **power** consumption. Dueto coupl**in**g, there is a direct correspondence between delayuncerta**in**ty and **power** uncerta**in**ty.2. Reduc**in**g switch**in**g activity factor may not always reduce**power** consumption. To see this, consider the example **of**2n parallel l**in**es coupled along their entire length to theirimmediate neighbors. As **in** our experiments assume C c =C g + C L = C. Now we compare two transitions U0U0..and UUUU.... The first transition draws **power** P U0 =(3n−1)CV 2 while the second transition draws **power** P UU =2nCV 2 . Further assume that all odd-**in**dexed l**in**es (start**in**gfrom 1) have an activity factor A 1 while all even-**in**dexedl**in**es (start**in**g from 2) have an activity factor A 2 . Also assumethat switch**in**g activities are correlated such that a Utransition occurs on any even-**in**dex l**in**e only when aU transitionoccurs on the neighbor**in**g odd-**in**dex l**in**es. 9 Thus,A 1 > A 2 . The **power** consumption **of** the n-l**in**e system is thengiven by P = A 2 P UU +(A 1 − A 2 )P U0 + A 1 (A 1 − A 2 )P noise .Clearly, **in**creas**in**g A 2 decreases **power** consumption until wereach A 2 = A 1 .3. The fact that a major component **of** **power** comes from**in**terconnect capacitance suggests renewed attention towirelength- and activity-driven layout methodologies to optimize**power**. The goal **of** rout**in**g the most frequently switch**in**gnets with smallest wirelengths has been well-understoodfor the past decade, but the relative significance **of** such anobjective **in**creases with technology scal**in**g.Our ongo**in**g and future work **in**cludes the follow**in**g.• Estimation **of** **power** for non-monotone transitions, whichwas ignored **in** the crosstalk glitch **power**.• Estimation **of** **error** **in** short-circuit **power** **estimation**. We expectthis **error** to be small as short-circuit current itself canbe limited to small values by proper design.• Assessment **of** crosstalk glitches, which can also cause an**in**crease **in** receiver short-circuit **power** if the amplitude **of**the glitch exceeds transistor threshold voltages. This effect9 Note that this implicitly assumes that all odd-**in**dexed l**in**es switch together, as doall even-**in**dexed l**in**es.is likely to be small as the glitches are usually not **of** highamplitude.• Account**in**g for all crosstalk glitch transitions. Currently, wejust consider the 1D transition as the **power** consum**in**g transition.This needs to be verified with respect to, e.g., 1Utransitions driv**in**g **power** to the supply or **power** be**in**g drawnfrom ground **in** the 0D case. 108 AcknowledgmentsWe thank Pr**of**essor Dennis Sylvester **of** the University **of** Michiganat Ann Arbor for his cont**in**uous help and guidance dur**in**g thecourse **of** this work. We also thank Dr. Tak Young **of** MontereyDesign Systems for provid**in**g valuable **in**put and review**in**g severalprevious drafts.References[1] D. Blaauw, A. Dharchoudhury, R. Panda, S. Sirichotiyakul, C. Oh and T. Edwards,“Emerg**in**g **power** management tools for processor design”, Proc. InternationalSymposium on Low Power Electronics and Design, 1998, pp. 143-148.[2] ”Berkeley Predictive Technology Model”, http://wwwdevice.eecs.berkeley.edu/∼ptm/[3] A.P. Chandrakasan and R.W. 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Veendrick, “Short-Circuit Dissipation **of** Static **CMOS** Circuitry and ItsImpact on the Design **of** Buffer Circuits”, IEEE Journal **of** Solid State Circuits19(4) (1984), pp. 468-473.10 For **in**stance, consider the 1U transition. If the victim is be**in**g held high and aneighbor**in**g wire goes high as well, positive charge is **in**jected across the coupl**in**gcap (displacement current) which temporarily causes the victim voltage to exceedV dd . The PMOS driver **of** the victim then removes this charge by conduct**in**g currents**in**ce it sees a non-zero V ds .Proceed**in**gs **of** the Fourth International Symposium on Quality Electronic Design (ISQED’03)0-7695-1881-8/03 $17.00 © 2003 IEEE