Cache Usage Tutorial - MGNet

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Typical architectures IBM Power 3:• L1 = 64 KB, 128-way set associative (funny definition, however)• L2 = 4 MB, direct mapped, line size = 128, write back IBM Power 4 (2 CPU/chip):• L1 = 32 KB, 2-way, line size = 128• L2 = 1,5 MB, 8-way, line size = 128• L3 = 32 MB, 8-way, line size = 512 Compaq EV6 (Alpha 21264):• L1 = 64 KB, 2-way associative, line size= 32• L2 = 4 MB (or larger), direct mapped, line size = 64 HP PA-RISC:• PA8500, PA8600: L1 = 1.5 MB, PA8700: L1 = 2.25 MB• no L2 cache!Prof. Craig C. DouglasUniversity of Kentucky andYale UniversityHiPC2003, 12/17/2003 vHPC <strong>Cache</strong> Aware Methods 24
Typical architectures (cont’d) AMD Athlon (from “Thunderbird” on):• L1 = 64 KB, L2 = 256 KB Intel Pentium 4:• L1 = 8 KB, 4-way, line size = 64• L2 = 256 KB up to 2MB, 8-way, line size = 128 Intel Itanium:• L1 = 16 KB, 4-way• L2 = 96 KB, 6-way• L3: off-chip, size varies Intel Itanium 2 (McKinley / Madison):• L1 = 16 / 32 KB• L2 = 256 / 256 KB• L3: 1.5 or 3 / 6 MBProf. Craig C. DouglasUniversity of Kentucky andYale UniversityHiPC2003, 12/17/2003 vHPC <strong>Cache</strong> Aware Methods 25
Page 4 and 5: Part IArchitectures and Fundamental
Page 6 and 7: How fast should a solver be?(just a
Page 8 and 9: Comparison of solvers(what got me s
Page 10 and 11: PipeliningProf. Craig C. DouglasUni
Page 12 and 13: CPU trendsEPIC (similar to VLIW) (I
Page 14 and 15: Memory acceleration techniquesInter
Page 16 and 17: CachesFast but small extra memoryHo
Page 18 and 19: Cache issuesUniqueness and transpar
Page 20 and 21: Effect of cache hit ratioThe cache
Page 22 and 23: Cache organizationNumber of cache l
Page 26 and 27: Basic efficiency guidelinesChoose t
Page 28 and 29: Choose the best algorithm(cont‘d)
Page 30 and 31: Sources for librariesVendor-indepen
Page 32 and 33: Find good compiler optionsModern co
Page 34 and 35: Use suitable data layoutAccess memo
Page 36 and 37: ProfilingSubroutine-level profiling
Page 38 and 39: Profiling: hardware performancecoun
Page 40 and 41: Profiling tools: valgrindMemory/thr
Page 42 and 43: Profiling tools: PAPIPAPI = Perform
Page 44 and 45: hpcview Screen ShotProf. Craig C. D
Page 46 and 47: HPCToolkit Philosophy 2Provide info
Page 48 and 49: Our reference code2D structured mul
Page 50 and 51: Using PCL - Example 1Digital PWS 50
Page 52 and 53: Using PCL - Example 2PCLinit(&descr
Page 54 and 55: Examples of DCPI toolsdcpiwhatcg: W
Page 56 and 57: Using DCPI - Example 2Call the DCPI
Page 58 and 59: Using DCPI - Example 2Static stalls
Page 60 and 61: Part IIOptimization TechniquesforSt
Page 62 and 63: Optimization ofFloating-PointOperat
Page 64 and 65: Loop unrollingSimplest effect of lo
Page 66 and 67: Loop unrolling:Improving flop/load
Page 68 and 69: Fused Multiply-Add (FMA)On many CPU
Page 70 and 71: Exposing ILP (cont’d)Superscalar
Page 72 and 73: AliasingArrays (or other data) that
Page 74 and 75:
Aliasing (cont’d)Aliasing is lega
Page 76 and 77:
Eliminating overheads:if statements
Page 78 and 79:
Eliminating loop overheadsFor start
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Eliminating subroutine callingoverh
Page 82 and 83:
Data layout optimizationsArray tran
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Data layout optimizationsStride-1 a
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Data layout optimizations:Cache-awa
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Data layout optimizations:Array pad
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Data layout optimizations:Array pad
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Loop optimizationsLoop unrolling (s
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Data access optimizations:Loop fusi
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Page 98 and 99:
Page 100 and 101:
Page 102 and 103:
Data access optimizations:Loop spli
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Data access optimizations:Loop bloc
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Data access optimizations:Loop bloc
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Data access optimizationsLoop block
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Two common multigridalgorithmsV Cyc
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DiMEPACK libraryC++ interface, fast
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Example:Cache-OptimizedMultigrid on
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Data layout optimizationsfor 3D mul
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Data layout optimizationsfor 3D mul
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Data access optimizationsfor 3D mul
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Example:Cache Optimizations forthe
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LBM (cont‘d)Stream: read distribu
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Layout 2: Grid Compression: save me
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3-way blocking (cont’d):Prof. Cra
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4-way blocking (cont’d):Prof. Cra
Page 132 and 133:
Layout: Grid compression, access pa
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Performance resultsMFLOPS for 2D GS
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Memory access behaviorStandard impl
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Memory access behavior2D skewed blo
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Performance results (cont’d)2D LB
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Performance results (cont’d)3D LB
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C++-specific considerationsWe will
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Inlining (cont‘d)Advantages:• R
Page 148 and 149:
Inlining virtual functionsVirtual f
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ExampleDefine a simple vector class
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Example (cont‘d)Need a wrapper cl
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Example (cont‘d)Need overloaded o
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Part IIIOptimization Techniques for
Page 158 and 159:
Is It really unstructured?This is r
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Motivating example• Suppose probl
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Cache aware Gauss-SeidelPreprocessi
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Example of subblock membershipCache
Page 166 and 167:
Standard Gauss-SeidelThe complexity
Page 168 and 169:
Cache boundaries connectedProf. Cra
Page 170 and 171:
Physical boundaries unknownProf. Cr
Page 172 and 173:
Physical boundaries knownProf. Crai
Page 174 and 175:
Physical boundaries knownThe comple
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Preprocessing costsPessimistic (nev
Page 178 and 179:
Numerical experiments: BavariaExper
Page 180 and 181:
Implementation detailsOne parameter
Page 182 and 183:
Journal articles C.C. Douglas, Cach
Page 184 and 185:
Conference proceedingsC. Weiss, W.
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Cache Usage Tutorial - MGNet

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