Gen2DSP: A Green DSP for DECT and VoIP - Hardware Conference
Gen2DSP: A Green DSP for DECT and VoIP - Hardware Conference
Gen2DSP: A Green DSP for DECT and VoIP - Hardware Conference
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<strong>Gen2<strong>DSP</strong></strong>:A <strong>Green</strong> <strong>DSP</strong> <strong>for</strong> <strong>DECT</strong> <strong>and</strong> <strong>VoIP</strong>Wessel LubberhuizenJune 17, 2010
SiTel at a glanceThe first choice IC supplier <strong>for</strong>Cordless communications <strong>and</strong> <strong>VoIP</strong>• Fabless model, using st<strong>and</strong>ard 0.16µ CMOS• Lowest BOM; Highest integration• Key customers: Gigaset, Panasonic, Microsoft• Key suppliers: UTAC, TSMC
Application SegmentsWSN<strong>VoIP</strong> PhonesCAT-iq in IAD xDSL-BoxGame Controllers<strong>DECT</strong> <strong>and</strong> DCT1992 2005 2006 2008 20092010
Unique Strengths <strong>VoIP</strong>• Audio quality, especially h<strong>and</strong>s-free• Integrated <strong>DECT</strong>• µClinux based• All software in source code• Power efficiency
Global Enterprise <strong>VoIP</strong> Semiconductors<strong>Green</strong> Excellence in ProductInnovation AwardPresented toSiTel Semiconductor B.V.
<strong>VoIP</strong> Phone Power UsageSitel SC14452Sitel SC14450Snom 320Snom 360Snom 300Thomson ST2030-EU-S-MetallPolycom Soundpoint IP 330Polycom Soundpoint IP 430Snom 370Cisco IP 7911Polycom Soundpoint IP 320Gr<strong>and</strong>stream GXP 2020Gr<strong>and</strong>stream GXP 2000Aastra 53iThomson ST2022-EU-S-MetallPolycom Soundpoint IP 601Aastra 55iPolycom Soundpoint IP 550Polycom Soundpoint IP 650Cisco IP 7941Aastra 57iLinksys SPA942Linksys SPA962Polycom Soundpoint IP 670Cisco IP 79700 1 2 3 4 5 6 7Power (Watt)
RegulationsProposal of European Commission Regulation on Ecodesign:(Implementing Directive 2005/32/EC)- Limiting the st<strong>and</strong>by power consumption- 2 W if the device has a display- 1 W otherwise.- A future second phase:- 1 W if the device has a display- 0.5 W otherwise- Similar proposals in US.
Power BreakdownPower(mW)400350300250200150100500IdleActiveIOCoreEthernet
Ethernet power usage
Energy Efficient Ethernet
Energy Efficient Ethernet
SC14452
Signal Processing FunctionsSpeech / Audio Codecs• G.711 (A-Law / u-Law, 64 kbit/s)• G.726 (ADPCM, 32 kbit/s)• G.722 (SB-ADPCM, 32 kbit/s, Wideb<strong>and</strong> audio)• G.729 A+B (CS-ACELP, 8 kbit/s)• iLBC (Internet Low Bitrate Codec, 15.2 kbit/s)• MP3 (streaming music)Packet Loss ConcealmentFiltering• FIR• IIREcho Cancellation
Key Per<strong>for</strong>mance IndicatorsCheapDedicated hardwareFastDevelopmentHighPer<strong>for</strong>mance
Key Per<strong>for</strong>mance IndicatorsCheapApplicationProcessorFastDevelopmentHighPer<strong>for</strong>mance
Key Per<strong>for</strong>mance IndicatorsCheap<strong>DSP</strong> processorFastDevelopmentHighPer<strong>for</strong>mance
Target Compiler TechnologiesPioneer <strong>and</strong> leading provider of EDA tools <strong>for</strong> application-specificprocessors (ASIPs)Worldwide activities• HQ in Leuven, Belgium• US office in Boulder, Colorado• Representation in Japan (Innotech) <strong>and</strong> Korea (Acetronix)Incorporated in 1996, spin-off of IMECIndependently owned, profitable company
ASIPs in Multi-Core SoCASIP: Application-Specific Processor Anything between general-purpose µP <strong>and</strong> hardwired data-path Flexibility through programmability <strong>and</strong> design-time reconfigurability High throughput, low energy through parallelism <strong>and</strong> specializationASIP is foundation of heterogeneous multi-core SoC Balanced SoC architecture offers best per<strong>for</strong>mance at lowest energy <strong>and</strong> lowest cost
IP Designer Tool Suite
<strong>Gen2<strong>DSP</strong></strong> ArchitecturepointersdataP0P1P2P3P4P5P6 = MdD1D3D5D7D9D11D0D2D4D6D8D10L0L1L2L3ProgramRAMProgramROMP7 = SPACUMacAluCNDLFLRILRPCPCULC0LS0LE0LC1LS1LE1DataRAMIM IREQ IE STAT
<strong>Gen2<strong>DSP</strong></strong> - MacAluin1in2in3in4321632P0P1P2P3P4P5P6 = MdP7 = SPACUmultDataRAMnormalignfrac/intshifterD1D3D5D7D9D11roundingcnstD0D2D4D6D8D10MacAluL0L1L2L3AddSubCNDLFLC0LC1masksaturationExecutes in Single cycle – 80+ MhzProgramRAMProgramROMin1LRin3ILRLS0LS1PCPCULE0LE1IM IREQ IE STAT
<strong>Gen2<strong>DSP</strong></strong> - ACUP /S Pa d dP /S PStm o d u l oM dO fb i t re va d ds hR A Ma d d r
Very Long Instruction WordArchitectureSimultaneous execution of functions:A=A+B*C,B=mem[P+ 2*Q], Q=(Q++)%Rdata pointer pointermultiplication shift incrementaddition addition modulosaturationload mem
Pipelined executionIFInstruction FetchIDInstruction DecodeE1Execution Stage 1E2Execution Stage 2
Pipelined ExecutionCyclesPipeline StageIF 1 IF 2 IF 3 IF 4ID 1 ID 2 ID 3 ID 4E1 1 E1 2 E1 3 E1 4E2 1 E2 2 E2 3 E2 4
<strong>Gen2<strong>DSP</strong></strong> – Instruction Set01010111MacAluAcu - RAMControl110 Acu - RAM MacAlu110111 Control MacAlu1110111101110001110MacAlu – 2Acu - RAM 2Control 2Mixed 16 <strong>and</strong> 32 bit instruction set(previous generation 62 bits)
CPU Load2520MIPS1510<strong>Gen2<strong>DSP</strong></strong>C54xC55x50G.711 G.726 G.722 G.729AB iLBC AES
Power optimizations• Sleep mode• Frequency scaling (PLL – XTAL)• Manual clock gating• Automatic clock gate insertion
Power efficiency0,80,70,6mW / MHz0,50,40,30,20,10C55041.05V<strong>Gen2<strong>DSP</strong></strong>1.80VC55101.60VC54021.80V
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