Mentor Graphics ASIC Design Flow

VLSI/FPGA 

Design and Test Flow with 

Mentor Graphics CAD Tools 

Victor P. Nelson

Mentor Graphics CAD Tool Suites 

�� IC/SoC IC/ SoC design flow 1 

�� DFT/BIST/ATPG design flow 1 

�� FPGA design flow 2,3 

�� PCB design flow 2 

�� Digital/analog/mixed-signal Digital/analog/mixed signal modeling & simulation 1,2 

�� ASIC/FPGA synthesis 1,2 

�� Vendor-provided Vendor provided (Xilinx,Altera,etc 

( Xilinx,Altera,etc.) .) back end tools 2 

1. User-setup User setup selection: eda/mentor/ICFlow2006.1 

2. User-setup User setup selection: eda/mentor/EN2002.3 

3. User-setup User setup selection: eda/mentor/FPGA 

eda/mentor/FPGA

Mentor Graphics CAD Tools 

(select “eda eda/mentor /mentor” in user-setup user setup on the Sun network*) 

ICFlow2006.1–– For For custom custom & & standard standard cell cell IC IC designs designs 

– IC flow tools (Design (Design Architect--IC, Architect IC, IC IC Station, Station, Calibre)) Calibre 

– Digital/analog/mixed simulation ((Modelsim,ADVance 

– HDL Synthesis (Leonardo) (Leonardo) 

– ATPG/DFT/BIST tools (DFT (DFT Advisor, Advisor, Flextest, Flextest, 

Fastscan)) Fastscan 

– Limited access to Quicksim II (some (some technologies) 

technologies) 

EN2002u3 –– For For FPGA FPGA ““front front end”” end design design & & printed printed circuit circuit boards boards 

– Design Architect, Quicksim II, Quicksim Pro (Schematic/Simulation) 

– ModelSim & Leonardo (HDL (HDL Simulation/Synthesis) 

– Xilinx ISE & Altera “Quartus Quartus” tools (Back (Back end end design) design) 

�� ICFlow2006.1 

�� EN2002u3 

FPGA (FPGA (FPGA Advantage, Advantage, Modelsim, Modelsim, 

Leonardo) Leonardo) 

�� FPGA 

Modelsim,ADVance MS,Eldo,MachTA)) 

MS,Eldo,MachTA 

*Only *Only one one of of the the above above three three groups groups may may be be selected selected at at a a time 

time

Mentor Graphics ASIC Design Kit (ADK) 

�� Technology files & standard cell libraries 

– AMI: ami12, ami05 (1.2, 0.5 μm) m) 

– TSMC: tsmc035, tsmc025, tsmc018 (0.35, 0.25, 0.18 μm) m) 

�� IC flow & DFT tool support files: 

– Simulation 

�� VHDL/Verilog 

VHDL/ Verilog/Mixed /Mixed-Signal Signal models ((Modelsim/ADVance 

Modelsim/ADVance MS) MS) 

�� Analog (SPICE) models ((Eldo/Accusim 

Eldo/Accusim)) 

�� Post-layout Post layout timing (Mach (Mach TA) TA) 

�� Digital schematic (Quicksim Quicksim II, II, Quicksim Quicksim Pro) Pro) (exc. tsmc025,tsmc018) 

– Synthesis to std. cells ((LeonardoSpectrum 

LeonardoSpectrum)) 

– Design for test & ATPG (DFT (DFT Advisor, Advisor, Flextest/Fastscan)) 

Flextest/Fastscan 

– Schematic capture (Design (Design Architect--IC) 

Architect IC) 

– IC physical design (standard cell & custom) 

�� Floorplan, Floorplan, 

place & route (IC (IC Station) Station) 

�� Design rule check, layout vs schematic, parameter extraction ((Calibre Calibre))

Xilinx/Altera 

Xilinx/ Altera FPGA/CPLD Design 

�� Technology files & libraries for front-end front end design with 

Mentor Graphics tools 

– Schematic symbols for Design Design Architect Architect 

– Simulation models for Quicksim Quicksim II, II, Quicksim Quicksim Pro Pro 

– Synthesis library for Leonardo Leonardo 

�� Vendor tools for back-end back end design 

(map, place, route, configure, timing) 

– Xilinx Integrated Integrated Software Software Environment Environment (ISE) 

�� Xilinx XST can synthesize the design from VHDL or Verilog (instead 

of Leonardo) 

– Altera Quartus Quartus II II & & Max+Plus2 

Max+Plus2

DFT/BIST 

& ATPG 

Test vectors 

Standard Cell IC 

& FPGA/CPLD 

DRC & LVS 

Verification 

ASIC Design Flow 

Synthesis 

Behavioral 

Model 

VHDL/Verilog 

Gate-Level 

Netlist 

Transistor-Level 

Netlist 

Physical 

Layout 

Map/Place/Route 

Full-custom IC 

IC Mask Data/FPGA Configuration File 

Verify 

Function 

Verify 

Function 

Verify Function 

& Timing 

Verify 

Timing

Behavioral Design & Verification 

VHDL 

Verilog 

SystemC 

(mostly technology-independent) 

technology independent) 

ModelSim 

(digital) 

Leonardo 

Spectrum 

(digital) 

Create Behavioral/RTL 

HDL Model(s) 

Simulate to Verify 

Functionality 

Synthesize Gate-Level 

Circuit 

Post-Layout Simulation, 

Technology-Specific Netlist 

to Back-End Tools 

VHDL-AMS 

Verilog-A 

ADVance MS 

(analog/mixed signal) 

Technology Libraries

ADVance MS Simulation System 

�� ADVance MS “kernel kernel” supports: 

– VHDL & Verilog: Verilog: 

digital (via ModelSim) ModelSim 

– VHDL-AMS VHDL AMS & Verilog-A: Verilog A: analog/mixed signal 

– Eldo/SPICE: Eldo/SPICE: 

analog (via Eldo) Eldo 

– Eldo RF/SPICE: analog RF (via Eldo RF) 

– Mach TA/SPICE: high-speed high speed analog/timing 

�� Invoke stand-alone stand alone or from Design Architect-IC 

Architect IC 

�� Mentor Graphics “Legacy Legacy” Simulators 

Simulators (PCB design) 

– Quicksim II, Quicksim Pro (digital) 

– ASIC: adk_quicksim 

adk_quicksim 

– FPGA/PLD: Xilinx: pld_quicksim, 

pld_quicksim, 

Altera: Altera: 

max2_quicksim 

– Accusim (analog): adk_accusim 

adk_accusim

ADVance MS 

Digital, Analog, Mixed-Signal Mixed Signal Simulation 

Working 

Library 

Simulation 

Setup 

VHDL,Verilog, 

VHDL-AMS, Verilog-A, 

SPICE Netlists 

Design_1 

Design_2 

VITAL 

ADVance MS 

SPICE 

models 

IEEE 1164 Resource 

Libraries 

Input 

Stimuli 

Eldo, 

EZwave 

Eldo RF or Xelga ModelSim 

Analog 

(SPICE) 

Mach TA 

Mach PA 

View Results 

Digital 

(VHDL,Verilog) 

Mixed Signal 

(VHDL-AMS, 

Verilog-A)

Example: 4-bit 4 bit binary counter 

�� VHDL model (count4.vhd) 

(count4.vhd) 

– Create working library: vlib vlib work work 

vmap vmap work work work work 

– Compile: vcom vcom count4.vhd count4.vhd 

– Simulate: vsim vsim count4(rtl) count4(rtl) 

�� ModelSim simulation-control simulation control inputs 

– ModelSim “Macro 

– OR, VHDL testbench 

�� ModelSim results 

– listing listing or or waveform 

waveform 

Macro” (count4_rtl.do)

-- count4.vhd 4-bit 4 bit parallel-load parallel load synchronous counter 

LIBRARY ieee; ieee 

USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; 

ieee.numeric_std.all 

ENTITY count4 IS 

PORT (clock,clear,enable,load_count 

( clock,clear,enable,load_count : IN STD_LOGIC; 

D: IN unsigned(3 downto 0); 

Q: OUT unsigned(3 downto 0)); 

END count4; 

ARCHITECTURE rtl OF count4 IS 

SIGNAL int : unsigned(3 downto 0); 

BEGIN 

PROCESS(clear, PROCESS(clear, 

clock, enable) 

BEGIN 

IF (clear = '1') THEN 

int

Test stimulus: 

Modelsim “do do” file: count4_rtl.do 

add wave /clock /clear /enable /load_count 

/ load_count /D /Q 

add list /clock /clear /enable /load_count 

/ load_count /D /Q 

force /clock 0 0, 1 10 -repeat repeat 20 

force /clear 0 0, 1 5, 0 10 

force /enable 0 0, 1 25 

force /load_count 

/ load_count 0 0, 1 20, 0 35, 1 330, 0 350 

force /D 10#5 0, 10#9 300 

run 400

Testbench: Testbench: 

count4_bench.vhd 

LIBRARY ieee; ieee; 

USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; 

ieee.numeric_std.all 

ENTITY count4_bench is end count4_bench; 

ARCHITECTURE test of count4_bench is 

component count4 

PORT (clock,clear,enable,load_count 

( clock,clear,enable,load_count : IN STD_LOGIC; 

D: IN unsigned(3 downto 0); 

Q: OUT unsigned(3 downto 0)); 

end component; 

for all: count4 use entity work.count4(behavior); 

signal clk : STD_LOGIC := '0'; 

signal clr, clr, 

en, ld: STD_LOGIC; 

signal din, qout: qout: 

unsigned(3 downto 0); 

begin 

UUT: count4 port map(clk,clr,en,ld,din,qout); 

map(clk,clr,en,ld,din,qout); 

clk

Count4 – Simulation waveform 

Clear 

Parallel 

Load 

Counting

ADVance MS : mixed-signal mixed signal simulation 

A/D converter 

digital 

analog 

VHDL-AMS

ADVance MS: mixed Verilog-SPICE 

Verilog SPICE 

Verilog top 

(test bench) 

SPICE 

subcircuit

Technology 

Synthesis 

Libraries 

FPGA 

ASIC 

ADK 

AMI 0.5, 1.2 

TSMC 0.35, 0.25 

Automated Synthesis with 

Leonardo Spectrum 

Leonardo Spectrum 

(Level 3) 

Technology- 

Specific 

Netlist 

VHDL, Verilog, SDF, 

EDIF, XNF 

VHDL/Verilog 

Behavioral/RTL Models 

Design 

Constraints 

Level 1 – FPGA 

Level 2 – FPGA + Timing

Leonardo – ASIC Synthesis Flow

Leonardo synthesis procedure 

1. Invoke leonardo leonardo 

2. Select & load a technology library (ASIC or FPGA) 

– ASIC ASIC > > ADK ADK > > TSMC TSMC 0.35 0.35 micron micron 

): count4.vhd count4.vhd 

3. Read input VHDL/Verilog 

VHDL/ Verilog file(s): file(s 

4. Enter any constraints (clock freq, delays, etc.) 

5. Optimize for area/delay/effort level 

6. Write output file(s) file(s 

– count4_0.vhd count4_0.vhd -- VHDL VHDL netlist netlist 

– count4.v count4.v -- Verilog Verilog netlist netlist (for (for IC IC layout) layout) 

– count4.sdf count4.sdf -- Standard Standard delay delay format format file file (for (for timing) timing) 

– count4.edf count4.edf -- EDIF EDIF netlist netlist (for (for Xilinx/Altera 

Xilinx/ Altera FPGA) 

FPGA)

Leonardo-synthesized 

Leonardo synthesized netlist count4_0.vhd 

library IEEE; use IEEE.STD_LOGIC_1164.all; 

library adk; adk; 

use adk.adk_components.all; 

adk.adk_components.all; 

-- ADDED BY VPN 

entity count4 is 

port ( 

clock : IN std_logic ; clear : IN std_logic ; enable : IN std_logic ; load_count : IN std_logic ; 

D : IN std_logic_vector (3 DOWNTO 0) ; Q : OUT std_logic_vector (3 DOWNTO 0)) ; 

end count4 ; 

architecture netlist of count4 is -- rtl changed to netlist by VPN 

signal Q_3_EXMPLR, Q_2_EXMPLR, Q_1_EXMPLR, Q_0_EXMPLR, nx8, nx14, nx14, 

nx22, 

nx28, nx48, nx54, nx62, nx126, nx136, nx146, nx156, nx169, nx181, 

nx183, nx185, nx187, nx189: std_logic ; 

begin 

Q(3) clock, R=>clear); R=>clear); 

ix127 : mux21_ni port map ( Y=>nx126, A0=>Q_0_EXMPLR, A1=>nx8, A1=>nx8, 

S0=>enable ); 

ix9 : oai21 port map ( Y=>nx8, A0=>load_count 

A0=> load_count, , A1=>Q_0_EXMPLR, B0=>nx169 ); 

ix170 : nand02 port map ( Y=>nx169, A0=>D(0), A1=>load_count 

A1=> load_count); ); 

Q_1_EXMPLR_EXMPLR : dffr port map ( Q=>Q_1_EXMPLR, QB=>OPEN, D=>nx136, CLK=>clock, R=>clear); 


S0=> enable); 

ix29 : ao22 port map ( Y=>nx28, A0=>D(1), A1=>load_count 

A1=> load_count, , B0=>nx14, B1=> nx22); 

ix15 : or02 port map ( Y=>nx14, A0=>Q_0_EXMPLR, A1=>Q_1_EXMPLR); 

A1=>Q_1_EXMPLR); 

ix23 : aoi21 port map ( Y=>nx22, A0=>Q_1_EXMPLR, A1=>Q_0_EXMPLR, A1=>Q_0_EXMPLR, 

B0=> load_count); 

load_count); 

Q_2_EXMPLR_EXMPLR : dffr port map ( Q=>Q_2_EXMPLR, QB=>OPEN, D=>nx146, CLK=>clock, R=>clear); R=> clear); 


S0=> enable); 

ix49 : oai21 port map ( Y=>nx48, A0=>nx181, A1=>nx183, B0=>nx189); 

B0=> nx189); 

ix182 : aoi21 port map ( Y=>nx181, A0=>Q_1_EXMPLR, A1=>Q_0_EXMPLR, A1=>Q_0_EXMPLR, 

B0=> Q_2_EXMPLR); 

ix184 : nand02 port map ( Y=>nx183, A0=>nx185, A1=>nx187); 

ix186 : inv01 port map ( Y=>nx185, A=>load_count 

A=> load_count); ); 

ix188 : nand03 port map ( Y=>nx187, A0=>Q_2_EXMPLR, A1=>Q_1_EXMPLR, A1=>Q_1_EXMPLR, 

A2=> Q_0_EXMPLR); 

ix190 : nand02 port map ( Y=>nx189, A0=>D(2), A1=>load_count 

A1=> load_count); ); 

Q_3_EXMPLR_EXMPLR : dffr port map ( Q=>Q_3_EXMPLR, QB=>OPEN, D=>nx156, CLK=>clock, R=>clear); R=>clear); 


S0=> enable); 

ix63 : mux21_ni port map ( Y=>nx62, A0=>nx54, A1=>D(3), S0=>load_count 

S0= load_count); ); 

ix55 : xnor2 port map ( Y=>nx54, A0=>Q_3_EXMPLR, A1=>nx187); 

A1=>nx187) 

end netlist ;

Verilog description for cell count4, LeonardoSpectrum Level 3, 2005a.82 

module count4 ( clock, clear, enable, load_count, load_count, 

D, Q ) ; 

input clock ; 

input clear ; 

input enable ; 

input load_count ; 

input [3:0]D ; 

output [3:0]Q ; 

wire nx8, nx14, nx22, nx28, nx48, nx54, nx62, nx126, nx136, nx146, nx156, nx169, nx181, nx183, nx185, nx187, 

nx189; 

wire [3:0] \$dummy $dummy ; 

dffr Q_0__rename_rename (.Q (Q[0]), .QB (\$dummy ( $dummy [0]), .D (nx126), .CLK (clock), .R (clear)) ; 

mux21_ni ix127 (.Y (nx126), .A0 (Q[0]), .A1 (nx8), .S0 (enable)) (enable)) 

; 

oai21 ix9 (.Y (nx8), .A0 (load_count 

( load_count), ), .A1 (Q[0]), .B0 (nx169)) ; 

nand02 ix170 (.Y (nx169), .A0 (D[0]), .A1 (load_count 

( load_count)) )) ; 



; 

ao22 ix29 (.Y (nx28), .A0 (D[1]), .A1 (load_count 

( load_count), ), .B0 (nx14), .B1 (nx22) ) ; 

or02 ix15 (.Y (nx14), .A0 (Q[0]), .A1 (Q[1])) ; 

aoi21 ix23 (.Y (nx22), .A0 (Q[1]), .A1 (Q[0]), .B0 (load_count 




; 

oai21 ix49 (.Y (nx48), .A0 (nx181), .A1 (nx183), .B0 (nx189)) (nx189) ) ; 

aoi21 ix182 (.Y (nx181), .A0 (Q[1]), .A1 (Q[0]), .B0 (Q[2])) ; 

nand02 ix184 (.Y (nx183), .A0 (nx185), .A1 (nx187)) ; 

inv01 ix186 (.Y (nx185), .A (load_count 


nand03 ix188 (.Y (nx187), .A0 (Q[2]), .A1 (Q[1]), .A2 (Q[0])) (Q[0]) ) ; 

nand02 ix190 (.Y (nx189), .A0 (D[2]), .A1 (load_count 




; 

mux21_ni ix63 (.Y (nx62), .A0 (nx54), .A1 (D[3]), .S0 (load_count 


xnor2 ix55 (.Y (nx54), .A0 (Q[3]), .A1 (nx187)) ; 

endmodule

Post-synthesis Post synthesis simulation 

(Leonardo Leonardo-generated generated netlist) netlist 

�� Verify synthesized netlist matches behavioral 

model 

�� Create simulation primitives library for std cells: 

>>vlib vlib adk adk 

>>vcom vcom $ADK/technology/adk.vhd 

$ADK/technology/ adk.vhd 

>>vcom vcom $ADK/technology/adk_comp.vhd 

$ADK/technology/ adk_comp.vhd 

�� Insert library/package declaration into netlist 

library library adk;; adk 

use use adk.adk_components.all;; 

adk.adk_components.all 

VITAL 

models of all 

ADK std cells 

�� Simulate in Modelsim, Modelsim, 

using “do do file” file or test bench from 

original behavioral simulation 

– results results should should match match

Post-synthesis Post synthesis timing analysis 

�� Leonardo can generate SDF (std. delay format) file with 

technology-specific, technology specific, VITAL-compliant VITAL compliant timing parameters. 

(CELLTYPE "dffr " dffr") ") 

(INSTANCE Q_0_EXMPLR_EXMPLR) 

(DELAY 

(ABSOLUTE 

(PORT D (::0.00) (::0.00)) 

(PORT CLK (::0.00) (::0.00)) 

(PORT R (::0.00) (::0.00)) 

(IOPATH CLK Q (::0.40) (::0.47)) 

(IOPATH R Q (::0.00) (::0.55)) 

(IOPATH CLK QB (::0.45) (::0.36)) 

(IOPATH R QB (::0.53) (::0.00)))) 

(TIMINGCHECK 

(SETUP D (posedge ( posedge CLK) (0.47)) 

(HOLD D (posedge ( posedge CLK) (-0.06)))) ( 0.06))))

Design for test & test generation 

�� Consider test during the design phase 

– Test design more difficult after design frozen 

�� Basic steps: 

– Design for test (DFT) – insert test points, scan 

chains, etc. to improve testability 

– Insert built-in built in self-test self test (BIST) circuits 

– Generate test patterns (ATPG) 

– Determine fault coverage (Fault Simulation)

DFT & test design flow 

Memory 

& Logic 

BIST Boundary 

Scan 

Internal 

Scan Design 

ATPG

DFTadvisor/FastScan Design Flow 

DFT/ATPG 

Library: 

adk.atpg 

count4.vhd 

count4_0.vhd 

count4.v 

count4_scan.v 

Source: FlexTest Manual

VHDL/Verilog 

Netlist With 

Scan Elements 

ASIC DFT Flow 

DFT Advisor 

Synthesized VHDL/Verilog Netlist 

Fastscan/ 

Flextest 

Insert Internal 

Scan Circuitry 

Generate/Verify 

Test Vectors 

Test Pattern File 

ATPG Library 

adk.atpg

Example DFTadvisor session 

�� Invoke: 

– dftadvisor –verilog verilog count4.v –lib lib $ADK/technology/adk.atpg 

$ADK/technology/ adk.atpg 

�� Implement scan with defaults: 

(full scan, mux-DFF mux DFF scan elements) 

– set system mode setup 

– analyze control signals –auto auto 

– set system mode dft 

– run 

– insert test logic 

– write netlist count4_scan.v –verilog verilog 

– write atpg setup count4_scan 

(creates (creates count4_scan.dofile for for ATPG ATPG in in Fastscan)) 

Fastscan

count4 – without scan design

count4 – scan inserted by DFTadvisor

�� Invoke: 

ATPG with FastScan 

(full-scan (full scan circuit) 

– fastscan –verilog verilog count4.v –lib lib $ADK/technology/adk.atpg 

$ADK/technology/ adk.atpg 

�� Generate test pattern file: 

– dofile count4_scan.dofile (defines scan path & procedure) 

– set system mode atpg 

– create patterns –auto auto (generate test patterns) 

– save patterns 

Note: “count4_scan.dofile” created by DFTadvisor

Test file: scan chain definition and 

load/unload procedures 

scan_group "grp1" = 

scan_chain "chain1" = 

scan_in = "/scan_in1"; 

scan_out = "/output[3]"; 

length = 4; 

end; 

procedure shift "grp1_load_shift" = 

force_sci "chain1" 0; 

force "/clock" 1 20; 


period 40; 

end; 

procedure shift "grp1_unload_shift" = 

measure_sco "chain1" 10; 



period 40; 

end; 

procedure load "grp1_load" = 

force "/clear" 0 0; 


force "/scan_en "/ scan_en" " 1 0; 

apply "grp1_load_shift" 4 40; 

end; 

procedure unload "grp1_unload" = 

force "/clear" 0 0; 


force "/scan_en "/ scan_en" " 1 0; 

apply "grp1_unload_shift" 4 40; 

end; 

end;

Generated scan-based scan based test 

// send a pattern through the scan chain 

CHAIN_TEST = 

pattern = 0; 

apply "grp1_load" 0 = (use grp1_load procedure) 

chain "chain1" = "0011"; (pattern to scan in) 

end; 

apply "grp1_unload" 1 = (use grp1_unload procedure) 

chain "chain1" = "1100"; (pattern scanned out) 

end; 

end; 

// one of 14 patterns for the counter circuit 

pattern = 0; (pattern #) 

apply "grp1_load" 0 = (load scan chain) 

chain "chain1" = "1000"; (scan-in (scan in pattern) 

end; 

force "PI" "00110" 1; (PI pattern) 

measure "PO" "0010" 2; (expected POs) 

pulse "/clock" 3; (normal op. cycle) 

apply "grp1_unload" 4 = (read scan chain) 

chain "chain1" = "0110"; (expected pattern) 

end;

ASIC Physical Design (Standard Cell) 

Generate 

Mask Data 

Std. Cell 

Layouts 

Libraries 

Process Data 

Design Rules 

IC Mask Data 

(can also do full custom layout) 

Component-Level Netlist (EDDM format) 

Design Rule 

Check 

Floorplan 

Chip/Block 

Place & Route 

Std. Cells 

ICblocks 

Backannotate 

Schematic 

Mach TA/Eldo Simulation Model 

Mentor Graphics 

“IC Station” 

(adk_ic) 

Layout vs. 

Schematic 

Check 

Calibre Calibre Calibre

Cell-Based Cell Based IC

Cell-Based Cell Based Block

Basic standard 

Cell layout 

Source: Weste “CMOS VLSI Design”

Preparation for Layout 

1. Use Design Architect-IC Architect IC to convert Verilog netlist to 

Mentor Graphics EDDM netlist format 

– Invoke Design Architect-IC 

Architect IC ((adk_daic adk_daic)) 

– On menu bar, select File File > > Import Import Verilog Verilog 

�� Netlist file: count4.v count4.v (the (the Verilog Verilog netlist)) netlist 

�� Output directory: count4 count4 (for the EDDM netlist) netlist 

�� Mapping file $ADK/technology/adk_map.vmp 

$ADK/technology/ adk_map.vmp 

2. Open the generated schematic for viewing 

– Click Schematic Schematic in DA-IC DA IC palette 

– Select schematic in directory named above (see next slide) 

– Click Update Update LVS LVS in the schematic palette to create a netlist to 

be used later by “Calibre Calibre” 

3. Create design viewpoints for ICstation tools 

– adk_dve adk_dve count4 count4 ––t t tsmc035 tsmc035 (V.P V.P’s: : layout, lvs, lvs, 

sdl, sdl, 

tsmc035) 

�� Can also create gate/transistor schematics directly in 

DA-IC DA IC using components from the ADK library

DA-IC DA IC generated schematic

Eldo simulation from DA-IC DA IC 

�� Run simulations from within DA-IC DA IC 

– Eldo, Eldo, 

ADVance ADVance MS, MS, 

Mach Mach TA TA 

�� DA-IC DA IC invokes a “netlister netlister” to create a 

circuit model from the schematic 

– SPICE model for Eldo Eldo & Mach Mach TA TA 

�� Eldo analyses, forces, probes, etc. same 

as SPICE 

�� View results in EZwave EZwave or Xelga 

Xelga

Eldo input and output files 

-Netlist 

-Simulation cmds 

-Stimulus

SPICE “circuit” file generated by DA-IC 

Force values (created interactively) 

From ADK 

library 

SPICE netlist for modulo7 counter

Eldo simulation of modulo7 counter 

(transient analysis)

Create a std-cell std cell based logic block 

in IC Station 

�� Invoke: adk_ic adk_ic 

�� In IC Station palette, select: Create Create Cell Cell 

– Cell name: count4 count4 

– Attach library: $ADK/technology/ic/process/tsmc035 

– Process: $ADK/technology/ic/process/tsmc035 

– Rules file: $ADK/technology/ic/process/tsmc035.rules 

– Angle mode: 45 45 

– Cell type: block block 

– Select With With connectivity 

connectivity 

– EDDM schematic viewpoint: count4/layout 

count4/layout 

– Logic loading options: flat 

flat

Create Cell dialog box

Auto-”floorplan 

Auto floorplan” the block 

place place & & route route > > autofp 

autofp

Auto-place Auto place the std cells 

Autoplc Autoplc > > StdCel 

StdCel

Auto-place Auto place “ports 

ports” ((Autoplc Autoplc > > Ports) Ports) 

Signal connections on cell boundaries

AutoRoute all nets 

(hand-route (hand route any unrouted “overflows overflows”) 

Then: Add > Port Text to copy port names from schematic – for Calibre

Layout design rule check (DRC) 

�� Technology-specific Technology specific design rules specify 

minimum sizes, spacing, etc. of features 

to ensure reliable fabrication 

– Design rules file specified at startup 

Ex. tsmc035.rules 

tsmc035.rules 

�� From main palette, select ICrules 

– Click Check Check and then OK OK in prompt box 

(can optionally select a specific area to check) 

– Rules checked in numeric order

Common errors detected by DRC 

�� To fix, click on First First in palette to highlight first 

error 

– Error is highlighted in the layout 

– Click View View to zoom in to the error (see next) 

– Example: DRC9_2: Metal2 spacing = 3L 

– Fix by drawing a rectangle of metal2 to fill in the gap 

between contacts that should be connected 

�� Click Next Next to go to next error, until all are fixed 

NOTE: There can be no DRC errors if MOSIS is to 

fabricate the chip – they will run their own DRC.

Error: DRC9_2 metal2 spacing = 3L 

Draw 

rectangle 

of metal2 

to fill gap

Layout vs schematic check 

Calibre Interactive LVS 

�� From ICstation menu: Calibre Calibre > > Run Run LVS LVS 

– In popup, Calibre location: $MGC_HOME/../Calibre 

$MGC_HOME/../ Calibre 

– Rules: $ADK/technology/ic/process/tsmc035.calibre.rules 

– Input: count4.src.net count4.src.net (previously created in DA-IC) DA IC) 

– H-cells: cells: $ADK/technology/adk.hcell 

$ADK/technology/ adk.hcell (hierarchical cells) 

– Extracted file: count4.lay.net 

count4.lay.net 

�� Compares extracted transistor-level 

transistor level netlist vs. 

netlist saved in DA-IC DA IC

Post-layout Post layout parameter extraction 

Calibre Interactive PEX 

�� Extract Spice netlist, netlist, 

including parasitic RC 

– Simulate in Eldo or MachTA 

�� ICstation menu: Calibre>Run Calibre>Run 

PEX PEX 

– Options Options similar similar to to Calibre Calibre LVS LVS 

– Extraction Extraction options: options: 

�� lumped lumped C C + + coupling coupling cap’’ss cap 

�� distributed distributed RC RC 

�� distributed distributed RC RC + + coupling coupling cap’’ss cap 

– Output file: count4.pex.netlist

Post-layout Post layout simulation with MachTA 

�� MachTA is an accelerated Spice simulator 

– Digital & mixed-signal mixed signal circuits 

– Analyze timing effects pre- pre and post-layout post layout 

�� SPICE netlists with parasitic R/C 

– Execute test vector file to verify functionality 

�� Algorithms support large designs 

– Partition design, simulate only partitions with changes 

– Combine time-driven time driven & event-driven event driven operation 

– Solves linearized models using a proprietary highperformance, 

graph-theory based, matrix solution 

algorithm

Mach TA flow diagram 

$ADK/technology/mta/tsmc035 

SPICE 

netlist

Post-layout Post layout simulation with Mach TA 

(netlist netlist extracted by Calibre PEX) 

�� Prepare netlist 

netlist (remove subcircuits for Mach TA) 

– Extracted netlist = count4.pex.netlist 

– Command: $ADK/bin/mta_prep 

$ADK/bin/ mta_prep count4 count4 

– Creates SPICE file: count4.sp count4.sp 

�� Invoke Mach TA: 

ana ana - command file to initialize Anacad SW 

mta mta ––ezw ezw ––t t $ADK/technology/mta/tsmc035 count4.sp count4.sp 

� Mach PA (mpa) does current & power analysis

Sample Mach TA “dofile dofile” 

(transient analysis) 

Signals to observe in EZwave 

plot v(clk) v(clk) 

v(q[2]) v(q[1]) v(q[0]) 

measure rising TRIG v(clk) v(clk) 

VAL=2.5v RISE=1 TARG v(q[0]) VAL=2.5v 

l load 

l reset 

h count 

Measure time from rising edge of clk (TRIGger) 

l clk 

to 1st rising edge of q[0] (TARGet) - voltages 

run 5 ns 

h reset 

h clk 

Drive signals low/high (Lsim format) 

run 5 ns 

l clk 

run 5 ns 

Simulate for 5 ns 

h clk 

run 5 ns 

Command to execute: dofile file.do

Double-click 

signal name 

to display. 

EZwave waveform viewer 

(results for previous dofile) dofile

Alternative Mach TA “dofile dofile” 

(same result as previous example) 

plot v(clk) v(clk) 

v(q[2]) v(q[1]) v(q[0]) 

measure rising TRIG v(clk) v(clk) 

VAL=2.5v RISE=1 TARG v(q[0]) 

VAL=2.5v 

vpulse Vclk clk 0 pulse(0 3.3 10n .05n .05n 10n 20n) 

v-levels delay rise fall width period 

l load 

l reset 

Nodes to which 

h count 

run 5 ns 

source connected 

Periodic pulses 

h reset 

run 200 ns 

Voltage source name

Mach TA – test vector file 

�� Verify design functionality/behavior 

– apply test vectors 

– capture outputs 

– compare outputs to expected result 

– vectors/outputs from behavioral simulation 

�� Command to execute a test vector file: 

run run ––tvend tvend tvfile.tv tvfile.tv 

test vector file (next slide)

Test vector file format 

# Test vector file for modulo7 counter 

CODEFILE 

UNITS ps 

RISE_TIME 50 

FALL_TIME 50 

signal order within vectors 

Header 

INPUTS clk,reset,load,count,i[2],i[1],i[0]; 

OUTPUTS q[2] (to=max),q[1] (to=max),q[0] (to=max); 

CODING(ROM) 

RADIX 3; 

Vector format 

@0 X; 

@2000 0; 

@7000 0; 

@10000 5; 

Sample 5 fs before next vector 

@20000 5; 

@30000 6; 

@40000 6; 

@50000 0; 

@60000 0; 

….. .. 

END 

Vectors: @time expected_output 

Test vectors derived from behavioral simulation results

Behavioral simulation listing Corresponding Mach TA test vector file

Alternate test vector file 

(clock generated separately by voltage source) 

vpulse vclk clk 0 

pulse(0 3.3 10n .5n .5n 10n 20n) 

Can mix other simulation 

commands with test vector 

application.

Xilinx “ISE” 

Altera “Max Plus 2” 

Physical Design - FPGA 

User-Specified 

Constraints 

Component-Level Netlist 

Generate 

Programming 

Data 

Configuration File 

Map to FPGA 

LUTs, FFs, IOBs 

Place & Route 

Generate 

Timing Model 

Simulation Model 

FPGA/PLD 

Technology 

Files

Xilinx/Altera 

Xilinx/ Altera FPGA/CPLD Design 

�� Technology files & libraries for front-end front end design with 

Mentor Graphics tools 

– Schematic symbols for Design Design Architect Architect 

– Simulation models for Quicksim Quicksim II, II, Quicksim Quicksim Pro Pro 

– Synthesis library for Leonardo Leonardo 

�� Vendor tools for back-end back end design 

(map, place, route, configure, timing) 

– Xilinx Integrated Integrated Software Software Environment Environment (ISE) 

– Altera Quartus Quartus II II & & Max+Plus2 

Max+Plus2

Mentor Graphics ASIC Design Flow

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?