PIC18F to PIC24F Migration: An Overview - Microchip

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Instruction SetThe PIC24F instruction set architecture represents aconsiderable extension of its PIC18F predecessor.While barely larger in terms of base instructions, itmakes substitutions of selected instructions toenhance the performance, while expanding the scopeof addressing modes and data type operations.Through all of this, the PIC24F instruction set maintainsthe highly orthogonal structure of previous PICmicroarchitectures.The main differences between the PIC18F and PIC24Finstruction sets are presented in Table 2.TABLE 2:COMPARISON OF MAJOR INSTRUCTION SET FEATURESFeature PIC18F PIC24FInstruction Size 16 bits 24 bitsBase Instructions 75 76Supported Data Types Byte Byte, Word, Double WordOperand Support Up to binary (b = a + b) Up to trinary (a + b = c)Addressing Modes Direct, Indirect (5) Direct, Indirect (6)Indirect Addressing Type Uses FSR Pointer register sets; limit of3 pointersUses any of the W registers as pointers withinstruction-based manipulation; limit of 16Data Space AddressingShort literal, limited to a single bank atone time; full literal on few instructionsShort literal for entire Near Data Space;indirect address for entire spaceCHANGES FROM PIC18F INSTRUCTION SETThe PIC24F instruction set implements severalfeatures that enhance performance for math operations,and extend the ability to handle high-levellanguages with more complex stack and pointerrequirements. These are summarized in Table 3.In addition, several PIC18F instructions do not have anexact single instruction equivalent in the PIC24F architecture.Most of these instructions have either single orpairs of PIC24F instructions that have similar effect, butbecause of differences in the STATUS register, resultsare not exactly equivalent. They are:• CPFSEQ• INFSNZ• CPFSGT• MOVSF• CPFSLT• MOVSS• DCFSNZ• PUSHL• DECFSZ• SUBULNK• INCFSZ• TSTFSZ• MOVFF (all modes except indirect to indirect)• SWAPF (all modes except with WREG)Even with these changes, most PIC18F assemblerinstructions have a single-cycle equivalent in thePIC24F assembler. A comprehensive list is providedin Appendix A: “Mapping PIC18F to PIC24FInstructions”.TABLE 3:NEW OR SIGNIFICANTLY MODIFIED PIC24F INSTRUCTIONSPIC24F InstructionDescriptionDIV Divide two numbers (signed or unsigned, 16/16 or 32/16)LNK and UNLKLink or unlink Frame Pointer (W14)LSR and ASRLogical or arithmetic shift right by 1 to 16 bits, by either a literal or variable valueMUL.SS, MUL.SU, Specific instructions for multiplying signed and unsigned numbersMUL.USPUSH and POPBoth instructions now include source or destination arguments, allowing the stack tostore values other then the current PCREPEATRepeat the next instruction a specified number of timesSLShift left by 1 to 16 bits by either a literal or variable valueDS39764A-page 4© 2006 Microchip Technology Inc.
SUPPORTED DATA TYPESAside from bit-oriented instructions, PIC18Finstructions operate exclusively on single byte data.Any data that is longer than a single byte is handled byconcatenating bytes in the proper order.As 16-bit devices, PIC24F instructions are designed tohandle data in terms of 16-bit words. In addition, mostinstructions are capable of handling single byte anddouble word (32-bit) data objects. Invoking this featureis generally done by using the suffix “.b” (for bytes) or“.d” (for double words) after the instruction mnemonic.Data alignment within the memory space is automaticallyadjusted and maintained according to the datatype selected.OPERAND SUPPORTThe PIC18F instruction set supports both unary andbinary operations. That is to say, an instruction canfunction with a single argument operating on the contentsof one register (e.g., increment the WREG), orwith two arguments storing the results in one of the tworegisters (e.g., adding the contents of a register toWREG and storing the sum in WREG).The PIC24F instruction set also supports trinaryoperations; that is, an operation can have three arguments,specifying not only two operands but also anindependent address for the result. Trinary operationsare supported for most arithmetic and logic instructions.ADDRESSING MODESThe biggest difference between the PIC18F andPIC24F instruction sets is how the instructions specifyaddresses in the data memory space. While the methodsare equivalent, the PIC24F version allows moreoptions for more of its instructions.Direct AddressingWhile PIC18F instructions can directly address anyregister in the data space, very few specify a fulladdress as part of the instruction. Instead, most use an8-bit literal value to specify an address within one of16 banks of 256 bytes within the space. The bank inquestion is separately selected by the Bank SelectRegister (BSR).PIC24F instructions are designed to be able to literallyaddress any register within the lowest 8 Kbytes of thedata space (also known as the Near Data Space). Thisallows immediate access to all SFRs. Implementedmemory areas above the top of the Near Data Spaceare accessible by indirect addressing, as describedbelow.Indirect AddressingPIC18F instructions perform indirect addressingthrough pointers and virtual registers. Three 12-bitpointers (FSR0 through FSR2) are loaded withappropriate values; then, one of five virtual registersassociated with that pointer is used as an argument foran instruction, either as an address or an offset for anaddress. Depending on which of the registers is used,the value of the pointer can also be automatically incrementedor decremented. Only these three pointers andtheir associated registers can be used for indirectaddressing.In contrast, PIC24F architecture increases the numberof options for the addressing mode. Any one of the Wregisters can be used as a pointer for indirect addressing.Instead of using a virtual register name to determinethe pointer and its operation, the MPLAB ® IDEassembler language uses specific syntax conventionsto indicate when a W register is being used as a pointeror offset, and what increment or decrement operation isto be done to the register. The PIC24F Instruction SetArchitecture (ISA) also offers a pre-decrement optionnot available with PIC18F. An additional feature of thePIC24F increment/decrement options is how they workwith the data type specified by the instruction. If theinstruction is executed as a byte type instruction, theregister will be incremented or decremented by one.This aligns the pointer to the next byte in memory whichis not always the next memory address. Word-orientedinstructions will increment or decrement the register bytwo and maintain proper word alignment.The differences between architectures in indirectaddressing modes and syntax are summarized inTable 4. A comparison of how to use these addressingmodes is shown in Example 1.TABLE 4:Indirect AddressingModeINDIRECT ADDRESSING IN PIC18F AND PIC24F INSTRUCTION SETSPIC18F VirtualRegister OperandPIC24F EquivalentSyntaxAfter ByteInstructionWn (or FSR)After WordInstructionNo Modification INDFx [Wn] Wn = Wn Wn = WnPre-Increment PREINCx [++Wn] Wn = Wn + 1 Wn = Wn + 2Pre-Decrement N/A [--Wn] Wn = Wn – 1 Wn = Wn – 2Post-Increment POSTINCx [Wn++] Wn = Wn + 1 Wn = Wn + 2Post-Decrement POSTDECx [Wn--] Wn = Wn – 1 Wn = Wn – 2Register Offset PLUSWx [Wn + Wb] Wn = Wn Wn = Wn© 2006 Microchip Technology Inc. DS39764A-page 5
Page 1 and 2: PIC18F to PIC24F Migration: An Over
Page 3: W REGISTERSAll PIC18F devices have
Page 7 and 8: Memory Map and Program MemoryBoth P
Page 9 and 10: INTERRUPT/RESET/TRAP VECTORSIn PIC1
Page 11 and 12: Data Memory SpaceThe PIC24F data me
Page 13 and 14: Resets and Start-up TimingThe PIC24
Page 15 and 16: ADDITIONAL PIC24F RESETSBeyond the
Page 17 and 18: Interrupt ControllerThe PIC24F inte
Page 19 and 20: OscillatorThe PIC24F oscillator sys
Page 21 and 22: INTERNAL RC OSCILLATORS (INTOSC/FRC
Page 23 and 24: Power-Saving FeaturesPIC24F power-s
Page 25: Watchdog Timer (WDT)The Watchdog Ti
Page 28 and 29: NEW PIC24F FEATURES• Open-drain i
Page 30 and 31: NEW PIC24F FEATURESThe most apparen
Page 32 and 33: In Full-Bridge mode, the PIC18F PWM
Page 34 and 35: Serial Peripheral Interface (SPI)Th
Page 36 and 37: Inter-Intergrated Circuit (I 2 C)Th
Page 38 and 39: Universal AsynchronousReceiver/Tran
Page 40 and 41: TRANSMISSION SETUP (8-BIT DATA MODE
Page 42 and 43: NEW PIC24F A/D FEATURESMany of the
Page 44 and 45: NEW PIC24F COMPARATOR MODULEFEATURE
Page 46 and 47: NOTES:DS39764A-page 46© 2006 Micro
Page 48 and 49: TABLE A-1:PIC18FInstructionPIC18F A
Page 54:
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PIC18F to PIC24F Migration: An Overview - Microchip

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