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High Speed OpticalLink Based onIntegrated <strong>Silicon</strong><strong>Photonics</strong>Dr. Haisheng Rong<strong>Photonics</strong> Research <strong>Lab</strong>Intel Corporationwww.intel.com/go/spPKU, Summer SchoolJuly 04, 2012© 2011, Intel Corporation. All Rights Reserved

Agenda• Motivation• Electronic & Photonic Evolution• Intel’s Research Program• Integrated SiP link• Challenges & Summary2© 2011, Intel Corporation. All Rights Reserved

Estimating the Exaflood, Discovery Institute, 1/08; Amassing Digital Fortunes, a Digital Storage Study, CEA, 3/08A Wealth of Data to MovePersonal MediaBusinessMedicalSocial MediaScienceHuman Genomics7 EB/yr, 200% CAGRAve. Files on HD54GBRetail Customer DB600 TBClinical Image DB~1PBHD video forecast12 EB/yrPhysics (LHC)300 EB/yrMore than 15Bconnecteddevices by 2015KiosksMedicalImagingNetworkAppliancesDigitalSignageTest &MeasurementSecuritySurveillanceIn-VehicleInfotainment3How do you connect all these?© 2011, Intel Corporation. All Rights Reserved

Example: Advanced Video Technology3D DisplaysHigh Dynamic Range24Hz 48Hz 60Hz 120Hz (3D)HDR Increase(color depth)Today: Full HD1080pTomorrow : Quad HD2160p24 48 24 48 24 48 24 481.19Gbps4.78Gbps2.39Gbps9.56Gbps2.39Gbps9.56Gbps4.78Gbps19.11Gbps2.99Gbps11.94Gbps5.97Gbps23.89Gbps5.97Gbps23.89Gbps11.94Gbps47.78Gbps4Future: Ultra High Definition (4320p, 30bpp, 60Hz) needs 60 Gbps!Hard to do this electrically.© 2011, Intel Corporation. All Rights Reserved

Challenges for Cu InterconnectsPlatform requirements taking it to the breaking pointCopper cables have issues withdistance, bend radius, weight,thickness, <strong>and</strong> airflow interruption5© 2011, Intel Corporation. All Rights Reserved

What if we could Eliminate Distance &B<strong>and</strong>width Constraints Using Optical Links?Optical linksBoard-BoardMultiprocessingRack LevelInterconnectOptical linksMulti-terabyteMemory BankSharedMemoryOptical linksNew opportunities to:• Increase performance• Reduce system costs• Reduce thermal density• Improve energy efficiency• Enable new form factors-IDOptical linksCould Revolutionize future platform architecturesBut…. Have to be low cost to enable ……6© 2011, Intel Corporation. All Rights Reserved

Moving to Optical InterconnectsOpticalCopperMetro &Long Haul0.1 – 80 kmChip to Chip1 – 50 cmBillionsRack toRack1 to 100 mBoard to Board50 – 100 cmMillionsVolumesThous<strong>and</strong>sDecreasing Distances→Need to Drive optical to highvolumes <strong>and</strong> low costs7© 2011, Intel Corporation. All Rights Reserved

Electronics:Economics of Moore’s LawSCALING + WAFER SIZE + HIGH VOLUME = LOWER COSTIntegration & increased functionality8© 2011, Intel Corporation. All Rights Reserved

A Half Century of Integration1959 Today<strong>Silicon</strong>~50yearsFirst <strong>Silicon</strong> IC (Noyce <strong>and</strong> Kilby)Billions of Transistors• We have gone from 2 transistors to 2 billion• This “Moore’s Law” scaling has led to transformative technologies•9• Mainframes -> Servers -> PCs -> Laptops -> H<strong>and</strong>helds• Internet, e-commerce, social media<strong>Silicon</strong> manufacturing has made this all possible© 2011, Intel Corporation. All Rights Reserved

A Half Century of Innovation1960 TodayLasers50yearsFirst Laser(Ted Maiman)Countless apps• Practical usages not known upon invention• Laser has impacted industries from medicine tomanufacturing to entertainment <strong>and</strong> more• All long distance communications driven by lasers10Costs limits use of optical for everyday devices© 2011, Intel Corporation. All Rights Reserved

Bringing Si Manufacturing to Optical CommsSi ManufacturingOptical CommunicationsHigh volume,low costHighlyintegratedScalableVery highb<strong>and</strong>widthLong distancesImmunity toelectrical noiseOPTICALANYWHERE,INCREDIBLEPOTENTIAL11© 2011, Intel Corporation. All Rights Reserved

The Opportunity of <strong>Silicon</strong> <strong>Photonics</strong>• Enormous ($ billions) CMOS infrastructure, processlearning, <strong>and</strong> capacity– Draft continued investment in Moore’s law• Potential to integrate multiple optical devices• Micromachining could provide smart packaging• Potential to converge computing & communicationsTo benefit from this optical wafersmust run alongside existing product.12

<strong>Silicon</strong> as an Optical MaterialPhoton Energy (eV) → 2.76 1.55 1.1eV 0.41Wavelength (µm) → 0.45 0.8 1.12µm 3.0Transparent in >1.2 µmHigh index Low light emission efficiencyLow cost material No electro-optical effectCMOS compatible No detection in 1.3-1.6 µmHigh Thermal conductivity13<strong>Silicon</strong> traditionally NOToptical material of choice13

The Path to “<strong>Silicon</strong>izing” <strong>Photonics</strong>Lasers Data Encoders Light detectors1 st Continuous Wave<strong>Silicon</strong> Raman Laser(Feb. ‘05)<strong>Silicon</strong> Modulators1GHz ( Feb ‘04)10 Gbps (Apr ‘05)40 Gbps (July ’07)40 Gbps PINPhotodetectors(Aug. ’07)Hybrid <strong>Silicon</strong>Laser (Sept. ‘06)Basic Light RoutingWaveguides, multiplexers,demultiplexers, couplers…340 GHz Gain*BWAvalanche Photodetector(Dec ’08)14Numerous scientific breakthroughsin silicon photonic building blocks© 2011, Intel Corporation. All Rights Reserved

Intel’s Second Generation: <strong>Silicon</strong> Modulatorinput1x2 MMIpn phaseshifters2x1 MMIoutputMetal contactPhase shifterwaveguideSEM picture of p-n phase shifter- Based on traveling wave design- Optimized optical & electrical RF15© 2011, Intel Corporation. All Rights Reserved

40 Gbps Data Transmission40 GbpsNormalized Modulator Output (dB)10-1-2-3-4-5-6-7-8Optical Roll-off (1mm phase shifter)On-chip terminationExternal termination0 1 10 100Frequency (GHz)• Optical 3 dB roll off ~30 GHz (parasitic effect included)• 6 dB electrical roll-off ~ 40 GHz (no parasitic effect included)• Measured phase efficiency = 3.3 V-cm16© 2011, Intel Corporation. All Rights Reserved

Photo-detection• <strong>Silicon</strong> does not absorb IR well• Using SiGe to extend to 1.3µm+• Must overcome lattice mismatchGeBulk Films of Si <strong>and</strong> GeStrained Si 1-x Ge x on SiRelaxed Si 1-x Ge x on SiSia Ge ~ .565 nma Si ~ .543 nmmisfitdislocationMisfit dislocations typically create threading dislocations which degrade deviceperformance - dark current (I dk ) goes up.Must simultaneously achieve requiredspeed, responsivity, & dark current17© 2011, Intel Corporation. All Rights Reserved

Waveguide Photo-detector DesignN-Gei-GeSEM Cross-Section18© 2011, Intel Corporation. All Rights Reserved

SiGe WG PIN - High Speed PerformanceRelative Responsivity (dB)30-3-6-9-1231 GHz Optical B<strong>and</strong>widthB<strong>and</strong>width (GHz)35302520151057.4um x 50um4.4um x 100um0 1 2 3 4 5Voltage (V)7.4um x 50um, -2V4.4um x 100um, -2V10 8 10 9 10 10Frequency (Hz)40 Gb/s Eye Diagram95% Quantum EfficiencyOperating at λ ~1.56um< 200nA of dark current19© 2011, Intel Corporation. All Rights Reserved

Hybrid <strong>Silicon</strong> Lasers•The Indium Phosphide emits thelight into the silicon waveguide• The silicon acts as laser cavity:• <strong>Silicon</strong> waveguide routes the light• End Facets or gratings are reflectors/mirrors• Light bounces back <strong>and</strong> forth <strong>and</strong> gets amplified by InP• Laser performance determined by InP <strong>and</strong> Si waveguide- No alignment needed- Multiple lasers with ONE bond- Light inside the waveguide20© 2011, Intel Corporation. All Rights Reserved

Hybrid Laser Fabrication Overview• III-V material (unprocessed) is bonded everywhere or only on smallparts of a wafer/die• Alignment during bonding is not critical III-V is processedafter bonding, with mask alignment to underlying silicon markers(1) WaferBondingProcess(2) III-VBacksideProcess© 2011, Intel Corporation. All Rights Reserved

DBR Lasers on Hybrid Laser Platform• Tapers transition from hybrid(active) WG to silicon (passive) WG• Gratings in silicon WG formwavelength selective mirrors© 2011, Intel Corporation. All Rights Reserved

Hybrid silicon evanescent modal gain<strong>Silicon</strong> waveguide dimensions controlMQW overlap <strong>and</strong> modal gainChanging waveguide width allows forvarying confinement factors within a dieor PICMQW© 2011, Intel Corporation. All Rights Reserved

Lithographically defined first order gratingsFabricated using 193-nm laser stepper lithography (HVM compatible)PeriodTop Down ViewGratingwidthGaplengthCross section0.3um0.5um1.5umetchwidthetch depth© 2011, Intel Corporation. All Rights Reserved

Single Wavelength Hybrid Lasergrating mirrors in silicon,enabling wavelength-specificlaser light outputThe Device~1000umOptical SpectrumLine width Measurement~150 um25© 2011, Intel Corporation. All Rights Reserved

Common Building Block – Economy of ScaleIntegrated SiP Tx <strong>and</strong> Rx Building BlocksChallenges:- Integrate all building blocks onto Si platforms- Optimize processes for integration (vs. discrete)- Low cost packaging, assembly, <strong>and</strong> system testing- Do all these using “PC-Board” techniques <strong>and</strong> passiveoptical alignment

The 50G Integrated <strong>Silicon</strong> <strong>Photonics</strong> LinkTransmitting <strong>and</strong> Receiving Light with <strong>Silicon</strong>Optical FiberIntegratedTransmitterChipIntegratedReceiverChipTransmitModuleReceiverModule28© 2011, Intel Corporation. All Rights Reserved

Integrated <strong>Silicon</strong> <strong>Photonics</strong> Link4λx12.5 Gb/sElements are combined together,along with drivers <strong>and</strong> packaging toform a CWDM link29© 2011, Intel Corporation. All Rights Reserved

Integrated Transmitter Chip1101001110Electrical data in…Up to 12.5 Gbps/channelIntegrates Hybrid <strong>Silicon</strong> LasersWith Modulators for data encoding<strong>and</strong> a Multiplexer to put 4 opticalchannels onto 1 fiberAlignment Pin50Gbpsout on oneoptical fiberConnector30Parallel channels are key to scalingb<strong>and</strong>widths at low costs© 2011, Intel Corporation. All Rights Reserved

Integrated Receiver ChipIntegrates a coupler to receive incominglight with a demultiplexer to split opticalsignals <strong>and</strong> Ge-on-Si photodetectors toconvert photons to electronsAlignment PinCouplerElectrical data out…Up to12.5 Gbpsper channel1101001110110100111050Gbpsin on oneoptical fiber11010011101101001110Connector31Receives 4 optical channels at 12.5Gbps<strong>and</strong> converts to electrical data© 2011, Intel Corporation. All Rights Reserved

Measured Data4 hybrid <strong>Silicon</strong> Laser Outputs12.5Gbps data outputper channelTransmitReceiveDe-Multiplexer separates wavelengthsElectrical OutputFrom Receiver32We ran link for more than a day with no errors (>1 Petabit)Translates to Bit-Error-Rate (BER) of < 3e -15© 2012, Intel Corporation. All Rights Reserved

4λx10Gbps SiP Tx & Rx PackagesOptical FiberIntegrated4λ x10GSiP Tx ChipTransmitter PackageReceiver PackageIntegrated4λ x 10GSiGe PD RxCMOSDriver ICPassiveOpticalConnectorReceiver ICSocketableEdgeConnectorTx & Rx packages enable bothseparable (passive) optical <strong>and</strong>electrical connectors33© 2011, Intel Corporation. All Rights Reserved

What Could You <strong>Download</strong> in

What Could You <strong>Download</strong> in

The Path to Tera-scale Data RatesToday: 12.5 Gbps x 4 = 50Gbps25 Gbps x 4 = 100GbpsScale UP40G, 100G…Scale OUT12.5 Gbps x 8 = 100GbpsSpeed Width Rate12.5 x4 50G12.5 x8 100G25 x16 400G40 x25 1TFutureTerabit+ Links36x16, x32…Could enable cost-effective high speedI/O for data-intensive applications© 2011, Intel Corporation. All Rights Reserved

CMOS Integration Challenges• Film topology• Thermal budgets• Yield metrology• Contaminating the fab• Coupling to devices• Heat dissipation• ComplexityOptical wafers must run alongsideproduct, introducing challenges37

Example: Topology• Depth of focus (DOF) shrinks as litho improves• Many optical devices are much taller than transistorsNew planarization techniques <strong>and</strong>specific process flowsrequired for advanced lithoDOF vs. LithoTechnology (µm)Transistoron 90nm8µmTaper0.25 0.18 0.090.9µmRib0.5 µm0.35µm0.2µm0.1µm gate0.3µmStrip38<strong>Silicon</strong> Wafer38

Example: Thermal Budgets1050°CTemperatureMelting Point of InP 1054°CGate Oxide950°CS/D ActivationMelting Point of Ge 940°CAnnealing of Si nc 800°C500-650°CGate ContactsProcessing Steps450°C• Thermal budget dictates process step order• Cannot use high temperatures at later steps without damageAl / Cu200°CPackagingOptical Polymers 200°CThis determines what can beintegrated in the fab vs. backend39

Example: Yield metrologyElectronics:•CMOS fabs monitor thous<strong>and</strong>s of parameters across wafer in line•Tight control – e.g. CMOS gate width held to 10’s of angstroms• Significant per-wafer cost savings from screening out yield earlyScreeningwafers forearly defectdetectionIntegratedverticalcouplingapproachesOptical•In-line wafer level optical probing is very immature•Most optical device testing is performed after wafer dicingFor HVM, techniques for screeningoptical wafers must be developed40

Challenges: Optical Integration with CPUPackage topsideConnection?MonolithicIntegration?PROCESSORFIBERSORGANIC PACKAGESOCKETFR4 MOTHERBOARDBoard connection?Challenges:Power: CPU’s operate with Temperatures near ~85°CPackaging: Compatibility with existing HVM packages connector costTesting: Testing co-packaged optical /electrical CPU modulesPackaging, thermals <strong>and</strong> testing key to enabling optical inplatform41© 2011, Intel Corporation. All Rights Reserved

Summary• SiP is a key enabling technology for high BW interconnects• Developed first fully integrated Si photonics based Tx & Rx• Demonstrated CWDM based Si Photonic link @ 50Gb/s• On path to develop fully integrated silicon photonic links toaddress various interconnect applications42Acknowledgements• Intel Corp. - SiP team <strong>and</strong> LAD team• Aurrion Inc. – For InP processing <strong>and</strong> hybrid laser developments• Micron – For <strong>Silicon</strong> <strong>Photonics</strong> processing

Thank You!43To learn more www.intel.com/go/sp© 2011, Intel Corporation. All Rights Reserved

Legal Disclaimer• Intel may make changes to specifications <strong>and</strong> product descriptions at any time, without notice.• Performance tests <strong>and</strong> ratings are measured using specific computer systems <strong>and</strong>/or components <strong>and</strong> reflect the approximateperformance of Intel products as measured by those tests. Any difference in system hardware or software design or configuration mayaffect actual performance. Buyers should consult other sources of information to evaluate the performance of systems or componentsthey are considering purchasing. For more information on performance tests <strong>and</strong> on the performance of Intel products, visit IntelPerformance Benchmark Limitations• Intel does not control or audit the design or implementation of third party benchmarks or Web sites referenced in this document. Intelencourages all of its customers to visit the referenced Web sites or others where similar performance benchmarks are reported <strong>and</strong>confirm whether the referenced benchmarks are accurate <strong>and</strong> reflect performance of systems available for purchase.• Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, notacross different processor families. See www.intel.com/products/processor_number for details.• Intel, processors, chipsets, <strong>and</strong> desktop boards may contain design defects or errors known as errata, which may cause the product todeviate from published specifications. Current characterized errata are available on request.• Intel Virtualization Technology requires a computer system with a processor, chipset, BIOS, virtual machine monitor (VMM) <strong>and</strong>applications enabled for virtualization technology. Functionality, performance or other virtualization technology benefits will varydepending on hardware <strong>and</strong> software configurations. Virtualization technology-enabled BIOS <strong>and</strong> VMM applications are currently indevelopment.• Intel® Turbo Boost Technology requires a Platform with a processor with Intel Turbo Boost Technology capability. Intel Turbo BoostTechnology performance varies depending on hardware, software <strong>and</strong> overall system configuration. Check with your platformmanufacturer on whether your system delivers Intel Turbo Boost Technology. For more information, seehttp://www.intel.com/technology/turboboost• No computer system can provide absolute security under all conditions. Intel® Trusted Execution Technology (Intel® TXT) is a securitytechnology under development by Intel <strong>and</strong> requires for operation a computer system with Intel® Virtualization Technology, a Intel®Trusted Execution Technology-enabled Intel processor, chipset, BIOS, Authenticated Code Modules, <strong>and</strong> an Intel or other Intel®Trusted Execution Technology compatible measured virtual machine monitor. In addition, Intel® Trusted Execution Technologyrequires the system to contain a TPMv1.2 as defined by the Trusted Computing Group <strong>and</strong> specific software for some uses.• 64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers<strong>and</strong> applications enabled for Intel® 64 architecture. Performance will vary depending on your hardware <strong>and</strong> software configurations.Consult with your system vendor for more information.• Intel, Intel Xeon, Intel Core microarchitecture, <strong>and</strong> the Intel logo are trademarks or registered trademarks of Intel Corporation or itssubsidiaries in the United States <strong>and</strong> other countries.• * Other names <strong>and</strong> br<strong>and</strong>s may be claimed as the property of others.• © 2008 St<strong>and</strong>ard Performance Evaluation Corporation (SPEC) logo is reprinted with permission

<strong>Silicon</strong> <strong>Photonics</strong>’ FutureFilterECLDriversModulatorMultipleChannelsCMOSCircuitryTIATIAPassiveAlignmentPhotodetector45www.intel.com/go/sp© 2011, Intel Corporation. All Rights Reserved

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