A Power Gating Switch for Low Power 8 Bit CMOS Full Adder Circuit

e tInternational Journal on Emerging Technologies 4(1): 32-38(2013)ISSN No. (Print) : 0975-8364ISSN No. (Online) : 2249-3255A Power Gating Switch for Low Power 8 Bit CMOSFull Adder CircuitSaima Ayyub and Awadhesh. K.G. KanduDepartment of Electronics and Telecommunication,Lakshmi Narain College of Technology, Bhopal, (MP)(Received 05 November, 2012, Accepted 21 February, 2013)ABSTRACT: In most recent CMOS feature sizes (e.g., 90nm and 45nm), leakage power dissipation hasbecome an overriding concern for VLSI circuit designers. International technology roadmap forsemiconductors (ITRS) reports that leakage power dissipation may come to dominate total powerconsumption. Leakage is mainly due to the scaling of CMOS. There are static and dynamic (switch mode)power losses occurs in CMOS circuit, in which static power is more important for sleep mode (nooperation mode), leakage reduction improves the efficiency of the circuit, thereby saving a significantamount of energy. In static mode power consumption is the major drawback, As the biasing is remain inthe internal circuit of the system there will be more sources of leakage in the internal circuits. In nanoscale there are many sources (low threshold voltage, very thin gate oxide layer and band to bandtunneling) which are responsible for the leakage of current. This paper propose an approach of using apower gating switch (PGS) to minimize the leakage of power because of fine scaling of CMOS. Thepurpose of employing PGSs in circuits is to reduce sleep power by strongly shut off the leakage pathsduring sleep modes, means there is no close loop between supply and ground. In this method at stand bycondition leakage current will be minimized. Circuits are simulated in MICROWIND using 90nm and45nm CMOS technology. The simulations will show leakage consumption can greatly be reduced by usingthe proposed power-gating switch compared with the MTCMOS power-gating Technique.Keywords: MTCMOS, power gating switch, sleeps mode, standby mode, sub-threshold leakage, ClockAdiabatic Logic (CAL)However, as the feature size shrinks, e.g., to 45 nmI. INTRODUCTIONand 90nm, static power has become a great challengefor current and future technologies. This dissertationimplements 4bit and 8 bit CMOS parallel addercircuit with an addition of clocked adiabatic logicwith a power gating switch consisting of sleeptransistor to minimize the leakageComponents of Power Dissipation areThere are several sources for the leakage currents: (i)sub threshold leakage current due to very lowthreshold voltage (VT), (ii) gate leakage current due tovery thin gate oxide ( TOX), (iii) Band -to-Bandtunneling leakage current due to heavily doped halo.As a result of an exponential dependency on thereduction of the threshold voltage, sub-thresholdleakage has the potential to become the dominantfactor in sub-100nm generations [2, 3].Most recent CMOS feature sizes ( e.g., 90nm and45nm), leakage power dissipation has become anoverriding concern for VLSI circuit designers.International technology roadmap for semiconductors(ITRS) reports that leakage power dissipation maycome to dominate total power consumption. Powerconsumption of CMOS consists of dynamic and staticcomponents. Dynamic power is consumed whentransistors are switching or active and static power isconsumed regardless of transistor switching.Many previously proposed techniques, such asvoltage and frequency scaling, on dynamic powerreduction.Pavg = Pswitchin+Pshort-circuit+Pleakage2C .V F +I .V +I .VL DD clk SC DD Leakage DDThere are many reasons for which leakage powerlosses occurin CMOS circuit [3].• Sub-threshold leakage (weak inversioncurrent)• Gate oxide leakage (Tunneling current)• Channel punch through• Drain induced barrier lowering

Ayyub and Kandu 33Fig. 1. Leakage power components in CMOS.The sub-threshold leakage dissipation can be reducedsignificantly by controlling the threshold voltage ofthe devices. Various circuit techniques to control thesub-threshold leakage involve source biasingtechnique, input vector control technique, dualthresholdCMOS, power-gating techniques withmulti-threshold CMOS (MTCMOS), and variablethreshold CMOS (VTCMOS), However, thesetechniques.Adiabatic logic is a promising low-power method toreduce the energy dissipation in digital circuits.Several adiabatic logic families and their applicationshave been reported and achieved considerable energysavings [5-7]. Similar to power-gating techniques ofconventional CMOS circuits, power-gating schemesfor adiabatic circuits have been also introduced toreduce energy loss during idle periods [8-9].However, the previously reported power-gatingadiabatic circuits are mostly investigated for reducingtheir dynamic energy dissipations during idle periodsrequire significant circuit modification andperformance overhead for leakage reduction [6-7].This dissertation implements 4bit and 8 bitCMOS parallel full adder circuit with an addition ofclocked adiabatic logic with a power gating switchconsisting of sleep transistor to minimize the leakageII. CLOCKED ADIABATIC LOGICThe adiabatic logic structure dramatically reduces thepower dissipation. The adiabatic switching techniquecan achieve very low power dissipation, but at theexpense of circuit complexity. Adiabatic logic offers away to reuse the energy stored in the load capacitorsrather than the traditional way of discharging the loadcapacitors to the ground and wasting this energy. Inthis thesis work, a new CMOS logic family calledADIABATIC LOGIC, based on the adiabaticswitching principle is presented. The term adiabaticcomes from thermodynamics, used to describe aprocess in which there is no exchange of heat with theenvironment.The supply voltage in adiabatic circuits inaddition to providing the power to the circuit behavesas the clock of the circuit and for this reason is calledpower clock. One of the main concerns in theadiabatic logic circuits is the power clock generation.In these circuits the supply voltage is desired to be aramping voltage.Although. it can be approximated by a sinusoidalvoltage The improved CAL buffer is shown in Fig.2(a) [7][9]. The logic evaluation circuit consists of thetwo NMOS transistors (N1, N2). CX is an auxiliaryclock signal, and it enables the evaluation NMOStransistors (N1, N2) by turning on the NMOStransistors (N5, N6). The energy recovery circuitconsists of the two cross-coupled PMOS transistors(P1, P2).power-clock ( clk) charges the output ( OUTor OUTb) in evaluation phase through P1 and P2. Inrecovery phase, the energy of the output nodes isrecovered to clk through P1 and P2. The clamptransistors (N3 and N4) ensure stable operat ion bypreventing from floating of the output nodes. Theimproved CAL circuits are supplied by a single-phasepower clock, as shown in Fig. 2(a). The two phasenon-overlap sinusoidal clocks (CX and CXb) are usedfor the auxiliary lines, as shown in Fig. 2(b). The twophasesinusoidal clocks are generated with anauxiliary clock generator, as shown in Fig. 2(c) [7].Its simulated waveforms are also shown in Fig. 2(d)Fig. 2(a). CAL Buffer Circuit [7].Fig. 2(b). Simulation Waveform.

Ayyub and Kandu 34Fig. 2(c). Clock Generator [7].Fig. 3(a). Sleep Approach.Fig. 2(d). Simulation Waveform.III. TRANSMISSION GATE FOR SLEEPAPPROACHIn the sleep approach, both (i) A n additional "sleep"PMOS transistor is placed between VDD and the pullupnetwork of a circuit and (ii) An additional "sleep"NMOS transistor is placed between the pull-downnetwork and GND. These sleep transistors turn off thecircuit by cutting off the power rails. Fig. 1 shows itsstructure. The sleep transistors are turned on when thecircuit is active and turned off when the circuit is idle.By cutting off the power source, this technique canreduce leakage power effectively.Similar to power-gating techniques ofconventional CMOS circuits, adiabatic units can bealso shut down by switching off their power-clocks toreduce energy loss during idle periods. The powergatingscheme for the improved CAL circuits isshown in Fig. 3. The transmission gate (TG) is usedas the power-gating switch, which is inserted betweenthe single phase power-clock (pc) and virtual powerclock( clk). It is used to disconnect the power-gatedCAL logic blocks during idle periods In active mode,the power-gating control signal (Active) is high, thusclk follows the power-clock ( pc). In sleep mode,Active is low, thus clk is set as low level, so that thepower gated the power-gating adiabatic logic block.Fig. 3(b). Transmission gate using sleep input in 3.Fig. 3(c). Transmission Gate timing Waveform.IV. MOTIVATIONDigital CMOS integrated circuits have been thedriving force behind VLSI for high performancecomputing and other applications related to scienceand technology. The demand for digital CMOSintegrated circuits will continue to increase in the nearfuture, due to its important silent features like lowpower ,reliable performance and improvements in theprocessing technology. Large power dissipationrequires larger heat sinks hence increased area. Costof providing power has resulted in significant interestin power reduction of non portable devices sleepenergy, which has become important in modernCMOS processes due to increasing contributions ofsub threshold and gate.

Ayyub and Kandu 35Leakage current which affects total powerconsumption, and affects battery life. Therefore wehave motivated to perform dissertation work in theaccurate relative power measurement for effectivereduction of leakage in sleep mode with lesscomplexity and no overhead in the circuit.V. PROPOSED METHODOLOGYIn this paper, we use an energy efficient power gatingtechnique for adiabatic circuits.. Transmission gateswith sleep transistors are used as the power-gatingswitches.A 4 bit and 8-bit full adder based circuits isverified using the proposed power-gating technique.Energy consumption of the CAL based circuit issimulated as a function of frequency. The proposedapproach demonstrates that the circuit reducesconsiderable amount of leakage power in the Nanoscale CMOS integrated circuits and are simulated in45nm, 90nm and 120nm technology using MICRO-WIND EDA tool.In the next clock period B, the auxiliary clock CX = 0disables the logic evaluation. The previously storedlogic state repeats at the outputs out1 and out2regardless of the inputs, so that the stage that followscan perform logic evaluation. The logic evaluation isenabled in alternate logic stages by the auxiliary clockCX and its complement CX, at half the power clockrate [7][9].The power-gating switches using a Transmission gateinserted between power-clocks clk and virtual powerclocks.They are used to disconnect the adiabatic logicblock from the power-clocks during idle periods.In order to reduce additional energy loss and obtainfull swing operation of power gating switches shouldbe energy efficient . The control signals ‘sleep’ feedthe gates of S1 and S2 respectively. The sleeptransistors S1 and S2 are high threshold voltagedevices and the logic gate transistors are standardthreshold voltage devices. This is to provide a wellbalanced trade-off between high speed and leakageloss. The CMOS circuit output can be drawn eitherbetween PUN and sleep circuit or between sleepcircuit and PDN.VI. IMPLEMENTATIONA 4 bit CMOS adder circuit is implemented in DSCHtool. Functional block is made up with adiabatic logic.A sinusoidal clock is supplied to the adiabatic logic.Power gating switch is used for providing supplyvoltage in active mode. And shut off the supply instandby mode.Fig. 4. Flow Chart.In standby mode when sleep input is 1 powerclock is disconnected from the functional block.devices s1 and s2 are high threshold devices thereforesub threshold conduction reduces at the cost ofscaling of devices in 45nm and 90 nm. Thereforereduces leakage current and thus total powerconsumption reduces.Desired power-clock frequency f, which is fed to theadiabatic block having frequency f = √1/2 LC eq In theclock period A, the auxiliary clock CX enables thelogic evaluation. For out = 0, compliment of functionblock are on, causing outb = 0 and M1 to be on, andthus allowing output out2 to closely follow the powerclock waveform.Fig. 5. Implementation of 4-Bit full adder inMICROWIND.

Ayyub and Kandu 36Table 1: Power Loss Reduction of 8 Bit CAL FullAdder Using Power Gaitng Switch at 45nmProcess Compared with Base Case.%PowerReduction(45nm)Frequency (MHz)1000 2000 3000STATIC POWER 36.3 34.2 31.7TOTAL POWER 28.2 27.1 22.0CONSUMPTIONTable 2: Power Loss Reduction of 8 Bit CAL FullAdder Using Power Gaitng Switch at 90nmProcess Compared with Base Case.Fig. 6. Implementation of 8 Bit fulladder inMICROWIND.VII. RESULTSCompared with MTCMOS, proposed scheme canwell reduce the total power consumption .At 90 nmCMOS technology, the 8 bit improved CAL adderwith proposed scheme attains energy savings of26.9% to 27.6% with the frequency changing from1000 to 3000 MHz .At 45 nm CMOS technology, the 8 bit improvedCAL adder with proposed scheme attains energysavings of 22.6.9% to 28.0% with the frequencychanging from 1000 to 3000 MHz.Table 1, 2, 3 and 4 shows the leakage powerconsumption reduction and the total powerconsumption reduction of 8 bit and 5 bit improvedCAL adders with proposed scheme compared withthe MTCMOS in 45nm CMOS technology and 90nm CMOS technology ,respectively. As we can seethat Table 1 and 2 with the scaling of reduction ofprocesses ,the leakage power loss of CAL circuits canbe reduced more effectively by using power gatingswitch.Power consumption for 8 bit adder%PowerReduction(90nm)STATICPOWERTOTAL POWERCONSUMPTIONFrequency(MHz)1000 2000 300031.6 28.2 23.621.3 18.5 15.2Table 3: Power Loss Reduction of 4 Bit CAL FullAdder Using Power Gaitng Switch at 45nmProcess Compared with Base Case.%PowerReduction(45nm)Frequency(MHz)1000 2000 3000STATIC POWER 45.6 41.3 37TOTAL POWERCONSUMPTION27.6 27 26.8Table 4: Power Loss Reduction of 4 Bit CAL FullAdder Using Power Gaitng Switch at 45nmProcess Compared with Base Case.%PowerReduction(120nm)Frequency(MHz)1000 2000 3000STATIC POWER 37.8 35.6 35.4TOTAL POWERCONSUMPTION19.1 17.3 13.2

Ayyub and Kandu 37Simulation ResultFig. 7(A). Simulation Waveform of 8 Bit CAL FullAdder at 45nm Process.Fig.7(B). Simulation Waveform of 4 Bit CAL FullAdder.Fig. 7(c). Leakage Current in 4 Bit CAL Full adder.Fig. 7(D). Timing Waveform of 4 Bit CAL FullAdder.VIII. CONCLUSIONThis paper presents designing and simulation of 8Bit and four Bit low power CMOS full adder circuit.Results shows that by introducing a power gatingswitch, leakage power loss and total power loss of 4bit and 8 bit adder can be reduced by 20-30 bypercent.REFERENCES[1]. An Adiabatic Single-Phase MTCMOS Schemefor Leakage Reduction in Nano -Scale CMOSProcesses Li Su and Jianping Hu Faculty ofInformation Science and Technology NingboUniversity Ningbo City, Zhejiang 315211, China.[2]. N.S. Kim, T. Austin,,“Leakage current: Moore’slaw meets static power”, Computer, Vol. 38(12), pp.68-75, 2003.[3]. Kaushik Roy “Leakage Current Mechanismsand Leakage Reduction Techniquesin Deep-Submicrometer CMOS Circuits”, IEEE, Vol. 91(2): 305-327, 2003.[4]. F. Fallah, M. Pedram, “Standby and activeleakage current control and Minimization in CMOSVLSI circuits”, IEICE Transactions on Electronics,pp. 509–519, Vol. E88–C (4), 2005.[5] K.K. Kim, Y.B. Kim, M. Choi, and N. Park,“Leakage minimization technique for nanoscaleCMOS VLSI,” IEEE Design and Test of Computers,vol. 24(4), Aug. 2007, pp. 322-330.

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