BOM Cost Reduction by Removing S3 State white paper

BOM Cost Reduction by Removing S3 StatePower Rail DefinitionBelow are the power rail definitions.Core Rails (VCC_S, VNN_S)The Core supplies are an output of the Intel® MVP-6 voltage regulators andsupply power to the core rails of the Intel® Atom Processor E6xx Series.1.05 V Rail (V1P05, V1P05_S)The 1.05 V rail supplies many core parts of the Intel® Atom Processor E6xxSeries. It is also used for the processor signals of the ITP-XDP debug port (ifused).1.5 V Rail (V1P5_S)The Intel® Atom Processor E6xx Series requires this power source (knownas VCCA) to run the PLL clock generators on the silicon.DDR Rails (V1P8, V0P9)The Intel® Atom Processor E6xx Series supports DDR2 memorytechnology, which requires 1.8 V for V1P8 and 0.9 V for V0P9 (VREF).3.3 V Rails (V3P3, V3P3_A, V3P3_S)The 3.3 V rail is the most prolific rail on the platform. Most circuits on theplatform use it, including the Intel® Atom Processor E6xx Series. There arethree versions of the 3.3 V rail that are generated by the voltage regulator:Main rail (V3P3),Always version (V3P3A)Sleep version (V3P3S).5 V Rails (V5_A, V5_S)There are two versions of 5 V rails:The V5_A rail, an Always version is supplied by carrier board through COMExpress* connector. This rail can be used to generate 3.3 V and DDRrails.8

BOM Cost Reduction by Removing S3 StateThe Sleep version rail, V5_S is a switched rail and is enabled in S0 only.12 V Rail (V12_S)The 12 V rail is supplied by carrier board through COM Express* connector.Most of the power rails can be derived from V12_S using an on board voltageregulator.ResultEstimated BOM Cost SavingTable 3 shows the components that are not required when S3 is removed. Italso shows the estimated BOM cost savings with this implementation.Table 3: Components not required when S3 is removedComponent Description PriceLoad Switch TPS22922YZPR $0.26Load Switch TPS22922YZPR $0.26VR AS1371 $0.43Total: $0.95Cost savings is $0.95 per board1000 boards translates to a $950 savingsPower architecture is the backbone of any electronics system. As in anydesign implementation, verification is required to ensure the original powersequence remains intact and no bugs are introduced. We powered up theLittle Bay CRB to verify the design implementation. During preliminarytesting, it was booted in Windows XP SP3* and run for a period of 24 hours.Board vendors are encouraged to follow this approach to further validate thisimplementation.9

BOM Cost Reduction by Removing S3 StateConclusionThis white paper gives an overview of System Sleeping Power States (S-States). It provides background understanding on why extra sleep states arenot required in certain applications, such as industry control and In-Vehicle-Infotainment (IVI).By removing the S3 state from the boot up sequence, developers can removeunnecessary components from the system, saving money and board realestate.Board vendors are encouraged to follow this approach. This ensures reliabilitybefore implementing the new system on their embedded system.10

BOM Cost Reduction by Removing S3 StateThe Intel ® Embedded Design Center provides qualified developers with webbasedaccess to technical resources. Access Intel Confidential designmaterials, step-by step guidance, application reference solutions, training,Intel’s tool loaner program, and connect with an e-help desk and theembedded community. Design Fast. Design Smart. Get started today.http://intel.com/embedded/edc.AuthorAmy Chong Yew Ee is an Online Sales Account Manager with the APACOnline Sales Center at Intel Corporation.AcronymsS-StatesC-StatesIVIPLCACPIRTCCRBPLLMVP-6VRSystem Sleeping Power StatesProcessor Power StatesIn-Vehicle-InfotainmentProgrammable Logic ControllerAdvanced Configuration and Power InterfaceReal Time ClockCustomer Reference BoardPhase-locked loopMobile Voltage Positioning-6Voltage Regulator11

BOM Cost Reduction by Removing S3 StateINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NOLICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUALPROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMSAND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITYWHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TOSALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TOFITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT,COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS OTHERWISE AGREED INWRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANYAPPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATIONWHERE PERSONAL INJURY OR DEATH MAY OCCUR.Intel may make changes to specifications and product descriptions at any time, without notice.This paper is for informational purposes only. THIS DOCUMENT IS PROVIDED "AS IS" WITH NOWARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY,NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISEARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. Intel disclaims all liability, includingliability for infringement of any proprietary rights, relating to use of information in this specification.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is grantedherein.Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.*Other names and brands may be claimed as the property of others.Copyright © 2011 Intel Corporation. All rights reserved.§12