Design Support - UMC

F O U N D R Y L E A D E R S H I P F O R T H E S o C G E N E R A T I O Nwww.umc.comDesign Support

Design Support SolutionsOverviewUMC's Design Support Solutions provide customers with apractical and cost effective environment from RTL designs to GDS2tape-outs. The fundamental IP solutions include speed and areaoptimized standard cell libraries, I/O libraries with patented ESDprotection, and embedded memory compilers.The platform-based IP solutions enable customers to easilydevelop specific products such as baseband chips, DTV controllers,audio player controllers, digital camera controllers, etc. The lowpower design flow provides customers with a quick start for SoCdesigns in advanced technologies. Cost effective DFM solutionsoffer customers practical DFM methodologies that are seamlesslycompliant with current SoC designs flows. The foundry designkits provide customers a quick and convenient analog designenvironment with Optimized Capacitor Finder (OCF), OptimizedInductor Finder (OIF) and Optimized Transformer Finder (OTF).Fundamental IPStandard Cell LibrariesUMC's standard cell libraries are optimized forUMC's advanced technologies including 90nm,65nm, 40nm and 28nm. They provide richfeatures including multiple threshold voltagesupport, over-drive capabilities, density up to3120 K-gate/mm 2 at 28nm, multi-Vdd operations,and DFM compliance.25002000150010005000Kgates/mm 240nm2X smaller65nm90nm180nm130nm250nmGate Density9060300ps250nm 35% faster180nm130nm90nm65nm40nmGate DelayStandard I/O LibrariesWith patented ESD protection techniques, UMC's standard I/O libraries provide the best functionality for SoC connectivity. In addition to16mA fan-out driving, the I/O cells have a compact cell area at advanced nodes with Bonding Over Active Circuit (BOAC) support. AnalogI/O & power cells are also available.Embedded Memory CompilersEmbedded memories are generally required forSoC designs. UMC offers complete embeddedmemory generators for designers' convenience.These include single port SRAM, dual port SRAM,1-port register files, 2-port register files, andROM. The bit cells are built with HVt or RVt MOStransistors for low power designs in advancedtechnologies.Feature HV CIS 0.25um 0.18um 0.13um 90nm 65nm 55nm 40nm 28nmStandard CellStandard I/OAnalog I/OSingle Port SRAMDual port SRAM - -1-port Register File -2-port Register File - -ROM

Analog IPPlatform based IP solutionsWith a complete platform based IP portfolio,customers are able to seamlessly deploy theirrequired IP for specific SoC products, such asbaseband SoCs, digital TV controllers, cameracontrollers and audio players.Summary of IP PortfolioPLL, USB, LVDS,ADC/DAC,EmbeddedMemory,HDMI, DDR2PLL, USB, LVDS,ADC/DAC,HDMI, SATA,EmbeddedMemoryDTVDigital CameraMobile DDR, PLL,ADC/DAC,LVDS, USB,EmbeddedMemoryPLL, USB, LVDS,ADC/DAC,EmbeddedMemoryBasebandAudio PlayersVideo IP PLL Specialty I/O High Speed Interface PHYDAC 10-bit , 3-ch100Mhz HSTL Class I & II PCIe 1.0 & 2.0HDMI TX / Rx Deskew 200Mhz LVDS, 1G bit/s SATA I & IILVDS 400Mhz PECL, 500MHz DDR II & III100Mhz SSTL Class I & II USB 2.0 & OTGMultiplier200Mhz400MhzEmbedded Memory MacrosIn the modern SoC era, memory becomes an important and essential IP requirement for SoC design. UMC offers state-of-the-artembedded memory solutions to meet a variety of applications for 4C markets.High quality embedded non-volatile memory (eFuse, eOTP, eMTP, eEEPROM and eFlash) can be used for trimming, redundancy, dataencryption, ID, coding and programming.In addition, UMC's proprietary URAM TM is an ideal solution for higher density memory requirements. The important features of URAMare smaller form factor, higher bandwidth/speed and lower power consumption compared to traditional embedded 6T-SRAM.These comprehensive IP solutions have been helping UMC customers maximize the performance potential of their SoC designs.UMC Embedded Memory ProfilesUMC offers a comprehensive embeddedmemory profile. Customers have manyoptions to help customize their SoCdesigns.Furthermore, UMC embedded memoryis logic process compatible. The logicstandard cell (SC) and I/O can be adopteddirectly into UMC embedded memory.eFlash/EEPROMDOTPDMTPD D DeFuseDURAM TM 0.35um 0.25um 0.18um 0.162um 0.13um 0.11um 90nm 65nm 40nm 28nm/0.153um/80um /55umAvailableDDeveloping

Low Power DesignWith today's proliferation of low powerapplications, lowering energy consumptionwithout sacrificing performance has becomea critical concern for chip designers. UMC iscommitted to providing customers withCritical Area Analysisthe latest low power solutions, includinglow power and low leakage transistoroptions using advanced technologies. UMCdevelops multi Vt reference flows for lowpower designs. For advanced low powersolutions, UMC provides low power kitsas well as UMC libraries. Related referenceEDA flows are also available upon request.These resources provide customers witha streamlined path to manufacturing,allowing UMC customers designing powerefficientSoC projects to capitalize on today'slow power market opportunities..Power Consumption TrendsPower ConsumptionLeakage PowerDynamic Power0.25um 0.18um 0.13um 90nm 65nmTechnology NodesLow Power Design SupportTo reduce overall power consumption, designers have to take action during both front-end and back-end design stages. As shown inthe following chart, UMC is delivering convenient design solutions to support designers at each stage.Front-end designLow leakageprocessPowergatingMulti VthMulti VDDLow powersynthesisClockgatingVoltage andfrequency scalingBody biasBack-end design80%60% 40% 20% 20% 40% 60% 80%Leakage Power SavingDynamic Power SavingLow Power Design SolutionsTypeSupport FeaturesSupport28nm 40nm 65nm 90nm 0.13umDynamic PowerVoltage Island& ScalingClock Gating &Frequency ScalingLevel Shiftersw / InsulatorPower & TimingModel @ 80% of VddÞ Þ Þ Þ ÞClock Gated F/F Þ Þ Þ Þ ÞMulti-Vt Multi-Vt cells Þ Þ Þ Þ ÞLeakage PowerPower GatingIsolation cells, Retention F/FHeaders / Footers, etc.Þ Þ Þ Þ ÞBody BiasTapless cellsTiming / PowerModel (1) Þ Þ Þ Þ ÞTiming and power models will be supported according to each customer's particular requirements.

Low Power Reference Design FlowAdvanced leakage reduction techniques are demonstrated with low power reference design flow examples – Multi-Vdd Design withestablished voltage island, Multi-Vt Optimization, and advanced power gating technologies.Multi-Vdd DesignsMulti-Vdd designs are common in advanced technologies. In addition to data retention circuitry and timing considerations, UMC alsosupports designers to optimize voltage island placement surrounded by appropriate level shifters. The left is the example of the voltageisland establishment.Level Shifter CellsVoltage IslandCreate Voltage AreaLevel Shifter PlacementMulti-Vt OptimizationMulti-Vt optimization can be performed using a two-phase leakage reduction flow. This enables optimized results for cell swaps,where low threshold voltage standard cells are replaced with high threshold voltage standard cells. The result is an 83% leakage powerreduction in 0.13um technology.Design ImplementationFloorplanPostPlace Leakage PowerOptimizationsSi Driven RoutingPost Route Leakage PowerOptimizationThe Two-Phase Leakagereduction flow can beperformed using PostPlace & Route LeakagePower Optimization.PhysicalVerificationSoC EncounterExperimental Results100%FDK EDA Supported Tools80080%60%40%20%600Synopsys4002000%Spectre Placement PostPlace Eldo Routing PostRoute Opt.ADSSpectreRFEldoRFHVT cells (%) LVT cells (%) Leakage power (uW)83% leakage reduction (uW) Clock Speed 333Mhz0Gate CountHSPICEProcessAbout 1 million gatesUMC 0.13um 1P8M

Power Gating SolutionUMC's power gating solution takesadvantage of high threshold-voltagetransistors or sleep transistors in circuitblocks that switch infrequently. Thisresults in zero standby currents during theinactive state. The goal of power gating isto minimize leakage current by temporarilyswitching off power to blocks that are notrequired in the current operating mode.In our low power kits, we also designedisolation cells to prevent crowbar current.For the advanced purpose of retaining theinternal state of the block during powerdown and restoring the state duringpower up, we also implemented retentionVirtuoso XLregisters in place of ordinary flip-flops. Theresult is a 70x leakage power reduction for65nm technology through a proper designimplementation strategy.Primary power netVDDLSVDD1ISOVSSPrimary ground netTop designVDDVDD1VSSu1PGRRPrimary power netPrimary ground netCORETOPFoundry Design Kit (FDK)The Foundry Design Kit provides IC designers with an automatic design environment that eliminates unnecessary manual tasks andensures successful mixed signal and RF IC tape-outs. The FDK includes parameterized cells (P Cell), which have a schematic layout toprovide an automatic and complete design flow. Callback functions are also provided in the design flow to minimize data entry.In addition, UMC has worked with industry leading EDA tool partners to deliver fast and accurate 3D electromagnetic simulation toolsfor RF chip designs, including Virtual Capacitor Library (VCL), Virtual Inductor Library (VIL), and Virtual Transformer Library (VTL). UMChas also implemented Optimized Capacitor Finder (OCF), Optimized Inductor Finder (OIF), and Optimized Transformer Finder (OTF)tools deployed inside UMC’s Foundry Design Kit (FDK). These tools allow customers to make tradeoff decision between impedance andarea, Q and area, or request a specified “flatness” of inductance within a given frequency range for ultra-wideband (UWB), WiMAX, andmobile TV design.Using OIF for Optimum Inductor

Broad EDA Tool SupportUMC works closely with leading EDA toolvendors to provide a convenient, productiveand up-to-date work environment fordesigners. Tools are well supported byUMC and its EDA partners throughout theentire design process, from RTL design totapeout.Logic DesignPhysical DesignPhysical VerificationLogic Simulation Place & Route VerificationCadence NC-SimEDIAssuraCadenceMentor Model-Sim ETS QRCCadenceVCSEPSCalibreSynopsysMentorMVRC CELTIC XRCTalus VortexHerculesSynopsysLogic Synthesis Talus Power StarRC-XTMagmaCadence RTL Compiler Talus DesignQuartzMagmaTalus Design Quartz Rail QuickCapMagmaTalus PowerIC CompilerSynopsys Design Compiler Synopsys PrimeTimePrimeRailFDK Integrated FlowEDA VendorsSchematicEntryCircuitSimulationIC LayoutLVS/DRC/ LPEComposerSpectreSpecterRFVirtuosoVirtuoso XLAssuraQRCEldoEldo RFCalibreCalibre XRCADSADSHSPICEHerculesStarRC-XTCustomer SupportPartnership with ARM, Faraday & Virage• Enables prompt response from IP vendors• Feasibility assessment for customer’s requirementsFree Libraries for cost-sensitive products• Foundry library programsUMC Online support environment• IP Master sourcing• IP Help Desk

www.umc.comF O U N D R Y L E A D E R S H I P F O R T H E S o C G E N E R A T I O NNew CustomersFor new customer inquiries,please direct all questions tosales@umc.comWorldwide ContactsHeadquarters:UMCNo. 3, Li-Hsin 2nd Road,Hsinchu Science Park,Hsinchu, Taiwan, R.O.C.Tel: 886-3-578-2258Fax: 886-3-577-9392Email: foundry@umc.comIn China:UMC Beijing:Room #521, 5F, South Block,Raycom InfoTech Park, No.2,Kexueyuan South Road,Zhongguancun,Haidian District,Beijing 100190, ChinaTel: 86-10-5982225086-18913138053Fax: 86-10-59822588HeJian Technology (Suzhou):No. 333, Xinghua Street, SuzhouIndustrial Park, Suzhou, JiangsuProvince 215025, ChinaTel: 86-512-65931299Fax: 86-512-62530172In Japan:UMC Group Japan15F Akihabara Centerplace Bldg.,1 Kanda Aioi-Cho Chiyoda-KuTokyo 101-0029 JapanTel : 81-3-5294-2701Fax: 81-3-5294-2707In Singapore:UMC-SGNo. 3, Pasir Ris Drive 12,Singapore 519528Tel: 65-6213-0018Fax: 65-6213-0005In Korea:UMC Korea1117, Hanshin Intervally24, 322,Teheran-ro, Gangnam-gu,Seoul, KoreaTel: 82-2-2183-1790Fax: 82-2-2183-1794Email:korea@umc.comIn North America:UMC USA488 De Guigne Drive,Sunnyvale, CA 94085, USATel: 1-408-523-7800Fax: 1-408-733-8090In Europe:UMC Europe BVDe entree 771101 BH Amsterdam ZuidoostThe NetherlandsTel: 31-(0)20-5640950Fax: 31-(0)20-6977826For more information: visit www.umc.com or e-mail sales@umc.com 1404