systems circuits and - Virtus - Nanyang Technological University

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systems circuits and - Virtus - Nanyang Technological University

Division ofCIRCUITS ANDSYSTEMS


DIVISION OFCIRCUITS ANDSYSTEMS29INTRODUCTIONThe continuous growth in integrated circuit (IC) andelectronic design activities in Singapore has resulted inexcellent student enrolments in the Division’s final yearelectronics option as well as the IC Design SpecialistManpower Programme (SMP) and NTU-TUM MSc Coursein IC Design. Besides playing a leading role in IC designmanpower training for the nation’s expanding electronicsand IC design industries, the division has also performedextremely well in research.On 12 th January, the division signed an agreement withAdvanced RFIC (aRfic) Pte Ltd to set up the $9 millionnew research laboratory, Advanced RFIC@NTU. Thecollaboration aims to advance research anddevelopment in RFIC technology. The new researchlaboratory contains state-of-the-art equipment, includinga world-class 300 mm probe system that makes modelling,measurement and characterization of nano-RF devicesas well as integrated circuits and systems possible. Thirtypostgraduate scholarships have also been set aside toexpand the research activities in RFIC design.sharing their latest research with NTU researchers. NTUaims to build the ISNE into an international centre ofexcellence in five years and our colleagues have, to date,participated actively in 6 projects to be funded by the ISNE.On 7 th September, another new research laboratoryled by the division, the $10 million ElectromagneticEffects Research Laboratory (EMERL) set up jointlywith DSO National Laboratories, was officially openedby the Defence Minister, Mr Teo Chee Hean. The Semi-Anechoic Chamber and the Reverberation Chamberin the EMERL allow advanced ElectromagneticCompatibility (EMC) measurement for any electronicsystem up to 40 GHz. With the worldwide trend ofimposing EMC regulations on practically all electronicdevices, the setting up of the EMERL is timely for thedivision to play a key role to spearhead advanced EMCresearch that seeks to ensure that electronic devicesand systems are well designed with low electromagneticemission, as well as high electromagnetic immunity.MOU signing for the setting up ofAdvanced RFIC@NTUDefence Minister, Mr Teo Chee Hean (4 th from the left) unveilingthe commemorative plaque at the EMERL opening ceremonyOn 4 th September, NTU established the Institute forSustainable Nanoelectronics (ISNE), a new initiative led bythe division. The ISNE aims at designing and developingthe next generation of embedded IC chips which consumesignificantly less energy with low production costs. TheISNE has received a seed funding of $4 million to kick offits research activities. The ISNE strategy will be led byProfessor Krishna Palem of Rice University, who is also theCanon Visiting Professor at NTU. To officially launch theISNE, an inaugural workshop was held on 29th October withmany internationally renowned nano-electronics researchersOur colleagues have also done very well in securingresearch funding from both public and private sectors, suchas Panasonic Semiconductor, Chartered Semiconductor,SINO-American Silicon Products, ST Microelectronics,A*STAR, DSTA and DSO National Laboratoreis. The totalfunding secured is close to $4 million, covering researchareas in VLSI, RFIC, Reliability and EMC, which are inline with our division’s long-term research capability inSystem-on-Chip (SoC). A CRP research proposal from ourcolleagues has also been shortlisted by NRF despite keencompetition at the international-level.[ Nanyang Technological University • School of Electrical & Electronic Engineering ]


30DIVISION OFCIRCUITS ANDSYSTEMSHighlights of Research ActivitiesWith all these newly added research facilities, researchinitiatives and a strong research team, the division is wellpositioned to build up System-on-Chip (SoC) capabilityfor the realization of many SoC systems. Amongst theseare Software Defined Radio (SDR) systems that can beeasily configured to operate at many existing and futureworldwide air-interface standards, and ultimately to becomethe universal mobile communication system.400μmGND OUT GND VcontGND VDD GND620μmIn this report, the division would like to highlight some of itsresearch achievements.One main component in microwave receivers is theVoltage-Controlled Oscillator (VCO). The unity frequencyft, the frequency where the transistor current gain becomesunity for 0.18μm, is about 40 GHz for optimum biasing. Ina circuit with large biasing swing like a VCO, ft can be aslow as 15 GHz. This proves to be a major problem for VCOdesign as the VCO needs to work at 24 GHz. In addition,other parameters such as tuning range and phase noisecould be greatly affected by the low unity frequency. Thedivision has developed a VCO with an oscillation frequencyof 23 GHz using a CMOS transistor with ft of 15.8 GHz.Based on the 0.18μm CMOS process, our colleaguesdemonstrated that using novel push-pull buffer, a VCO canoperate up to almost double the unity frequency.Microphotograph of the 23-GHz VCOHigh-speed Digital Signal Processing (DSP) is a dedicatedmodule that has to cope with the complexity and diverseprocessing requirements and specifications of differentSoC systems. Traditional techniques for multiplierlessfiltering involve optimizing the digital filter coefficients insigned power-of-two (SPT) coefficient space, and thus thecoefficient multiplications are replaced by additions andshifts. However, the design of digital filters with discretecoefficient values may not always be possible in someapplications such as in adaptive filtering. The division hasdeveloped a new technique where signals are convertedinto a sum of a limited number of SPT terms. Since hardwarecircuitry for the real time conversion is available, the filteris also multiplierless even though the coefficient values arenot SPT. The new technique can handle very complex signalprocessing needs with low power consumption.IC Reliability is another important aspect of IC design,especially with the continuous reduction in line widthand the increase in the number of metallization layers.Our colleagues have developed a physical modelof the electromigration that allows accurateprediction the failure sites for interconnectswith different line widths and structures undervarious stress conditions. With the model, differentcategories of failure mechanisms can be predicted forfailure analysis.[ Nanyang Technological University • School of Electrical & Electronic Engineering ]


DIVISION OFCIRCUITS ANDSYSTEMS31abM2dummy lineVoide-flowMax4.54x10 27 3.75x10 29 7.46x10 291.90x10 29 5.61x10 29 9.32x10 29(a) FIB-SEM image of failed sample, (b) total AFD distribution at M1 test condition.Comparison of quantization error of the new technique(solid lines) and the measured results (histogram plots)With high-speed electronic systems operating at sub-nanosecond edge rates, board-level integration becomes avery challenging task. The interconnects begin to behaveas transmission lines. In addition, parasitic effects due tointer-layer vias, interconnect bends and gaps in groundplane, start to show their impacts on circuit performanceat these edge rates. Hence, Signal Integrity (SI) and EMCare becoming major issues for high-speed board design.The SI and EMC issues, if not properly resolved, will lead tounstable and intermittent operation problems. The researchgroup in EMERL has done extensive research work anddeveloped a systematic design methodology in SI/EMCcompliant high-speed designs.Near-field electromagnetic scanning results indicatinghot-spot areas that are causing SI/EMC problems[ Nanyang Technological University • School of Electrical & Electronic Engineering ]


32DIVISION OFCIRCUITS ANDSYSTEMSCENTRE FOR INTEGRATED CIRCUITS AND SYSTEMSThe Centre for Integrated Circuits & Systems (CICS) has18 active full-time academic staff, 4 Research Fellows, 10Research Associates, 3 Project Officers and 14 TechnicalStaff. Its research activities are focussed in three areas,namely RF Integrated Circuits and Systems, Analog/Mixed-Signal IC, and VLSI Design and Embedded Systems,with academic staff strengths of 5, 7, and 5 respectively.Most projects concern the design and analysis of devices,circuits and sub-systems of the final SoC (System onChip) products, with or without the embedded software.The RF Integrated Circuits and Systems group has 5academic staff, 6 research staff and 23 research students.Its research focuses on RF IC design for wireless & mobilecommunications, RF modelling and characterization fordeep sub-micrometer semiconductor devices, on-waferinterconnects and coupling, RFIC testing, ultra high speedclock-data-recovery, RF System-on-Chip, RF System-in-Package, Integrated Circuit Package Antenna, and EMC/EMI in RF integrated circuits and systems. At present thereare 6 on-going research projects with an aggregate fundingof some $2 million, the major part of the funding comesfrom external sources. The major research strengths ofthe group are Ultra Low Power RFIC designs for wireless,mobile and biochips applications. The research activitiesof the Analog/Mixed-Signal IC group are focussed on dataconverters, low-voltage low-power mixed signal circuits, andhigh-performance asynchronous digital signal processors.This group currently has a total research funding of some$2 million. In VLSI Design and Embedded Systems, theresearch activities cover a diversity of topics pertaining tothe development of novel algorithms, efficient hardwarearchitectures and design methodologies towards VLSI andembedded application solutions. The group has 2 majorprojects with a funding of $700,000.Some of the major projects and significant achievements aredescribed below.20-GHz High-FrequencyCMOS T/R Switch IC DesignOBJECTIVEA novel IC design method and topologyfor CMOS Transmit/Receive switch designtowards wideband and 20-GHz high frequencyapplications have been invented.Its novel design supports a wide range of wirelessapplications that require broadband and high frequency.The layout technique for switch transistor overcomesdrawbacks due to drain-source interconnections. Theseries-only topology saves chip area and reduces designcomplexity. The double-well body-floating techniqueovercomes drawbacks of excessive chip area in LCtunedtechniques. The switched body-floating techniqueovercomes the negative effects of body-floatingtechniques. The differential topology improves powerhandling capability and offers better signal quality.A 20-GHZ CMOS T/R Switch[ Nanyang Technological University • School of Electrical & Electronic Engineering ]


DIVISION OFCIRCUITS ANDSYSTEMS33Intelligent ISFET Sensory Systemfor Water Quality MonitoringOBJECTIVEThis project is to research a new intelligentISFET sensory system dedicated to precision pHsensing function, along with long-term monitoringcapability for water quality monitoring inenvironmental applications whilst not jeopardizingthe accuracy by any temperature and timefluctuations.variant compensation algorithm together with hardware andsoftware co-design, the sensing performance of the readoutIC is significantly enhanced even using standard ISFETsensing device.Using semiconductor theory and innovative circuit designtechnique, a novel readout IC has demonstrated thattemperature compensation can be accomplished withouttemperature sensor. Further incorporating generic time-An Intelligent ISFET Water Quality Sensory SystemLow Power Low Voltage8 Bit 200 MS/s Pipelined ADCOBJECTIVEThe ADC was designed for applications inbroadband wireless communications andoptimized for IEEE 802.11 standards.The achievement of high speed and ultra low poweroperation (200 MS/s @ 22 mW) sets a new benchmark inADC design. The design uses a novel mixed-mode samplingand holding technique which reduces signal swings in thepipelined ADC while maintaining the signal-to-noise ratio.The reduction of signal swings relaxes the op amp gain,slew rate, bandwidth and capacitor matching requirementsin pipelined ADCs. Thus, single stage op amps and smallcapacitor sizes can be used in this pipelined ADC, leadingto a high speed and low power consumption. The linearity ofthe ADC is also improved due to the reduced signal swing.The performance of the ADC is summarized in Table 1.Table 1. Performance SummaryTechnology0.18 μm 2P6M CMOSResolution8 bitsSampling Rate 200 MS/sSupply Voltage 1.8VInput Range0.8V ppDNL/INL0.30 LSB / 0.34 LSBSNDR (ƒ in = 40MHz) 45.2 dBSNDR (ƒ in = 99MHz) 44.2 dBSFDR (ƒ in = 40MHz) 60.4 dBSFDR (ƒ in = 99MHz) 53.4 dBActive Area0.8 mm x 0.4 mmPower Consumption 22 mWA Low Power Low Voltage 8 bit 200 MS/s Pipelined ADC[ Nanyang Technological University • School of Electrical & Electronic Engineering ]


34DIVISION OFCIRCUITS ANDSYSTEMSStaffMembers1 st Row (From left to right)Head of DivisionYeo Kiat SengAssociate ProfessorDeputy Head of DivisionSee Kye YakAssociate ProfessorAssistant Head of DivisionGoh Wang LingAssociate ProfessorProfessorDo Manh Anh2 nd Row (From left to right)Associate ProfessorsChan Pak KwongChang Chip HongChang, Joseph SylvesterAssociate Dean, College of Engineering(1 April 2006 - 31 March 2007)Gwee Bah Hwee3 rd Row (From left to right)Associate ProfessorsHo Duan JuatJong Ching ChuenKoh Liang Mong4 th Row (From left to right)Associate ProfessorsLam Ying Hung, YvonneLau Kim TeenProgram Director,MSc (Consumer Electronics)MSc (IC Design)Lim Meng Hiot[ Nanyang Technological University • School of Electrical & Electronic Engineering ]


DIVISION OFCIRCUITS ANDSYSTEMS35StaffMembers1 st Row (From right to left)Associate ProfessorsNg Lian SoonOng Keng Sian, VincentSiek LiterTan Cher Ming2 nd Row (From right to left)Associate ProfessorZhang Yue PingAssistant ProfessorsBoon Chirn ChyeTiew Kei TeeTan Meng Tong3 rd Row (From right to left)Assistant ProfessorYu YajunTeaching FellowsAlper CabukKong Zhi Hui4 th Row (From right to left)Associate Professorial FellowsChua Hong Chuck@Chua Hong ChuekOoi Tian Hock@Wei Ten FookWong Mong Chung, EddieTang Hung Kei[ Nanyang Technological University • School of Electrical & Electronic Engineering ]


36DIVISION OFCIRCUITS ANDSYSTEMSResearchInterestCIRCUITS AND SYSTEMS1Boon Chirn ChyeAssistant ProfessorRFIC Devices, Circuits and Systems Design, PLL Frequency SynthesizerDesign, Biomedical Consumer Electronic.2Chan Pak KwongAssociate ProfessorBiomedical Circuits and Systems, Sensor Interfaces, Mixed-Signal Circuitsand Systems.3Chang Chip HongAssociate ProfessorComputer Arithmetic, VLSI Design, Design automation, Digital SignalProcessing.4Chang, Joseph SylvesterAssociate ProfessorAcoustics, Audiology, Electronics, IC Design, Analogue and Digital SignalProcessing, Biomedical Engineering, Pyschophysics.5Chua Hong ChuckAssociate ProfessorialFellowHigh Density Multilayer PCB Design, System Integration (Noise & signalintegrity), Embedded Systems for Security.6Do Manh AnhProfessorBiomedical Electronics, Digital Communications, R.F. Circuits and Systems,Acoustics.7Goh Wang LingAssociate ProfessorDevice Processing, Device Characterization, and IC Design.8Gwee Bah HweeAssociate ProfessorAsynchronous & Digital Class-D Amplifier IC Designs, Acoustic NoiseReduction.9Ho Duan JuatAssociate ProfessorVideo Coding, System Level Digital Design, ASIC Design.10Jong Ching ChuenAssociate ProfessorHigh-Level Synthesis, Parallel Computation and Reconfigurable Systems.11Koh Liang MongAssociate ProfessorMachine Vision, Energy Saving Electronic Converters.12Lam Ying Hung, YvonneAssociate ProfessorMixed-signal IC Design, Analogue Design Automation.13Lau Kim TeenAssociate ProfessorLow power IC Design, Self-timed CMOS Circuits, Subthreshold CMOSCircuits.14Lim Meng HiotAssociate ProfessorComputational Intelligence, Embedded Systems, AI in Finance,Fuzzy/neural Hardware, Combinatorial Optimization.15Ng Lian SoonAssociate ProfessorAnalogue CMOS circuits, DAC/ADC, Micropower Circuits, AnalogueBipolar Circuits.16Ong Keng Sian, VincentAssociate ProfessorMaterials and Device Characterization, Analysis and Modelling, ElectronBeam Techniques, EBIC Metrology.17Ooi Tian HockAssociate ProfessorialFellowRF Circuits and Systems, ASIC, DSP in Consumer Electronics Applications,Factory Automation, Quality and Reliabilty, EMC/EMI/EMS.18See Kye YakAssociate ProfessorComputational Electromagnetics, Electromagnetic Compatibility andSignal Integrity.19Siek Liter @ Hsueh LiterAssociate ProfessorLow-power Low-voltage Analog/Mixed Signal CMOS/Bipolar IC Design.20Tan Cher MingAssociate ProfessorNanoelectronics, ULSI Interconnect Reliability, Wafer Bonding, Reliabilityand Maintenance Engineering.21Tan Meng TongAssistant ProfessorVLSI Design, Class D Amplifiers, Analog and Digital Signal Processing,Biomedical Engineering.22Tang Hung KeiAssociate ProfessorialFellowTechnopreneurship, Management of Innovation and Technology.[ Nanyang Technological University • School of Electrical & Electronic Engineering ]


ResearchInterestCIRCUITS AND SYSTEMSDIVISION OFCIRCUITS ANDSYSTEMS3723Tiew Kei TeeAssistant ProfessorAnalog and Mixed-signal IC Design, Delta-sigma Modulators,Bio-instrumentation.24Wong Moon Chung, EddieAssociate ProfessorialFellowBiomedical Instrumentation, Image Processing, Robotics And Automation,Digital Test Generation and DFT.252627Yeo Kiat SengYu YajunZhang Yue PingAssociate ProfessorAssistant ProfessorAssociate ProfessorDevice Modeling, RFIC Design, Low-voltage Low-power IC Design.VLSI Digital Signal Processing, VLSI Circuits and Systems Design.Wireless Chip Area Network, Single-chip Radio, and Radio Bioelectronics.PhD & MEngDegrees Awarded in 2007PhD - CIRCUITS AND SYSTEMSS/NO.PROJECT TITLE STUDENT SUPERVISOR/CO-SUPERVISOR1Design and implementation of a reconfigurable fuzzy inference processorCao QiLim Meng Hiot2Flicker noise fluctuations in deep submicron MOSFETsChew Kok Wai,JohnnyYeo Kiat Seng3Design and implementation of a low energy fast fourier transform/inverse fastfourier transform (FFT/IFFT) processor based on asynchoronous-logicChong Kwen SiongGwee Bah HweeChang, Joseph Sylvester4Performance analysis and integrated circuit design for ultra-wideband transceiverLi QiangZhang Yue Ping5Novel methodologies for miniaturized filter designs and realizationMa KaixueYeo Kiat SengMiao Jianmin6Dual band low-noise amplifier designs for bluetooth and hiperlan applicationsMou ShouxianYeo Kiat Seng7Characterization and modeling of on-wafer interconnects for RFICsShi XiaomengYeo Kiat SengLi Erping8Study of chip scale wireless interconnect systems and their antennasSun MeiZhang Yue PingGuo Lihui91011Algorithms for synthesis and optimization of multiplierless FIR filtersNew self-organizing algorithms for topological mapsiMeta-heuristic algorithm development for combinatorial optimization within anintegrated problem solving environmentXu FeiXu PengfeiXu YiliangJong Ching ChuenChang Chip HongLim Meng Hiot12Digital image enhancement algorithm for 2-D ultrasound imaging systemZhang FanKoh Liang Mong13Speckle removal in medical ultrasound images by compounding and filteringZhang LichenWong Moon Chung, EddieMEng - CIRCUITS AND SYSTEMSS/NO.PROJECT TITLE STUDENT SUPERVISOR/CO-SUPERVISOR1Fast finite field multipliers for public key cryptosystemsSatzoda Ravi KumarChang Chip Hong2An integrated platform for design & verification of digital FIR filtersSharma UditJong Ching Chuen[ Nanyang Technological University • School of Electrical & Electronic Engineering ]


38DIVISION OFCIRCUITS ANDSYSTEMSSelectedPublications in 2007List of Selected Publications - CIRCUITS AND SYSTEMS123456Aaron V. Do, C. C. Boon, M. A. Do, K. S. Yeo and A. Cabuk, "A Subthreshold Low-Noise Amplifier Optimized for Ultra-Low-PowerApplications in the ISM Band", accepted, IEEE Trans. on Microwave Theory and Techniques, 2007.K. M. Lim, C. Y. Ng, K. S. Yeo, M. A. Do and C. C. Boon, "A 2.4GHz Ultra Low Power Subthreshold CMOS Low-Noise Amplifier",Microwave and Optical Technology Letters, vol. 49, pp. 743 - 744, February 2007.P. K. Chan and D. Y. Chen, "A CMOS ISFET Interface Circuit with Dynamic Current Temperature Compensation Technique", Special Issueon Smart Sensors, IEEE Trans. on Circuits and Systems, Part I, vol. 54, no. 1, pp. 119 - 129, January 2007.J. Peng and P. K. Chan, "Analysis of Nonideal Effects on a Tomography-Based Switched-Capacitor Transducer", IEEE Sensors Journal,vol. 7, no. 3, pp. 381 - 391, March 2007.J. K. Yin and P. K. Chan, "A Low-Jitter Polyphase Filter Based Frequency Multiplier with Phase Error Calibration", accepted, IEEE Trans.on Circuits and Systems, Part II, 2007.F. Xu, C. H. Chang and C. C. Jong, "Design of Low-Complexity FIR Filters Based on Signed-Powers-of-two Coefficients with ReusableCommon Subexpressions", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 10, pp. 1898 - 1907,October 2007.789101112131415161718Y. Shao and C. H. Chang, "A Generalized Time-Frequency Subtraction Method for Robust Speech Enhancement Based on WaveletFilter Bank Modeling of Human Auditory System", IEEE Trans. on Systems, Man and Cybernetics, Part B: Cybernetics, vol. 37, no.4, pp. 877- 889, August 2007.B. Cao, C. H. Chang and T. Srikanthan, "A Residue-to-Binary Converter for a New 5-moduli set", IEEE Trans. on Circuits andSystems, Part I, vol. 54, no. 5, pp. 1041 - 1049, May 2007.Z. H. Lu, K. S. Yeo, J. G. Ma, M. A. Do, W. M. Lim, and X. Y. Chen, "Broadband Design Techniques for Trans-impedance Amplifiers", IEEETrans. on Circuits and Systems I, vol. 54, no. 3, pp. 590 - 600, March 2007.X. P. Yu, M. A. Do, J. G. Ma, W. M. Lim, K. S. Yeo and X.L. Yan, "Sub-1V Low Power Wide Range Injection-Locked FrequencyDivider", IEEE Microwave and Wireless Components Letters, vol. 17, no. 7, pp. 528 - 530, July 2007.D. D. Chen, K. S. Yeo, M. A. Do and C. C. Boon,"A Fully Integrated CMOS Limiting Amplifier with Novel Offset CompensationNetwork", IET Electronics Letters, vol. 43, no. 20, pp. 1084 - 1085, September 2007.H. Q. Liu, W. L. Goh, L. Siek, Y. P. Zhang and W.M. Lim, "A Low-Noise Multi-GHz CMOS Multiloop Ring Oscillator with Coarse and FineFrequency Tuning", accepted, IEEE Trans. on Very Large Scale Integration Systems, 2007.K. S. Chong, B. H. Gwee and J. S. Chang, "Energy-Efficient Synchronous-Logic and Asynchronous-Logic FFT/IFFT Processors",IEEE Journal of Solid State Circuits, vol. 42, no. 9, pp. 2034 - 2045, September 2007.C. F. Chong, B. H. Gwee and J. S. Chang, "Asynchronous Control Network Optimization Using Fast Minimum Cycle Time Analysis",accepted, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 2007.K. S. Chong, B. H. Gwee, and J. S. Chang, "Design of Several Asynchronous-Logic Macrocells for a Low-Voltage Micropower CellLibrary", IET Proc. Circuits, Devices and Systems, vol. 1, no. 2, pp. 161 - 169, April 2007.A. Agarwal, M. H. Lim, M. J. Er and T. N. Nguyen, "Rectilinear Workspace Partitioning for Parallel Coverage using Multiple UAVs",Advanced Robotics, vol. 21, no. 1, January 2007.Z. Z. Zhao, Y. S. Ong, M. H. Lim and B. S. Lee, "Memetic Algorithm using Multi-Surrogates for Computationally Expensive OptimizationProblems", Soft Computing, 11(10), pp. 957 - 971, 2007.J. Tang, M. H. Lim and Y. S. Ong, "Diversity-Adaptive Parallel Memetic Algorithm for Solving Large Scale Combinatorial OptimizationProblems", Soft Computing, 11(9), pp. 873 - 888, 2007.[ Nanyang Technological University • School of Electrical & Electronic Engineering ]


SelectedPublications in 2007List of Selected Publications - CIRCUITS AND SYSTEMSDIVISION OFCIRCUITS ANDSYSTEMS3919202122232425262728293031323334J. Deng and K. Y. See, "In-circuit Characterization of Common-mode Chokes", IEEE Trans. on Electromagnetic Compatibility, vol. 49, no.2, pp. 451 - 454, May 2007.K. Y. See, P. L. So and A. Kamarul, "Feasibility Study of Adding a Common-mode Choke in PLC modem for EMI Suppression", IEEETrans. on Power Delivery, vol. 22, no. 4, pp. 2136 - 2139, October 2007.C. M. Tan and A. Roy, "Electromigration in ULSI Interconnects", Materials Science and Engineering R, 58, 1 - 75, 2007.C. M. Tan and Y. Hou, "Lifetime Modeling for Stress-induced Voiding in Integrated Circuit Interconnections", Appl. Phys. Lett., 91(6),061904, 2007.C. M. Tan and N. Raghavan, "A Framework to Practical Predictive Maintenance Modeling for Multi-State Systems", in press, ReliabilityEngineering and System Safety, 2007.K. Ma, K.S. Yeo, J.G. Ma and M.A. Do, "An Ultra-compact Hairpin Band Pass Filter with Additional Zero Points," accepted, IEEEMicrowave and Wireless Components Letters, 2007.X. M. Shi, K. S. Yeo, J.G. Ma, M. A. Do and E. P. Li, "Complex Shaped On-Wafer Interconnects Modeling for CMOS RFICs," accepted,IEEE Trans. on Very Large Scale Integration Systems, August 2007.K. Ma, K. S. Yeo, J. G. Ma, and M. A. Do, "An Ultra-Compact Planar Bandpass Filter with Open-ground Spiral for wireless Application,"accepted, IEEE Trans. on Advanced Packaging, August 2007.Q. Li and Y. P. Zhang, "A 1.5-V 2-9.6-GHz Inductorless Low-noise Amplifier in 0.13-μm CMOS," accepted, IEEE Trans. on MicrowaveTheory and Techniques, vol. 55, no. 10, pp. 2015 - 2023, October 2007.A. Poh and Y. P. Zhang, "Design and Analysis of Transmit/Receive Switch in Triple-well CMOS for MIMO Wireless Systems", IEEE Trans.on Microwave Theory and Techniques, vol. 55, no. 3, pp. 458 - 466, March 2007.Q. Li and Y. P. Zhang, "CMOS T/R Switch Design: Towards Ultrawide-band and Higher Frequency", IEEE Journal of Solid-State Circuits,vol. 42, no. 3, pp. 563 - 570, March 2007.G. Moldovan, P. Kazemian, P. Edwards, V.K.S. Ong, O. Kurniawan and C.J. Humphreys, "Low-Voltage Cross-Sectional EBIC forCharacterisation of GaN-Based Light Emitting Devices", Ultramicroscopy, vol. 107, no. 45, pp. 382 - 389, 2007.O. Kurniawan and V.K.S. Ong, "Investigation of Range-Energy Relationships for Low Energy Electron Beams in Silicon and GalliumNitride", accepted, Scanning, 2007.Y. J. Yu and Y. C. Lim, "Design of Linear Phase FIR Filters in Subexpression Space Using Mixed Integer Linear Programming", IEEE Trans.on Circuits and Systems, Part I, vol 54, no. 10, pp. 2330 - 2338, October 2007.Y. C. Lim, Y. J. Yu, T. Saramäki and K. L. Teo, "FRM Based FIR Filters with Optimum Finite Word Length Performance", IEEE Trans. on SignalProcessing, vol. 55, pp. 2914 - 2924, June 2007.Y. J. Yu and Y. C. Lim, "Roundoff Noise Analysis of Signals Represented Using Signed Power-of-Two Terms", IEEE Trans. on SignalProcessing, vol. 55, pp. 2122 - 2135, May 2007.[ Nanyang Technological University • School of Electrical & Electronic Engineering ]

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