ARCHIVE 2009 - BiTS Workshop

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2009Session 3Adventures in Test & Burn-in OperationsParallel Logic TestInterface SolutionsYH Jeon, TSESang-Il Kwon, TSEChris Mack, PragmaticsGary Westendorf, Pragmatics2009 BiTS WorkshopMarch 8 - 11, 2009Contents• Welcome & Introductions• Why We Chose This Subject• Enabling Technologies• Logic / SOC Test Interfaces• Fan-Out Methodologies• Fan-Out Signal Performance• Considerations• Conclusion3/2009 Parallel Logic Test Interface Solutions2Paper #1March 8 - 11, 20091
2009Session 3Adventures in Test & Burn-in OperationsWhy We Chose This Subject…• Lessons learned from years ofproducing high parallel memory &MCP test interfaces are being appliedto production Logic / SOC testing.• Economics often require Logic / SOCproduction test without new capitalspending on ATE.• The real estate inside parallel testinterfaces can be utilized to expandATE resources.• There are more Logic / SOC devicesemerging that require high volumeproduction.3/2009 Parallel Logic Test Interface Solutions3Enabling Technologies• Increasing density ATE PEs & interconnects.• DFT/BIST/SCAN reduces ATE I/O requirements.• Logic load boards are transitioning to paralleltest interfaces with real estate for fan-outcircuitry & additional DUT power supplies.• Advancements in lithography & packagingprovides denser, smaller Logic / SOC devicesthat can be handled by memory test handlers.3/2009 Parallel Logic Test Interface Solutions4Paper #1March 8 - 11, 20092
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ARCHIVE 2009 - BiTS Workshop

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