UDP/IP Stack product brief

Full Hardware UDP/ IP stackV2.0Product Brief (August 2011 - Rev A)FeaturesFull Hardware UDP / IP / Ethernet stack• Drop-in module for Spartan(tm)-3A/Spartan(tm)-6/ Virtex(tm)-4/ Virtex(tm)-5/Virtex(tm)-6/ Virtex(tm)-7 / Kintex(tm)-7 XilinxFPGAs• Ethernet 100/1000• Supported protocols :• IPv4• UDP• ARP (request/reply)• ICMP (Ping reply / Trace route)• IGMPv2 (option)• DHCP client (option)• UDP port filtering• Unicast and broadcast• CRC32 Ethernet validations• IP/UDP checksums validations• Number of UDP Output Channel dependingfrom Ethernet speed connection andcustomer requirement.• Programmable MAC FPGA and static IP FPGAaddresses• Programmable UDP destination and sourceports (TX)• Management of ARP table up to Number ofUDP output• Jumbo frames up to 9kB(option)• IPv4 fragmentation not supported• Netlist version available for ISE 12.2 and layerApplicationsMVD Hardware UDP / IP stack may be used inapplications related to Ethernet transmission with XilinxTechnology.DescriptionThe UDP/IP core is a drop-in module that includes thefollowing functions :• Reception – Emission of IP / UDP datagram• Checksum computation of Ethernet, IP and UDPlayers (Emission and Reception)• Frames with bad checksum are not decrypted• Non-support of fragmented IP datagram• UDP Port filtering (ports number 1024 to 65535may be used for applications).• Ports 67 – 68 reserved to DHCP protocol.• For applications which used port numbers 1 to1023, please ask MVD.ARPLayerICMPProtocolDHCPProtocol16Port_udpEthernetRX/TXEthernetLayerIP LayerUDPLayer8Data_udp 8Data_en_udpSend_data8 Data_udp_to_txTransmit_udpApplicationLayer(*)(**)ApplicationLayer(*)(**)(*) Application layer not included in the core(**) Application layer can be: FIFO, MVD Modulators, top layer protocol over UDP such as RTP etc.106, avenue des guis – 31830 Plaisance du Touch – FranceTel: +33 (0) 5 62 13 52 32 – Fax: +33 (0) 5 61 06 72 60E-mail: info_cores@mvd-fpga.com – Web: www.mvd-fpga.com

Resource Utilization (*)Slices BRAMs (18k) (**) MULT BUFGor DSP48Spartan 3 TM 2 800 5 0 3Spartan 6 TM 1 280 5 0 3Virtex 4 TM 2 800 5 0 3Virtex 5 TM 1 500 5 0 3Virtex 6 TM 1 170 5 0 3( These values may vary depending on implementation options)Deliverables :Datasheet and user’s guideNetlist for core generation(*) Values given for Rx_Tx_DHCP version plus one UDP output channel.(**) BRAMs to write data in reception or to send data in emission are not take into account.Ordering information and related coresDesignationMVD_UDP_IP_RX_NETMVD_UDP_IP_RX_DHCP_NETMVD_UDP_IP_TX_NETMVD_UDP_IP_TX_DHCP_NETMVD_UDP_IP_RX_TX_NETMVD_UDP_IP_RX_TX_DHCP_NETVersionReceiverReceiver + DHCPTransmitterTransmitter + DHCPReceiver + TransmitterReceiver + Transmitter + DHCPThese cores are all CPU programmable.VHDL source code: Can be delivered as an option under NDA and other specific clauses.Companion cores: Serial Interface for CPU configuration.Related cores: ASI receiver, MVD modulators…Documentation and support: Datasheet and user’s guide. In addition MVD can provide on site or remotecoaching.Please contact us at info_cores@mvd-fpga.com for more information.106, avenue des guis – 31830 Plaisance du Touch – FranceTel: +33 (0) 5 62 13 52 32 – Fax: +33 (0) 5 61 06 72 60E-mail: info_cores@mvd-fpga.com – Web: www.mvd-fpga.com